diff --git a/group/tftf-l2-fvp/fvp-sme,fvp-cpu-extensions:fvp-tftf-fip.tftf-aemv8a.sme-debug b/group/tftf-l2-fvp/fvp-sme,fvp-cpu-extensions:fvp-tftf-fip.tftf-aemv8a.sme-debug
new file mode 100644
index 0000000..b8939c8
--- /dev/null
+++ b/group/tftf-l2-fvp/fvp-sme,fvp-cpu-extensions:fvp-tftf-fip.tftf-aemv8a.sme-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2022, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/model/base-aemva-common.sh b/model/base-aemva-common.sh
index 77b64eb..ed11766 100644
--- a/model/base-aemva-common.sh
+++ b/model/base-aemva-common.sh
@@ -52,6 +52,8 @@
 
 reset_var sve_plugin
 
+reset_var has_sme
+
 reset_var bmcov_plugin
 
 reset_var retain_flash
@@ -110,6 +112,7 @@
 ${sve_plugin+--plugin=$sve_plugin_path}
 ${sve_plugin+-C SVE.ScalableVectorExtension.enable_at_reset=0}
 ${sve_plugin+-C SVE.ScalableVectorExtension.veclen=$((128 / 8))}
+${has_sme+-C SVE.ScalableVectorExtension.has_sme=1}
 
 ${bmcov_plugin+--plugin=$bmcov_plugin_path}
 
@@ -305,6 +308,13 @@
 EOF
 fi
 
+if [ "$arch_version" = "9.2" ]; then
+	cat <<EOF >>"$model_param_file"
+-C cluster0.has_arm_v9-2=1
+-C cluster1.has_arm_v9-2=1
+EOF
+fi
+
 # Parameters for fault injection
 if [ "$fault_inject" = "1" ]; then
 	cat <<EOF >>"$model_param_file"
diff --git a/run_config/fvp-aemv8a.sme b/run_config/fvp-aemv8a.sme
new file mode 100644
index 0000000..f9cfcd9
--- /dev/null
+++ b/run_config/fvp-aemv8a.sme
@@ -0,0 +1,15 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2022, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+	local model="base-aemv8a"
+
+	model="$model" \
+		sve_plugin="1" has_sme="1" arch_version="9.2" \
+		gen_model_params
+	model="$model" gen_fvp_yaml
+}
diff --git a/tf_config/fvp-sme b/tf_config/fvp-sme
new file mode 100644
index 0000000..23cd2a2
--- /dev/null
+++ b/tf_config/fvp-sme
@@ -0,0 +1,8 @@
+CROSS_COMPILE=aarch64-none-elf-
+PLAT=fvp
+ENABLE_FEAT_HCX=1
+CTX_INCLUDE_AARCH32_REGS=0
+ARM_ARCH_MAJOR=8
+ARM_ARCH_MINOR=6
+ENABLE_SVE_FOR_NS=1
+ENABLE_SME_FOR_NS=1