| commit | 2952a142d7c78935d2a1b5bd22fa8f645756bdb8 | [log] [tgz] |
|---|---|---|
| author | Manish Pandey <manish.pandey2@arm.com> | Mon Nov 15 13:03:50 2021 +0000 |
| committer | Manish Pandey <manish.pandey2@arm.com> | Tue Nov 16 23:31:01 2021 +0100 |
| tree | 0e60464a3b2d4dbf211e6f6b72262f9860070a0e | |
| parent | 27d11c6eadaa4277ea961b63512f1e57a820462e [diff] |
fix(spm_mm) : build with ENABLE_SVE_FOR_NS=0 With change ID I69dbb272ca681bb020501342008eda20d4c0b096 in TF-A, SPM_MM and ENABLE_SVE_FOR_NS are now incompatible flags. Pass ENABLE_SVE_FOR_NS=0 when building SPM_MM Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ifebce4f0ec6edd581e1221c47db1d20c981bd849
diff --git a/tf_config/fvp-spm-mm b/tf_config/fvp-spm-mm index 9a79384..1d146b6 100644 --- a/tf_config/fvp-spm-mm +++ b/tf_config/fvp-spm-mm
@@ -1,5 +1,6 @@ ARM_BL31_IN_DRAM=1 CROSS_COMPILE=aarch64-none-elf- EL3_EXCEPTION_HANDLING=1 +ENABLE_SVE_FOR_NS=0 SPM_MM=1 PLAT=fvp
diff --git a/tf_config/fvp-spm-mm-cc b/tf_config/fvp-spm-mm-cc index b0e5a35..a3d5fcc 100644 --- a/tf_config/fvp-spm-mm-cc +++ b/tf_config/fvp-spm-mm-cc
@@ -2,5 +2,6 @@ CROSS_COMPILE=aarch64-none-elf- EL3_EXCEPTION_HANDLING=1 ENABLE_ASSERTIONS=0 +ENABLE_SVE_FOR_NS=0 SPM_MM=1 PLAT=fvp