commit 40e5be98b3e227d74d0a26b2827f96c0b97de8c0
author Sona Mathew <SonaRebecca.Mathew@arm.com> Thu Aug 10 16:31:45 2023 -0500
committer Sona Mathew <SonaRebecca.Mathew@arm.com> Tue Aug 15 16:00:24 2023 -0500
tree d442c195cb348f9fdf1404db8bbaf1b3922535e4
parent b5002ace28fb21118ac4442483b6bdf3fe74eb99

fix: increase TSRAM of 'fvp-tbb-mbedtls-bl2-el3'

This build job is currently failing the errata framework
based cpu conversion patches due to lack of available
SRAM.

Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>
Change-Id: Ied03ad8dc5ecdf1f84f91ae737122176042800f0

script/tf-coverity/tf-cov-make

diff --git a/script/tf-coverity/tf-cov-make b/script/tf-coverity/tf-cov-make
index 43256e8..9c79bc4 100755
--- a/script/tf-coverity/tf-cov-make
+++ b/script/tf-coverity/tf-cov-make
@@ -53,7 +53,7 @@
 clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram \
     SPD=tspd FVP_TRUSTED_SRAM_SIZE=384
 clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} ARM_TSP_RAM_LOCATION=dram SPD=tspd TSP_INIT_ASYNC=1 \
-    TSP_NS_INTR_ASYNC_PREEMPT=1
+    TSP_NS_INTR_ASYNC_PREEMPT=1 FVP_TRUSTED_SRAM_SIZE=384
 clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed FVP_TRUSTED_SRAM_SIZE=384
 clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=tlkd FVP_TRUSTED_SRAM_SIZE=384
 clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=pncd SPD_PNCD_NS_IRQ=126 \