#!/usr/bin/env bash
#
# Copyright (c) 2021-2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#

generate_lava_job_template() {
	payload_type="tftf" gen_yaml_template
}

generate_lava_job() {
	local model="base-aemv8a"

	# RME systems go BL1->BL2->BL31 so we must set this variable for expect
	# scripts to work properly and not hang up waiting for BL1->BL31.
	uart="0" set_expect_variable "skip_early_boot_msgs" "1"

	# Use standard TFTF expect script on primary UART.
	uart="0" file="tftf.exp" track_expect

	# Track the rest of the UARTs to aid in debugging.
	uart="1" file="hold_uart.exp" track_expect
	uart="2" file="hold_uart.exp" track_expect
	uart="3" file="hold_uart.exp" track_expect

	# For RME test configs, bp.secure_memory=0 and bp.has_rme=1 imply:
	# TZ access controls disabled.
	# RME access controls enabled.
	# Only Root access to Trusted ROM and SRAM.
	# SECURE/ROOT access only for below peripherals:
	# -Trusted DRAM
	# -REFCLK CNTControl (Generic Timer)
	# -Trusted Watchdog SP805, Trustzone address space controller
	# -AP_REFCLK CNTBase0 (Generic Timer)
	# -Trusted RNG, Non-Volatile Counter and Root-Key Storage
	# -Flash0, Flash1
	# -uart0, uart1, uart2, uart3

	model="$model" \
		secure_memory="0" \
		has_rme="1" \
		amu_present="1" \
		arch_version="9.2" \
		has_branch_target_exception="1" \
		has_smmuv3_params="1" \
		memory_tagging_support_level="2" \
		restriction_on_speculative_execution="2" \
		gicd_are_fixed_one="1" \
		gicv3_ext_interrupt_range="1" \
		gicd_ext_ppi_count="64" \
		gicd_ext_spi_count="1024" \
		gen_model_params

	model="$model" gen_fvp_yaml
}