| commit | 52c8ba34212b03f22a1f40068c1040116e344bf7 | [log] [tgz] |
|---|---|---|
| author | Olivier Deprez <olivier.deprez@arm.com> | Fri May 13 18:30:25 2022 +0200 |
| committer | Olivier Deprez <olivier.deprez@arm.com> | Tue May 17 14:53:22 2022 +0200 |
| tree | 238246ab657d3a488431d93eec5b16aa4453bfc7 | |
| parent | 368523d87fe0ec3c17659d79500abbf50a4a84c6 [diff] |
fix(spm-mm): tf config update to enable FP/SIMD Per introduction of [1], update SPM-MM tf build configurations to enable CTX_INCLUDE_FPREGS=1 to permit saving/restoring the normal world context on world switches. This is a security measure beyond the recommendation for SPs to save/restore the FP/SIMD context [2]. [1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/15167 [2] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/services/std_svc/spm_mm/spm_mm_setup.c?h=v2.6#n186 Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I7243f64799b56edcb2b19c0ca1ed0bee79288bce
diff --git a/tf_config/fvp-spm-mm b/tf_config/fvp-spm-mm index 1d146b6..47df74e 100644 --- a/tf_config/fvp-spm-mm +++ b/tf_config/fvp-spm-mm
@@ -1,5 +1,6 @@ ARM_BL31_IN_DRAM=1 CROSS_COMPILE=aarch64-none-elf- +CTX_INCLUDE_FPREGS=1 EL3_EXCEPTION_HANDLING=1 ENABLE_SVE_FOR_NS=0 SPM_MM=1
diff --git a/tf_config/fvp-spm-mm-cc b/tf_config/fvp-spm-mm-cc index a3d5fcc..8cdfdc1 100644 --- a/tf_config/fvp-spm-mm-cc +++ b/tf_config/fvp-spm-mm-cc
@@ -1,5 +1,6 @@ ARM_BL31_IN_DRAM=1 CROSS_COMPILE=aarch64-none-elf- +CTX_INCLUDE_FPREGS=1 EL3_EXCEPTION_HANDLING=1 ENABLE_ASSERTIONS=0 ENABLE_SVE_FOR_NS=0
diff --git a/tf_config/synquacer-spm b/tf_config/synquacer-spm index a32a8bb..c9e9464 100644 --- a/tf_config/synquacer-spm +++ b/tf_config/synquacer-spm
@@ -1,4 +1,5 @@ CROSS_COMPILE=aarch64-none-elf- +CTX_INCLUDE_FPREGS=1 EL3_EXCEPTION_HANDLING=1 SPM_MM=1 PLAT=synquacer