Enable cache modelling for fvp-aemv8a.quad model
Linux kernel boot failed with cache modelling enabled in
fvp-aemv8a.quad model hence we disabled the cache modelling
on this FVP model as workaround.
After investigation, we found that U-boot supports only cache
coherent interconnects CCN-400 and CCN-504, but not CCN-502,
and hence U-boot fails to boot the Linux kernel as it can not
perform CCN-502 L3 cache operations.
Hence passed extra parameter to this FVP model i.e.
"ccn502.cache_size_in_kbytes=0" to disable only L3 cache.
and enable back the cache state modelling. (to enable other cache
support in the model)
Also, this patch adds a config to test this FVP model with TFTF.
Change-Id: Icc6061341788f64e8abad6aa306611b3a3983c56
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
diff --git a/run_config/fvp-aemv8a.quad b/run_config/fvp-aemv8a.quad
index 13c11e6..7f1d458 100644
--- a/run_config/fvp-aemv8a.quad
+++ b/run_config/fvp-aemv8a.quad
@@ -7,7 +7,7 @@
post_fetch_tf_resource() {
model="base-aemv8a-quad" \
- cache_state_modelled="0" \
+ ccn502_cache_size_in_kbytes="0" \
gen_model_params
uart="0" set_expect_variable "num_cpus" "16"
}