Sync test groups with internal CI
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
Change-Id: I8bf270aaee4607c97b2706dd87328e8566be0261
diff --git a/group/tf-l3-boot-tests-misc/fvp-aarch32-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.nocache-debug b/group/tf-l3-boot-tests-misc/fvp-aarch32-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.nocache-debug
new file mode 100644
index 0000000..1e513d8
--- /dev/null
+++ b/group/tf-l3-boot-tests-misc/fvp-aarch32-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.nocache-debug
@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Cache state modelling is disabled for this test as this particular TBBR config
+# thrashes the I-cache hard, leading to ~60% of CPU time spent in the host kernel
+# switching the pages responsible for the I-cache from writable to executable and
+# back again.