diff --git a/group/spm-l3-boot-tests/fvp-default,fvp-ras-ffh-spmd-lsp,fvp-single-fault:fvp-spm.fi-debug b/group/spm-l3-boot-tests/fvp-default,fvp-ras-ffh-spmd-lsp,fvp-single-fault:fvp-spm.fi-debug
new file mode 100644
index 0000000..19363ec
--- /dev/null
+++ b/group/spm-l3-boot-tests/fvp-default,fvp-ras-ffh-spmd-lsp,fvp-single-fault:fvp-spm.fi-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2024 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/run_config/fvp-spm.fi b/run_config/fvp-spm.fi
new file mode 100644
index 0000000..9d332d2
--- /dev/null
+++ b/run_config/fvp-spm.fi
@@ -0,0 +1,37 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2024, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+	build_fip BL33="$archive/tftf.bin" BL32="$archive/secure_hafnium.bin"
+}
+
+generate_lava_job_template() {
+	payload_type="tftf" gen_yaml_template
+}
+
+generate_lava_job() {
+	local model="base-aemv8a"
+
+	uart="0" file="tftf.exp" track_expect
+	uart="1" file="hold_uart.exp" track_expect
+	uart="2" file="spm-uart2.exp" track_expect
+
+	# Enable fault injection
+	model="$model" \
+		arch_version="8.5" \
+		has_branch_target_exception="1" \
+		has_smmuv3_params="1" \
+		memory_tagging_support_level="2" \
+		gicd_are_fixed_one="1" \
+		gicv3_ext_interrupt_range="1" \
+		gicd_ext_ppi_count="64" \
+		gicd_ext_spi_count="1024" \
+		fault_inject="1" \
+		gen_model_params
+
+	model="$model" gen_fvp_yaml
+}
diff --git a/tf_config/fvp-ras-ffh-spmd-lsp b/tf_config/fvp-ras-ffh-spmd-lsp
new file mode 100644
index 0000000..fed64c1
--- /dev/null
+++ b/tf_config/fvp-ras-ffh-spmd-lsp
@@ -0,0 +1,16 @@
+CROSS_COMPILE=aarch64-none-elf-
+PLAT=fvp
+SPD=spmd
+ENABLE_SPMD_LP=1
+ARM_ARCH_MINOR=5
+CTX_INCLUDE_PAUTH_REGS=1
+ENABLE_FEAT_MTE=1
+BRANCH_PROTECTION=1
+SP_LAYOUT_FILE=${tftf_root}/build/fvp/${bin_mode}/sp_layout.json
+GIC_EXT_INTID=1
+ENABLE_FEAT_RAS=1
+EL3_EXCEPTION_HANDLING=1
+FAULT_INJECTION_SUPPORT=1
+HANDLE_EA_EL3_FIRST_NS=1
+SDEI_SUPPORT=1
+PLATFORM_TEST_FFH_LSP_RAS_SP=1