commit 8b8cd3e7f59bed667f0c4824887b07cdaa8166ab
author Harrison Mutai <harrison.mutai@arm.com> Mon Jun 06 12:40:13 2022 +0100
committer Olivier Deprez <olivier.deprez@arm.com> Thu Jun 16 14:27:36 2022 +0200
tree a7b1f4fd5864e79d64621ef37aee821ad49d8e68
parent edf25d9385f1edef36d2b9b39ae7363b216dad36

fvp: modify TLB size and memory protection

Increase the number of stage 1 and 2 TLB entries, and remove memory
attribute checks. This improves performance in tests that rely heavily
on memory operations. For reference, a ~10% performance uplift is
observed with the tftf-l2-reboot test suite.

Change-Id: I4b66a574fd1609de238c5e5f409c7a1a2c3444eb
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

model/base-aemva-common.sh

diff --git a/model/base-aemva-common.sh b/model/base-aemva-common.sh
index f6dabe2..9afec2e 100644
--- a/model/base-aemva-common.sh
+++ b/model/base-aemva-common.sh
@@ -204,6 +204,9 @@
 ${supports_crc32+-C cluster0.cpu2.enable_crc32=$supports_crc32}
 ${supports_crc32+-C cluster0.cpu3.enable_crc32=$supports_crc32}
 
+${cache_state_modelled+-C cluster0.stage12_tlb_size=1024}
+${cache_state_modelled+-C cluster0.check_memory_attributes=0}
+
 EOF
 
 if [ "$has_smmuv3_params" = "1" ]; then
@@ -389,6 +392,9 @@
 ${supports_crc32+-C cluster1.cpu2.enable_crc32=$supports_crc32}
 ${supports_crc32+-C cluster1.cpu3.enable_crc32=$supports_crc32}
 
+${cache_state_modelled+-C cluster1.stage12_tlb_size=1024}
+${cache_state_modelled+-C cluster1.check_memory_attributes=0}
+
 EOF
 
 # Parameters to select architecture version