Add Hafnium code coverage configurations
Signed-off-by: Saul Romero <saul.romero@arm.com>
Change-Id: I43d76ce35246e20668f68d955b91c8bf04e6514d
diff --git a/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm,fvp-48bit-pa:fvp-spm.48bit_pa.bmcov-debug b/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm,fvp-48bit-pa:fvp-spm.48bit_pa.bmcov-debug
new file mode 100644
index 0000000..8c2d647
--- /dev/null
+++ b/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm,fvp-48bit-pa:fvp-spm.48bit_pa.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm,fvp-ivy-vhe:fvp-spm.bmcov-debug b/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm,fvp-ivy-vhe:fvp-spm.bmcov-debug
new file mode 100644
index 0000000..ca6c54c
--- /dev/null
+++ b/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm,fvp-ivy-vhe:fvp-spm.bmcov-debug
@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+pre_spm_build() {
+ # Hafnium build repo containing Sercure hafnium binary build for vhe
+ out_dir="secure_aem_v8a_fvp_vhe_clang" set_spm_out_dir
+}
diff --git a/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-measured-boot,fvp-default:fvp-spm+romlib.bmcov-debug b/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-measured-boot,fvp-default:fvp-spm+romlib.bmcov-debug
new file mode 100644
index 0000000..c473896
--- /dev/null
+++ b/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-measured-boot,fvp-default:fvp-spm+romlib.bmcov-debug
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-rme,fvp-default:fvp-spm.trp.tftf-tftf.rme.bmcov-debug b/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-rme,fvp-default:fvp-spm.trp.tftf-tftf.rme.bmcov-debug
new file mode 100644
index 0000000..5515958
--- /dev/null
+++ b/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-rme,fvp-default:fvp-spm.trp.tftf-tftf.rme.bmcov-debug
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-rme,fvp-invalid-access:fvp-spm.trp.tftf-tftf.rme.bmcov-debug b/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-rme,fvp-invalid-access:fvp-spm.trp.tftf-tftf.rme.bmcov-debug
new file mode 100644
index 0000000..5515958
--- /dev/null
+++ b/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-rme,fvp-invalid-access:fvp-spm.trp.tftf-tftf.rme.bmcov-debug
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-sve,fvp-default-sve:fvp-spm.sve+amu.bmcov-debug b/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-sve,fvp-default-sve:fvp-spm.sve+amu.bmcov-debug
new file mode 100644
index 0000000..8c2d647
--- /dev/null
+++ b/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-sve,fvp-default-sve:fvp-spm.sve+amu.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-tbb,fvp-default:fvp-spm+romlib.bmcov-debug b/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-tbb,fvp-default:fvp-spm+romlib.bmcov-debug
new file mode 100644
index 0000000..8c2d647
--- /dev/null
+++ b/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-tbb,fvp-default:fvp-spm+romlib.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-tbb-dualroot,fvp-default:fvp-spm+romlib.bmcov-debug b/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-tbb-dualroot,fvp-default:fvp-spm+romlib.bmcov-debug
new file mode 100644
index 0000000..8c2d647
--- /dev/null
+++ b/group/spm-l2-boot-tests-code-coverage/fvp-default,fvp-spm-tbb-dualroot,fvp-default:fvp-spm+romlib.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/spm-l2-boot-tests-code-coverage/fvp-disable_assertions,fvp-spm,fvp-default:fvp-spm.bmcov-debug b/group/spm-l2-boot-tests-code-coverage/fvp-disable_assertions,fvp-spm,fvp-default:fvp-spm.bmcov-debug
new file mode 100644
index 0000000..8c2d647
--- /dev/null
+++ b/group/spm-l2-boot-tests-code-coverage/fvp-disable_assertions,fvp-spm,fvp-default:fvp-spm.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/run_config/fvp-spm+romlib.bmcov b/run_config/fvp-spm+romlib.bmcov
new file mode 100644
index 0000000..d6a90e4
--- /dev/null
+++ b/run_config/fvp-spm+romlib.bmcov
@@ -0,0 +1,44 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ fvp_romlib_runtime
+ build_fip BL33="$archive/tftf.bin" BL32="$archive/secure_hafnium.bin"
+}
+
+post_tf_archive() {
+ fvp_romlib_cleanup
+}
+
+generate_lava_job_template() {
+ payload_type="tftf" gen_yaml_template
+}
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ uart="0" file="tftf.exp" track_expect
+ uart="2" file="spm-uart2.exp" track_expect
+
+ # SPM(reference implementation of S-EL2 firmware) has SMMUv3 driver
+ # enabled to help with stage-2 translation and virtualization of
+ # upstream peripheral devices. Hence, enable the SMMUv3 IP in FVP
+ # by configuring the appropriate parameters of the SMMUv3 AEM.
+ if ! is_arm_jenkins_env && not_upon "$local_ci"; then
+ bmcov_plugin_path="${coverage_trace_plugin}"
+ bmcov_plugin="1"
+ fi
+
+ model="$model" \
+ arch_version="8.5" \
+ has_branch_target_exception="1" \
+ has_smmuv3_params="1" \
+ memory_tagging_support_level="2" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-spm-tftf.rme.bmcov b/run_config/fvp-spm-tftf.rme.bmcov
new file mode 100644
index 0000000..bd6b5c2
--- /dev/null
+++ b/run_config/fvp-spm-tftf.rme.bmcov
@@ -0,0 +1,43 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job_template() {
+ payload_type="tftf" gen_yaml_template
+}
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ # RME systems go BL1->BL2->BL31 so we must set this variable for expect
+ # scripts to work properly and not hang up waiting for BL1->BL31.
+ uart="0" set_expect_variable "skip_early_boot_msgs" "1"
+
+ # Use standard TFTF expect script on primary UART.
+ uart="0" file="tftf.exp" track_expect
+
+ # Track the rest of the UARTs to aid in debugging.
+ uart="1" file="hold_uart.exp" track_expect
+ uart="2" file="hold_uart.exp" track_expect
+ uart="3" file="hold_uart.exp" track_expect
+
+ if ! is_arm_jenkins_env && not_upon "$local_ci"; then
+ bmcov_plugin_path="${coverage_trace_plugin}"
+ bmcov_plugin="1"
+ fi
+
+ model="$model" \
+ amu_present="1" \
+ arch_version="8.6" \
+ has_branch_target_exception="1" \
+ has_rme="1" \
+ has_smmuv3_params="1" \
+ memory_tagging_support_level="2" \
+ restriction_on_speculative_execution="2" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-spm.48bit_pa.bmcov b/run_config/fvp-spm.48bit_pa.bmcov
new file mode 100644
index 0000000..90657b9
--- /dev/null
+++ b/run_config/fvp-spm.48bit_pa.bmcov
@@ -0,0 +1,40 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2022-2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ build_fip BL33="$archive/tftf.bin" BL32="$archive/secure_hafnium.bin"
+}
+
+generate_lava_job_template() {
+ payload_type="tftf" gen_yaml_template
+}
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ uart="0" file="tftf.exp" track_expect
+ uart="2" file="spm-uart2.exp" track_expect
+
+ # SPM(reference implementation of S-EL2 firmware) has SMMUv3 driver
+ # enabled to help with stage-2 translation and virtualization of
+ # upstream peripheral devices. Hence, enable the SMMUv3 IP in FVP
+ # by configuring the appropriate parameters of the SMMUv3 AEM.
+ if ! is_arm_jenkins_env && not_upon "$local_ci"; then
+ bmcov_plugin_path="${coverage_trace_plugin}"
+ bmcov_plugin="1"
+ fi
+
+ model="$model" \
+ arch_version="8.5" \
+ has_branch_target_exception="1" \
+ has_smmuv3_params="1" \
+ memory_tagging_support_level="2" \
+ pa_size="48" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-spm.bmcov b/run_config/fvp-spm.bmcov
new file mode 100644
index 0000000..8591fb8
--- /dev/null
+++ b/run_config/fvp-spm.bmcov
@@ -0,0 +1,39 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2020-2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ build_fip BL33="$archive/tftf.bin" BL32="$archive/secure_hafnium.bin"
+}
+
+generate_lava_job_template() {
+ payload_type="tftf" gen_yaml_template
+}
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ uart="0" file="tftf.exp" track_expect
+ uart="2" file="spm-uart2.exp" track_expect
+
+ # SPM(reference implementation of S-EL2 firmware) has SMMUv3 driver
+ # enabled to help with stage-2 translation and virtualization of
+ # upstream peripheral devices. Hence, enable the SMMUv3 IP in FVP
+ # by configuring the appropriate parameters of the SMMUv3 AEM.
+ if ! is_arm_jenkins_env && not_upon "$local_ci"; then
+ bmcov_plugin_path="${coverage_trace_plugin}"
+ bmcov_plugin="1"
+ fi
+
+ model="$model" \
+ arch_version="8.5" \
+ has_branch_target_exception="1" \
+ has_smmuv3_params="1" \
+ memory_tagging_support_level="2" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-spm.optee.sp.bmcov b/run_config/fvp-spm.optee.sp.bmcov
new file mode 100644
index 0000000..70261f3
--- /dev/null
+++ b/run_config/fvp-spm.optee.sp.bmcov
@@ -0,0 +1,49 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2020-2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ url="$tfa_downloads/spm/07-29-2021/spmc_sel2_optee_sel1.bin" fetch_file
+
+ archive_file "spmc_sel2_optee_sel1.bin"
+ cp "${archive}/spmc_sel2_optee_sel1.bin" "${tf_root}/build/fvp/${bin_mode}"
+
+ cat <<-EOF >"${tf_root}/build/fvp/${bin_mode}/optee_sp_layout.json"
+ {
+ "op-tee" : {
+ "image": "spmc_sel2_optee_sel1.bin",
+ "pm": "${tf_root}/plat/arm/board/fvp/fdts/optee_sp_manifest.dts"
+ }
+ }
+ EOF
+
+ build_fip BL33="$archive/tftf.bin" BL32="$archive/secure_hafnium.bin"
+}
+
+generate_lava_job_template() {
+ payload_type="tftf" gen_yaml_template
+}
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ uart="0" file="tftf.exp" track_expect
+ uart="1" file="spm-optee-sp-uart1.exp" track_expect
+
+ if ! is_arm_jenkins_env && not_upon "$local_ci"; then
+ bmcov_plugin_path="${coverage_trace_plugin}"
+ bmcov_plugin="1"
+ fi
+
+ model="$model" \
+ arch_version="8.5" \
+ has_branch_target_exception="1" \
+ has_smmuv3_params="1" \
+ memory_tagging_support_level="2" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-spm.sve+amu.bmcov b/run_config/fvp-spm.sve+amu.bmcov
new file mode 100644
index 0000000..8e21c19
--- /dev/null
+++ b/run_config/fvp-spm.sve+amu.bmcov
@@ -0,0 +1,42 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ build_fip BL33="$archive/tftf.bin" BL32="$archive/secure_hafnium.bin"
+}
+
+generate_lava_job_template() {
+ payload_type="tftf" gen_yaml_template
+}
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ uart="0" file="tftf.exp" track_expect
+ uart="1" file="hold_uart.exp" track_expect
+ uart="2" file="spm-uart2.exp" track_expect
+
+ # SPM(reference implementation of S-EL2 firmware) has SMMUv3 driver
+ # enabled to help with stage-2 translation and virtualization of
+ # upstream peripheral devices. Hence, enable the SMMUv3 IP in FVP
+ # by confuguring the appropriate parameters of the SMMUv3 AEM.
+ if ! is_arm_jenkins_env && not_upon "$local_ci"; then
+ bmcov_plugin_path="${coverage_trace_plugin}"
+ bmcov_plugin="1"
+ fi
+
+ model="$model" \
+ amu_present="1" \
+ arch_version="8.5" \
+ has_branch_target_exception="1" \
+ has_smmuv3_params="1" \
+ memory_tagging_support_level="2" \
+ sve_plugin="1" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-spm.trp.tftf.bmcov b/run_config/fvp-spm.trp.tftf.bmcov
new file mode 100644
index 0000000..729bc6e
--- /dev/null
+++ b/run_config/fvp-spm.trp.tftf.bmcov
@@ -0,0 +1,30 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# Build TF-A with tf-a-tests, TRP and Hafnium
+post_tf_build() {
+ # Stash the TRP binary
+ archive_file "${tf_root}/build/fvp/${bin_mode}/rmm.bin"
+
+ build_fip BL33="$archive/tftf.bin" BL32="$archive/secure_hafnium.bin" \
+ RMM="$archive/rmm.bin"
+}
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ if ! is_arm_jenkins_env && not_upon "$local_ci"; then
+ bmcov_plugin_path="${coverage_trace_plugin}"
+ bmcov_plugin="1"
+ fi
+
+ model="$model" \
+ arch_version="8.5" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}