Code Coverage: Creating weekly run
Change-Id: Ia22b01b57af58833b3fb0cb5355b3e1287f9cbdb
Signed-off-by: mardyk01 <mark.dykes@arm.com>
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a_gic600ae.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a_gic600ae.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a_gic600ae.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.etm_trace_ext.bmcov b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.etm_trace_ext.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.etm_trace_ext.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-xlat-v2:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-xlat-v2:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-default-cc,fvp-aarch32-xlat-v2:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.amu.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-enable-runtime-instr-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemva.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_3.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_6.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_6.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-mtpmu-disable-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.8_6.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-roxlattables-cc,fvp-aarch32-default:fvp-tftf-fip.tftf-aemv8a.aarch32.roxlattables.spmin_panic.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-roxlattables-cc,fvp-aarch32-default:fvp-tftf-fip.tftf-aemv8a.aarch32.roxlattables.spmin_panic.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-roxlattables-cc,fvp-aarch32-default:fvp-tftf-fip.tftf-aemv8a.aarch32.roxlattables.spmin_panic.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-sec-int-fconf-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-sec-int-fconf-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-sec-int-fconf-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-dualroot-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-dualroot-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-dualroot-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-dualroot-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-dualroot-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-dualroot-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-ecdsa-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-ecdsa-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-ecdsa-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-rsa-3k-cert-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-rsa-3k-cert-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-rsa-3k-cert-cc,fvp-aarch32-fwu:fvp-tftf.aarch32+fwu-aemv8a.aarch32.NVM_reboot.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.nocache.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.nocache.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch32-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-aarch32-default:fvp-tftf.aarch32-fip.tftf-aemv8a.aarch32.nocache.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-gicr-protection-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch64-gicr-protection-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-gicr-protection-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov b/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-extensive:fvp-tftf-fip.tftf-foundationv8.bmcov b/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-extensive:fvp-tftf-fip.tftf-foundationv8.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-only-cc,fvp-extensive:fvp-tftf-fip.tftf-foundationv8.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-roxlattables-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.roxlattables.bl31_panic.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch64-roxlattables-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.roxlattables.bl31_panic.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-roxlattables-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.roxlattables.bl31_panic.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-roxlattables-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.roxlattables.tspd_panic.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch64-roxlattables-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.roxlattables.tspd_panic.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-roxlattables-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.roxlattables.tspd_panic.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-sdei-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-aarch64-sec-int-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-aarch64-sec-int-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-aarch64-sec-int-fconf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-bl31-separate-nobits-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-bl31-separate-nobits-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-bl31-separate-nobits-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-cas-spinlock-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_3.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-cas-spinlock-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_3.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-cas-spinlock-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_3.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-crash-report-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.runtime_bl31_main_panic.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-crash-report-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.runtime_bl31_main_panic.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-crash-report-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.runtime_bl31_main_panic.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-debugfs-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-debugfs-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-debugfs-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-cpu-extensions:fvp-tftf-fip.tftf-aemv8a.sve.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-cpu-extensions:fvp-tftf-fip.tftf-aemv8a.sve.bmcov-debug
new file mode 100644
index 0000000..5515958
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-cpu-extensions:fvp-tftf-fip.tftf-aemv8a.sve.bmcov-debug
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_7.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_7.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_7.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.amu.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.amu.bmcov-debug
new file mode 100644
index 0000000..8c2d647
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.amu.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.gicv3_spi.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.gicv3_spi.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.gicv3_spi.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a_gic600ae.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a_gic600ae.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a_gic600ae.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa35x4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa35x4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa35x4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-invalid-access:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-invalid-access:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-invalid-access:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti+qarma3.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti+qarma3.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti+qarma3.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_6+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_6+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_6+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-xlat-v2:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-xlat-v2:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-cc,fvp-xlat-v2:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-clang-bfd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-clang-bfd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-clang-bfd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-default-clang-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-default-clang-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-default-clang-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-detect-features-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.arch_features.bmcov b/group/tf-l3-code-coverage-extensive/fvp-detect-features-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.arch_features.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-detect-features-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.arch_features.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ea-ffh-cc,fvp-ea-ffh:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ea-ffh-cc,fvp-ea-ffh:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ea-ffh-cc,fvp-ea-ffh:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-early-d-cache-cc,fvp-default:fvp-tftf-fip.tftf-aem8a.singlecluster.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-early-d-cache-cc,fvp-default:fvp-tftf-fip.tftf-aem8a.singlecluster.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-early-d-cache-cc,fvp-default:fvp-tftf-fip.tftf-aem8a.singlecluster.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-enable-runtime-instr-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ext-pstate-ea-el3-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-gcc-lto-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-gcc-lto-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-gcc-lto-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-gicv4-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.gicv4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-gicv4-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.gicv4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-gicv4-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.gicv4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-gpt-cc,fvp-default:fvp-tftf.gpt-aemv8a.gpt.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-gpt-cc,fvp-default:fvp-tftf.gpt-aemv8a.gpt.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-gpt-cc,fvp-default:fvp-tftf.gpt-aemv8a.gpt.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-hcx-aarch64-only-cc,fvp-hcx:fvp-tftf-fip.tftf-foundationv8.bmcov b/group/tf-l3-code-coverage-extensive/fvp-hcx-aarch64-only-cc,fvp-hcx:fvp-tftf-fip.tftf-foundationv8.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-hcx-aarch64-only-cc,fvp-hcx:fvp-tftf-fip.tftf-foundationv8.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-mb_hash256-tbb_hash256-romlib,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-mb_hash256-tbb_hash256-romlib,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..c473896
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-mb_hash256-tbb_hash256-romlib,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/tf-l3-code-coverage-extensive/fvp-mb_hash256-tbb_hash256-romlib-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-mb_hash256-tbb_hash256-romlib-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-mb_hash256-tbb_hash256-romlib-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-mtpmu-disable-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-mtpmu-disable-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-mtpmu-disable-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-mtpmu-disable-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_6.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-mtpmu-disable-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_6.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-mtpmu-disable-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.8_6.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-brbe-regs-access-cc,fvp-default:fvp-tftf-fip.tftf-aemva.feat_brbe.bl31_panic.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-no-brbe-regs-access-cc,fvp-default:fvp-tftf-fip.tftf-aemva.feat_brbe.bl31_panic.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-brbe-regs-access-cc,fvp-default:fvp-tftf-fip.tftf-aemva.feat_brbe.bl31_panic.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..5515958
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-cohmem-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-optimize-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-no-optimize-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-optimize-default-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-sys-regs-trace-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-no-sys-regs-trace-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-sys-regs-trace-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-trbe-regs-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-no-trbe-regs-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-trbe-regs-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-no-trf-regs-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-no-trf-regs-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-no-trf-regs-access-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-aemva.ete_trace_ext.bl31_panic.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-opteed-aarch64-only-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-foundationv8.bmcov b/group/tf-l3-code-coverage-extensive/fvp-opteed-aarch64-only-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-foundationv8.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-opteed-aarch64-only-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-foundationv8.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.assymetric.bmcov b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.assymetric.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.assymetric.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.bmcov-debug
new file mode 100644
index 0000000..5515958
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.bmcov-debug
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.singlecore.bmcov b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.singlecore.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemv8a.singlecore.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemva.bmcov b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemva.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-aemva.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-cortexa35x4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-cortexa35x4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-cortexa35x4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-cortexa57x4a53x4.bmcov b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-cortexa57x4a53x4.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-opteed-cc,fvp-default:fvp-tftf-optee-fip.tftf+bl32-cortexa57x4a53x4.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-sdei-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-sdei-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-sdei-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-romlib-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-sdei-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-sdei-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-bti-tsp-sdei-cc,fvp-pauth-bti:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-ctx-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-ctx-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-ctx-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-ctx-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-ctx-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-ctx-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-leaf-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-leaf-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-leaf-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-leaf-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-leaf-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-leaf-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-pac-ret-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-romlib-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pauth-standard-tsp-sdei-cc,fvp-pauth-standard:fvp-tftf-fip.tftf-aemv8a.8_5+bti.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-pl33-cc,fvp-default:fvp-tftf-aemv8a.pl33.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-pl33-cc,fvp-default:fvp-tftf-aemv8a.pl33.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-pl33-cc,fvp-default:fvp-tftf-aemv8a.pl33.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ras-ffh-cc,fvp-single-fault:fvp-tftf-fip.tftf-aemv8a.fi.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ras-ffh-cc,fvp-single-fault:fvp-tftf-fip.tftf-aemv8a.fi.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ras-ffh-cc,fvp-single-fault:fvp-tftf-fip.tftf-aemv8a.fi.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ras-ffh-cc,fvp-uncontainable:fvp-tftf.fault-fip.tftf-aemv8a.fi.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ras-ffh-cc,fvp-uncontainable:fvp-tftf.fault-fip.tftf-aemv8a.fi.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ras-ffh-cc,fvp-uncontainable:fvp-tftf.fault-fip.tftf-aemv8a.fi.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-reclaim-init-code-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-reclaim-init-code-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-reclaim-init-code-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-rng-trap-cc,fvp-rng-trap:fvp-tftf-fip.tftf-aemv8a.rng_trap.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-rng-trap-cc,fvp-rng-trap:fvp-tftf-fip.tftf-aemv8a.rng_trap.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-rng-trap-cc,fvp-rng-trap:fvp-tftf-fip.tftf-aemv8a.rng_trap.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.assymetric.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.assymetric.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.assymetric.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.singlecore.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.singlecore.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-spm-mm-cc,fvp-spm-mm:fvp-tftf.cactus_mm-fip.tftf+bl32-aemv8a.singlecore.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.tbb.disable_dyn_auth.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.tbb.disable_dyn_auth.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.tbb.disable_dyn_auth.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-sha512-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-sha512-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-ecdsa-sha512-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-full-dev-rsa-key-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-full-dev-rsa-key-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-full-dev-rsa-key-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-romlib-cot-in-dtb-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-romlib-cot-in-dtb-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-romlib-cot-in-dtb-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-3k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-3k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-3k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-4k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-4k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-4k-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-ecdsa-with-rsa-rotpk-ecdsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-ecdsa-with-rsa-rotpk-ecdsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-rsa-ecdsa-with-rsa-rotpk-ecdsa-cert-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.invalid_nvcounter.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.invalid_nvcounter.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.invalid_nvcounter.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.nvcounter_v1.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.nvcounter_v1.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tbb-mbedtls-upcounter-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.nvcounter_v1.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-default:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-extensive:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-extensive:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-aarch64-only-cc,fvp-extensive:fvp-tftf-fip.tftf-foundationv8.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-aemva.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-default:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.assymetric.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemv8a.singlecore.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemva.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemva.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-aemva.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa35x4.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-cc,fvp-extensive:fvp-tftf-fip.tftf-cortexa57x4a53x4.bmcov-tspd
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-quad-cluster-cc,fvp-4x4:fvp-tftf-fip.tftf-aemv8a.quad.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-quad-cluster-cc,fvp-4x4:fvp-tftf-fip.tftf-aemv8a.quad.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-quad-cluster-cc,fvp-4x4:fvp-tftf-fip.tftf-aemv8a.quad.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov-debug
new file mode 100644
index 0000000..5515958
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov-debug
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemva.bmcov b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemva.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-cc,fvp-fwu:fvp-tftf.fwu-aemva.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-dualroot-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-dualroot-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-dualroot-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-dualroot-cc,fvp-fwu:fvp-tftf.fwu.mbedtls2-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-dualroot-cc,fvp-fwu:fvp-tftf.fwu.mbedtls2-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-dualroot-cc,fvp-fwu:fvp-tftf.fwu.mbedtls2-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-ecdsa-dualroot-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-ecdsa-dualroot-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-ecdsa-dualroot-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-pauth-cc,fvp-fwu-pauth-standard:fvp-tftf.fwu-aemv8a.8_5+bti.bmcov b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-pauth-cc,fvp-fwu-pauth-standard:fvp-tftf.fwu-aemv8a.8_5+bti.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-pauth-cc,fvp-fwu-pauth-standard:fvp-tftf.fwu-aemv8a.8_5+bti.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-pauth-cc,fvp-fwu-pauth-standard:fvp-tftf.fwu-aemv8a.8_5.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-pauth-cc,fvp-fwu-pauth-standard:fvp-tftf.fwu-aemv8a.8_5.bmcov-debug
new file mode 100644
index 0000000..5515958
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-pauth-cc,fvp-fwu-pauth-standard:fvp-tftf.fwu-aemv8a.8_5.bmcov-debug
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-rsa-4k-cert-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-rsa-4k-cert-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tbb-mbedtls-rsa-4k-cert-cc,fvp-fwu:fvp-tftf.fwu-aemv8a.bmcov
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-tspd-tsp-async-ehf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd-debug b/group/tf-l3-code-coverage-extensive/fvp-tspd-tsp-async-ehf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-tspd-tsp-async-ehf-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-tspd-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/group/tf-l3-code-coverage-extensive/fvp-ubsan-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug b/group/tf-l3-code-coverage-extensive/fvp-ubsan-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
new file mode 100644
index 0000000..b452bbf
--- /dev/null
+++ b/group/tf-l3-code-coverage-extensive/fvp-ubsan-cc,fvp-default:fvp-tftf-fip.tftf-aemv8a.bmcov-debug
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/model/base-aemv8a-quad.sh b/model/base-aemv8a-quad.sh
index 0f4272f..d4f41bc 100644
--- a/model/base-aemv8a-quad.sh
+++ b/model/base-aemv8a-quad.sh
@@ -1,6 +1,6 @@
#!/usr/bin/env bash
#
-# Copyright (c) 2019-2022 Arm Limited. All rights reserved.
+# Copyright (c) 2023 Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -26,6 +26,8 @@
-C bp.terminal_2.start_port=5002
-C bp.terminal_3.start_port=5003
+${bmcov_plugin+--plugin=$bmcov_plugin_path}
+
${cluster_0_num_cores+-C cluster0.NUM_CORES=$cluster_0_num_cores}
${cluster_1_num_cores+-C cluster1.NUM_CORES=$cluster_1_num_cores}
${cluster_2_num_cores+-C cluster2.NUM_CORES=$cluster_2_num_cores}
diff --git a/model/cortex-a35x4.sh b/model/cortex-a35x4.sh
index 374d68b..1816ce0 100644
--- a/model/cortex-a35x4.sh
+++ b/model/cortex-a35x4.sh
@@ -1,6 +1,6 @@
#!/usr/bin/env bash
#
-# Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+# Copyright (c) 2023 Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -15,6 +15,8 @@
-C bp.terminal_2.start_port=5002
-C bp.terminal_3.start_port=5003
+${bmcov_plugin+--plugin=$bmcov_plugin_path}
+
${reset_to_spmin+-C cluster0.cpu0.RVBARADDR=${bl32_addr:?}}
${reset_to_spmin+-C cluster0.cpu1.RVBARADDR=${bl32_addr:?}}
${reset_to_spmin+-C cluster0.cpu2.RVBARADDR=${bl32_addr:?}}
diff --git a/model/cortex-a57x4-a53x4.sh b/model/cortex-a57x4-a53x4.sh
index 54d64ea..322cb72 100644
--- a/model/cortex-a57x4-a53x4.sh
+++ b/model/cortex-a57x4-a53x4.sh
@@ -1,6 +1,6 @@
#!/usr/bin/env bash
#
-# Copyright (c) 2019-2020 Arm Limited. All rights reserved.
+# Copyright (c) 2023 Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -15,6 +15,8 @@
-C bp.terminal_2.start_port=5002
-C bp.terminal_3.start_port=5003
+${bmcov_plugin+--plugin=$bmcov_plugin_path}
+
${reset_to_bl31+-C cluster0.cpu0.RVBARADDR=${bl31_addr:?}}
${reset_to_bl31+-C cluster0.cpu1.RVBARADDR=${bl31_addr:?}}
${reset_to_bl31+-C cluster0.cpu2.RVBARADDR=${bl31_addr:?}}
diff --git a/run_config/fvp-aem8a.singlecluster.bmcov b/run_config/fvp-aem8a.singlecluster.bmcov
new file mode 100644
index 0000000..7e52df9
--- /dev/null
+++ b/run_config/fvp-aem8a.singlecluster.bmcov
@@ -0,0 +1,21 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ model="$model" \
+ cluster_0_num_cores="4" \
+ cluster_1_num_cores="0" \
+ cluster_2_num_cores="0" \
+ cluster_3_num_cores="0" \
+ bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.8_3.bmcov b/run_config/fvp-aemv8a.8_3.bmcov
new file mode 100644
index 0000000..3c50e8f
--- /dev/null
+++ b/run_config/fvp-aemv8a.8_3.bmcov
@@ -0,0 +1,15 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ model="$model" arch_version="8.3" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.8_5+bti+qarma3.bmcov b/run_config/fvp-aemv8a.8_5+bti+qarma3.bmcov
new file mode 100644
index 0000000..ea35cc5
--- /dev/null
+++ b/run_config/fvp-aemv8a.8_5+bti+qarma3.bmcov
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ model="${model}" \
+ arch_version="8.5" \
+ has_branch_target_exception="1" \
+ has_pacqarma3="1" \
+ bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+
+ model="${model}" model_bin="FVP_Base_RevC-2xAEMvA" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.8_5+bti.bmcov b/run_config/fvp-aemv8a.8_5+bti.bmcov
new file mode 100644
index 0000000..85f1a0d
--- /dev/null
+++ b/run_config/fvp-aemv8a.8_5+bti.bmcov
@@ -0,0 +1,19 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ model="$model" \
+ arch_version="8.5" \
+ has_branch_target_exception="1" \
+ bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+
+ model="$model" model_bin="FVP_Base_RevC-2xAEMvA" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.8_5.bmcov b/run_config/fvp-aemv8a.8_5.bmcov
index 4bdf969..fc4ef02 100644
--- a/run_config/fvp-aemv8a.8_5.bmcov
+++ b/run_config/fvp-aemv8a.8_5.bmcov
@@ -1,6 +1,6 @@
#!/usr/bin/env bash
#
-# Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+# Copyright (c) 2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/run_config/fvp-aemv8a.8_6+bti.bmcov b/run_config/fvp-aemv8a.8_6+bti.bmcov
new file mode 100644
index 0000000..f53145d
--- /dev/null
+++ b/run_config/fvp-aemv8a.8_6+bti.bmcov
@@ -0,0 +1,23 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ uart="0" set_expect_variable "num_cpus" "4"
+
+ model="$model" \
+ arch_version="8.6" \
+ has_branch_target_exception="1" \
+ bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+
+ model="$model" \
+ model_bin="FVP_Base_RevC-2xAEMvA" \
+ gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.8_6.bmcov b/run_config/fvp-aemv8a.8_6.bmcov
new file mode 100644
index 0000000..5087ff5
--- /dev/null
+++ b/run_config/fvp-aemv8a.8_6.bmcov
@@ -0,0 +1,15 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ model="$model" arch_version="8.6" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" model_bin="FVP_Base_RevC-2xAEMvA" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.8_7.bmcov b/run_config/fvp-aemv8a.8_7.bmcov
new file mode 100644
index 0000000..8798793
--- /dev/null
+++ b/run_config/fvp-aemv8a.8_7.bmcov
@@ -0,0 +1,15 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ model="$model" arch_version="8.7" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.aarch32.8_3.bmcov b/run_config/fvp-aemv8a.aarch32.8_3.bmcov
new file mode 100644
index 0000000..1f32233
--- /dev/null
+++ b/run_config/fvp-aemv8a.aarch32.8_3.bmcov
@@ -0,0 +1,15 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ model="$model" aarch32="1" arch_version="8.3" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.aarch32.8_6.bmcov b/run_config/fvp-aemv8a.aarch32.8_6.bmcov
new file mode 100644
index 0000000..f186b2f
--- /dev/null
+++ b/run_config/fvp-aemv8a.aarch32.8_6.bmcov
@@ -0,0 +1,13 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ model="base-aemv8a" aarch32="1" arch_version="8.6" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="base-aemv8a" model_bin="FVP_Base_RevC-2xAEMvA" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.aarch32.NVM_reboot.bmcov b/run_config/fvp-aemv8a.aarch32.NVM_reboot.bmcov
new file mode 100644
index 0000000..0c236ef
--- /dev/null
+++ b/run_config/fvp-aemv8a.aarch32.NVM_reboot.bmcov
@@ -0,0 +1,43 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_archive() {
+ echo "Creating flash files which serve as Non-volatile Memory across reboots"
+ rm -f "$archive/flash0"
+ rm -f "$archive/flash1"
+ touch "$archive/flash0"
+ touch "$archive/flash1"
+
+ set_run_env "run_tftf_reboot_tests" "1"
+ # Contents of Non Volatile Memory are written to this file
+ set_run_env "NVM_file" "flash0"
+}
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ uart0_log=$(echo uart-0-$(date "+%H:%M:%S").log)
+ uart1_log=$(echo uart-1-$(date "+%H:%M:%S").log)
+ set_run_env "uart0_file" "$uart0_log"
+ set_run_env "uart1_file" "$uart1_log"
+
+ model="$model" \
+ aarch32="1" \
+ cluster_0_num_cores="1" \
+ cluster_1_num_cores="1" \
+ flashloader0_fwrite="flash0" \
+ flashloader1_fwrite="flash1" \
+ retain_flash="1" \
+ secure_memory="0" \
+ uart0_out="$uart0_log" \
+ uart1_out="$uart1_log" \
+ bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.aarch32.bmcov b/run_config/fvp-aemv8a.aarch32.bmcov
new file mode 100644
index 0000000..afd62e9
--- /dev/null
+++ b/run_config/fvp-aemv8a.aarch32.bmcov
@@ -0,0 +1,15 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ model="$model" aarch32="1" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.aarch32.nocache.bmcov b/run_config/fvp-aemv8a.aarch32.nocache.bmcov
new file mode 100644
index 0000000..a7a965f
--- /dev/null
+++ b/run_config/fvp-aemv8a.aarch32.nocache.bmcov
@@ -0,0 +1,19 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ use_pchannel_for_threads="1" \
+ model="$model" \
+ aarch32="1" \
+ bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.aarch32.roxlattables.spmin_panic.bmcov b/run_config/fvp-aemv8a.aarch32.roxlattables.spmin_panic.bmcov
new file mode 100644
index 0000000..170975a
--- /dev/null
+++ b/run_config/fvp-aemv8a.aarch32.roxlattables.spmin_panic.bmcov
@@ -0,0 +1,28 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+pre_tf_build() {
+ # Apply a patch which attempts to write to the translation tables (by
+ # changing the memory attributes of a region) immediately after the
+ # translation tables have been made read-only, triggering a data abort.
+ apply_tf_patch "readonly_xlat_tables/arm_sp_min_setup_write_after_readonly.patch"
+ # Apply patch which allows a 'Panic at PC:...' message to be printed
+ # when the data abort happens.
+ apply_tf_patch "readonly_xlat_tables/sp_min_data_abort_print_panic_message.patch"
+}
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ uart="0" timeout="60" file="timeout_spmin_roxlattables.exp" track_expect
+ uart="1" timeout="60" file="crash_panic.exp" set_primary="1" track_expect
+
+ model="$model" aarch32="1" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.amu.aarch32.bmcov b/run_config/fvp-aemv8a.amu.aarch32.bmcov
new file mode 100644
index 0000000..c9b899b
--- /dev/null
+++ b/run_config/fvp-aemv8a.amu.aarch32.bmcov
@@ -0,0 +1,21 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ model="$model" \
+ aarch32="1" \
+ amu_present="1" \
+ arch_version="8.4" \
+ use_pchannel_for_threads="1" \
+ bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.amu.bmcov b/run_config/fvp-aemv8a.amu.bmcov
index 85da7ee..3d34fdd 100644
--- a/run_config/fvp-aemv8a.amu.bmcov
+++ b/run_config/fvp-aemv8a.amu.bmcov
@@ -1,6 +1,6 @@
#!/usr/bin/env bash
#
-# Copyright (c) 2022, Arm Limited. All rights reserved.
+# Copyright (c) 2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/run_config/fvp-aemv8a.arch_features.bmcov b/run_config/fvp-aemv8a.arch_features.bmcov
new file mode 100644
index 0000000..8a30f19
--- /dev/null
+++ b/run_config/fvp-aemv8a.arch_features.bmcov
@@ -0,0 +1,15 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ model="$model" arch_version="8.7" has_brbe="1" has_trbe="1" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.assymetric.bmcov b/run_config/fvp-aemv8a.assymetric.bmcov
index de6274e..bb0525d 100644
--- a/run_config/fvp-aemv8a.assymetric.bmcov
+++ b/run_config/fvp-aemv8a.assymetric.bmcov
@@ -1,6 +1,6 @@
#!/usr/bin/env bash
#
-# Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+# Copyright (c) 2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -12,14 +12,14 @@
model="$model" \
arch_version="8.3" \
- bmcov_plugin_path="${coverage_trace_plugin}" \
- bmcov_plugin="1" \
cluster_0_has_el2="0" \
cluster_0_num_cores="2" \
cluster_0_reg_reset="0xffffffff" \
cluster_1_has_el2="0" \
cluster_1_num_cores="3" \
cluster_1_reg_reset="0xffffffff" \
+ bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
gen_model_params
model="$model" gen_fvp_yaml
diff --git a/run_config/fvp-aemv8a.fi.bmcov b/run_config/fvp-aemv8a.fi.bmcov
index 0b981cb..91e2f51 100644
--- a/run_config/fvp-aemv8a.fi.bmcov
+++ b/run_config/fvp-aemv8a.fi.bmcov
@@ -8,10 +8,8 @@
generate_lava_job() {
local model="base-aemv8a"
- model="$model" \
- bmcov_plugin_path="${coverage_trace_plugin}" \
- bmcov_plugin="1" \
- arch_version="8.4" fault_inject="1"
- gen_model_params
+ model="$model" arch_version="8.4" fault_inject="1" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
model="$model" gen_fvp_yaml
}
diff --git a/run_config/fvp-aemv8a.gicv3_spi.bmcov b/run_config/fvp-aemv8a.gicv3_spi.bmcov
new file mode 100644
index 0000000..822af1d
--- /dev/null
+++ b/run_config/fvp-aemv8a.gicv3_spi.bmcov
@@ -0,0 +1,15 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ model="$model" gicv3_spi_count="988" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.gicv4.bmcov b/run_config/fvp-aemv8a.gicv4.bmcov
new file mode 100644
index 0000000..66a55f0
--- /dev/null
+++ b/run_config/fvp-aemv8a.gicv4.bmcov
@@ -0,0 +1,25 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ model="$model" \
+ gicd_are_fixed_one="1" \
+ gicd_ext_ppi_count="64" \
+ gicd_ext_spi_count="1024" \
+ gicd_its_count="1" \
+ gicd_virtual_lpi="1" \
+ gicv3_ext_interrupt_range="1" \
+ gicv3_spi_count="988" \
+ has_gicv4_1="0" \
+ bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.gpt.bmcov b/run_config/fvp-aemv8a.gpt.bmcov
new file mode 100644
index 0000000..b573084
--- /dev/null
+++ b/run_config/fvp-aemv8a.gpt.bmcov
@@ -0,0 +1,15 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ model="$model" fip_as_gpt="1" supports_crc32="1" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.invalid_nvcounter.bmcov b/run_config/fvp-aemv8a.invalid_nvcounter.bmcov
new file mode 100644
index 0000000..ab16bbf
--- /dev/null
+++ b/run_config/fvp-aemv8a.invalid_nvcounter.bmcov
@@ -0,0 +1,19 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ # The Trusted non-volatile counter is invalid. Authentication of BL2
+ # image is expected to fail.
+ uart="0" file="trusted-firmware-load-error.exp" track_expect
+
+ model="$model" nvcounter_diag="4" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.nvcounter_v1.bmcov b/run_config/fvp-aemv8a.nvcounter_v1.bmcov
new file mode 100644
index 0000000..a5b6243
--- /dev/null
+++ b/run_config/fvp-aemv8a.nvcounter_v1.bmcov
@@ -0,0 +1,17 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ # Version 1 of the non-volatile counter may be incremented in a
+ # monotonic fashion (unlike version 0, which is fixed).
+ model="$model" nvcounter_diag="4" nvcounter_version="r1" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.pl33.bmcov b/run_config/fvp-aemv8a.pl33.bmcov
index a810abf..6d5ff20 100644
--- a/run_config/fvp-aemv8a.pl33.bmcov
+++ b/run_config/fvp-aemv8a.pl33.bmcov
@@ -1,6 +1,6 @@
#!/usr/bin/env bash
#
-# Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+# Copyright (c) 2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -14,10 +14,10 @@
local model="base-aemv8a"
model="$model" \
- bmcov_plugin_path="${coverage_trace_plugin}" \
- bmcov_plugin="1" \
preload_bl33_bin="tftf.bin" \
preload_bl33="1" \
+ bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
gen_model_params
model="$model" gen_fvp_yaml
diff --git a/run_config/fvp-aemv8a.quad.bmcov b/run_config/fvp-aemv8a.quad.bmcov
new file mode 100644
index 0000000..7829e16
--- /dev/null
+++ b/run_config/fvp-aemv8a.quad.bmcov
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a-quad"
+
+ uart="0" set_expect_variable "num_cpus" "16"
+
+ model="$model" \
+ ccn502_cache_size_in_kbytes="0" \
+ bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.rng_trap.bmcov b/run_config/fvp-aemv8a.rng_trap.bmcov
new file mode 100644
index 0000000..4c2e861
--- /dev/null
+++ b/run_config/fvp-aemv8a.rng_trap.bmcov
@@ -0,0 +1,23 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ # Due to a bug in the model, the FEAT_RNG_TRAP feature is not available
+ # in models that implement versions lower than 8.8, even though this is
+ # a v8.5 feature. Therefore, version 8.8 will be used while the FVP
+ # team fixes this problem. Once ready, the parameter arch_version will
+ # be changed to 8.5.
+ arch_version="8.8" \
+ has_rng_trap="1" \
+ has_rng="1" \
+ bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.roxlattables.bl31_panic.bmcov b/run_config/fvp-aemv8a.roxlattables.bl31_panic.bmcov
new file mode 100644
index 0000000..4f35791
--- /dev/null
+++ b/run_config/fvp-aemv8a.roxlattables.bl31_panic.bmcov
@@ -0,0 +1,27 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+pre_tf_build() {
+ # Apply a patch which attempts to write to the translation tables (by
+ # changing the memory attributes of a region) immediately after the
+ # translation tables have been made read-only, triggering an unhandled
+ # exception at EL3.
+ apply_tf_patch "readonly_xlat_tables/arm_bl31_setup_write_after_readonly.patch"
+}
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ uart="0" timeout="60" file="timeout.exp" track_expect
+ uart="1" timeout="60" file="crash_roxlattables_unhandled_exception_at_el3.exp" \
+ set_primary="1" track_expect
+
+ model="$model" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.roxlattables.tspd_panic.bmcov b/run_config/fvp-aemv8a.roxlattables.tspd_panic.bmcov
new file mode 100644
index 0000000..5008988
--- /dev/null
+++ b/run_config/fvp-aemv8a.roxlattables.tspd_panic.bmcov
@@ -0,0 +1,30 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+pre_tf_build() {
+ # Apply a patch which attempts to write to the translation tables (by
+ # changing the memory attributes of a region) immediately after the
+ # translation tables have been made read-only, triggering a synchronous
+ # exception.
+ apply_tf_patch "readonly_xlat_tables/arm_tsp_setup_write_after_readonly.patch"
+ # Apply patch which allows a 'Panic at PC:...' message to be printed
+ # when the synchronous exception happens.
+ apply_tf_patch "readonly_xlat_tables/tsp_sync_exception_print_panic_message.patch"
+}
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ uart="0" timeout="60" file="timeout.exp" track_expect
+ uart="1" timeout="60" file="crash_panic.exp" set_primary="1" track_expect
+ uart="2" timeout="60" file="readonly_el1_xlat_tables.exp" track_expect
+
+ model="$model" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.runtime_bl31_main_panic.bmcov b/run_config/fvp-aemv8a.runtime_bl31_main_panic.bmcov
new file mode 100644
index 0000000..6eb1a3a
--- /dev/null
+++ b/run_config/fvp-aemv8a.runtime_bl31_main_panic.bmcov
@@ -0,0 +1,23 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+pre_tf_build() {
+ # Apply fault injection patches
+ apply_tf_patch "fault_inject/induce_bl31_main_panic.patch"
+}
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ uart="0" timeout="60" file="bl31_boot.exp" track_expect
+ uart="1" timeout="60" file="bl31_main_panic.exp" set_primary="1" track_expect
+
+ model="$model" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a.singlecore.bmcov b/run_config/fvp-aemv8a.singlecore.bmcov
index 85ae259..ce452b0 100644
--- a/run_config/fvp-aemv8a.singlecore.bmcov
+++ b/run_config/fvp-aemv8a.singlecore.bmcov
@@ -1,6 +1,6 @@
#!/usr/bin/env bash
#
-# Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+# Copyright (c) 2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -11,10 +11,10 @@
uart="0" set_expect_variable "num_cpus" "1"
model="$model" \
- bmcov_plugin_path="${coverage_trace_plugin}" \
- bmcov_plugin="1" \
cluster_0_num_cores="1" \
cluster_1_num_cores="0" \
+ bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
gen_model_params
model="$model" gen_fvp_yaml
diff --git a/run_config/fvp-aemv8a.sve.bmcov b/run_config/fvp-aemv8a.sve.bmcov
index 3aef7fd..d07f58b 100644
--- a/run_config/fvp-aemv8a.sve.bmcov
+++ b/run_config/fvp-aemv8a.sve.bmcov
@@ -1,6 +1,6 @@
#!/usr/bin/env bash
#
-# Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+# Copyright (c) 2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
diff --git a/run_config/fvp-aemv8a.tbb.disable_dyn_auth.bmcov b/run_config/fvp-aemv8a.tbb.disable_dyn_auth.bmcov
new file mode 100644
index 0000000..11e869e
--- /dev/null
+++ b/run_config/fvp-aemv8a.tbb.disable_dyn_auth.bmcov
@@ -0,0 +1,23 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+pre_tf_build() {
+ # Apply a patch which disables dynamic authentication
+ # of images during trusted board boot.
+ apply_tf_patch "tbb_dyn_auth/disable_dyn_auth.patch"
+}
+
+generate_lava_job() {
+ local model="base-aemv8a"
+
+ uart="0" file="disable_dyn_auth_tftf.exp" track_expect
+
+ model="$model" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a_gic600ae.aarch32.bmcov b/run_config/fvp-aemv8a_gic600ae.aarch32.bmcov
new file mode 100644
index 0000000..b5aecd2
--- /dev/null
+++ b/run_config/fvp-aemv8a_gic600ae.aarch32.bmcov
@@ -0,0 +1,15 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a-gic600ae"
+
+ model="$model" aarch32="1" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemv8a_gic600ae.bmcov b/run_config/fvp-aemv8a_gic600ae.bmcov
new file mode 100644
index 0000000..4bcface
--- /dev/null
+++ b/run_config/fvp-aemv8a_gic600ae.bmcov
@@ -0,0 +1,15 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemv8a-gic600ae"
+
+ model="$model" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemva.aarch32.bmcov b/run_config/fvp-aemva.aarch32.bmcov
new file mode 100644
index 0000000..cb67434
--- /dev/null
+++ b/run_config/fvp-aemva.aarch32.bmcov
@@ -0,0 +1,15 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemva"
+
+ model="$model" aarch32="1" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemva.aarch32.etm_trace_ext.bmcov b/run_config/fvp-aemva.aarch32.etm_trace_ext.bmcov
new file mode 100644
index 0000000..f0a9e64
--- /dev/null
+++ b/run_config/fvp-aemva.aarch32.etm_trace_ext.bmcov
@@ -0,0 +1,21 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemva"
+
+ model="$model" \
+ aarch32="1" \
+ etm_plugin="1" \
+ etm_present="1" \
+ supports_trace_filter_regs="2" \
+ bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemva.bmcov b/run_config/fvp-aemva.bmcov
new file mode 100644
index 0000000..0ec21f9
--- /dev/null
+++ b/run_config/fvp-aemva.bmcov
@@ -0,0 +1,17 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemva"
+
+ uart="0" set_expect_variable "num_cpus" "4"
+
+ model="$model" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemva.ete_trace_ext.bl31_panic.bmcov b/run_config/fvp-aemva.ete_trace_ext.bl31_panic.bmcov
new file mode 100644
index 0000000..cce3419
--- /dev/null
+++ b/run_config/fvp-aemva.ete_trace_ext.bl31_panic.bmcov
@@ -0,0 +1,25 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemva"
+
+ uart="0" timeout="60" file="timeout_test.exp" track_expect
+ uart="1" timeout="60" file="panic_in_lower_el.exp" \
+ set_primary="1" track_expect
+
+ model="$model" \
+ ete_plugin="1" \
+ etm_present="1" \
+ supports_trace_buffer_control_regs="1" \
+ supports_trace_filter_regs="2" \
+ bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-aemva.feat_brbe.bl31_panic.bmcov b/run_config/fvp-aemva.feat_brbe.bl31_panic.bmcov
new file mode 100644
index 0000000..68662f9
--- /dev/null
+++ b/run_config/fvp-aemva.feat_brbe.bl31_panic.bmcov
@@ -0,0 +1,22 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="base-aemva"
+
+ uart="0" timeout="60" file="timeout_test.exp" track_expect
+ uart="1" timeout="60" file="panic_in_lower_el.exp" \
+ set_primary="1" track_expect
+
+ model="$model" \
+ supports_branch_record_buffer_control_regs="1" \
+ bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-cortexa35x4.bmcov b/run_config/fvp-cortexa35x4.bmcov
new file mode 100644
index 0000000..680e670
--- /dev/null
+++ b/run_config/fvp-cortexa35x4.bmcov
@@ -0,0 +1,17 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="cortex-a35x4"
+
+ uart="0" set_expect_variable "num_cpus" "4"
+
+ model="$model" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-cortexa57x4a53x4.bmcov b/run_config/fvp-cortexa57x4a53x4.bmcov
new file mode 100644
index 0000000..9069275
--- /dev/null
+++ b/run_config/fvp-cortexa57x4a53x4.bmcov
@@ -0,0 +1,15 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+generate_lava_job() {
+ local model="cortex-a57x4-a53x4"
+
+ model="$model" bmcov_plugin="1" \
+ bmcov_plugin_path="${coverage_trace_plugin}" \
+ gen_model_params
+ model="$model" gen_fvp_yaml
+}
diff --git a/run_config/fvp-foundationv8.bmcov b/run_config/fvp-foundationv8.bmcov
index aedd6a5..0774d42 100644
--- a/run_config/fvp-foundationv8.bmcov
+++ b/run_config/fvp-foundationv8.bmcov
@@ -1,6 +1,6 @@
#!/usr/bin/env bash
#
-# Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+# Copyright (c) 2023, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -10,10 +10,8 @@
uart="0" set_expect_variable "num_cpus" "4"
- model="$model" \
+ model="$model" bmcov_plugin="1" \
bmcov_plugin_path="${coverage_trace_plugin}" \
- bmcov_plugin="1" \
gen_model_params
-
model="$model" gen_fvp_yaml
}
diff --git a/tf_config/fvp-aarch32-default-cc b/tf_config/fvp-aarch32-default-cc
new file mode 100644
index 0000000..bcd11fa
--- /dev/null
+++ b/tf_config/fvp-aarch32-default-cc
@@ -0,0 +1,5 @@
+AARCH32_SP=sp_min
+ARCH=aarch32
+CROSS_COMPILE=arm-none-eabi-
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-aarch32-enable-runtime-instr-cc b/tf_config/fvp-aarch32-enable-runtime-instr-cc
new file mode 100644
index 0000000..36c894a
--- /dev/null
+++ b/tf_config/fvp-aarch32-enable-runtime-instr-cc
@@ -0,0 +1,6 @@
+AARCH32_SP=sp_min
+ARCH=aarch32
+CROSS_COMPILE=arm-none-eabi-
+ENABLE_RUNTIME_INSTRUMENTATION=1
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-aarch32-mtpmu-disable-cc b/tf_config/fvp-aarch32-mtpmu-disable-cc
new file mode 100644
index 0000000..6ce122c
--- /dev/null
+++ b/tf_config/fvp-aarch32-mtpmu-disable-cc
@@ -0,0 +1,7 @@
+AARCH32_SP=sp_min
+ARCH=aarch32
+ARM_ARCH_MINOR=6
+CROSS_COMPILE=arm-none-eabi-
+DISABLE_MTPMU=1
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-aarch32-roxlattables-cc b/tf_config/fvp-aarch32-roxlattables-cc
new file mode 100644
index 0000000..88b6159
--- /dev/null
+++ b/tf_config/fvp-aarch32-roxlattables-cc
@@ -0,0 +1,6 @@
+AARCH32_SP=sp_min
+ARCH=aarch32
+CROSS_COMPILE=arm-none-eabi-
+PLAT=fvp
+ALLOW_RO_XLAT_TABLES=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-aarch32-sec-int-fconf-cc b/tf_config/fvp-aarch32-sec-int-fconf-cc
new file mode 100644
index 0000000..5cc58ef
--- /dev/null
+++ b/tf_config/fvp-aarch32-sec-int-fconf-cc
@@ -0,0 +1,6 @@
+AARCH32_SP=sp_min
+ARCH=aarch32
+CROSS_COMPILE=arm-none-eabi-
+PLAT=fvp
+SEC_INT_DESC_IN_FCONF=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-aarch32-tbb-mbedtls-cc b/tf_config/fvp-aarch32-tbb-mbedtls-cc
new file mode 100644
index 0000000..92eb268
--- /dev/null
+++ b/tf_config/fvp-aarch32-tbb-mbedtls-cc
@@ -0,0 +1,9 @@
+AARCH32_SP=sp_min
+ARCH=aarch32
+ARM_ROTPK_LOCATION=devel_rsa
+CROSS_COMPILE=arm-none-eabi-
+GENERATE_COT=1
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+TRUSTED_BOARD_BOOT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-aarch32-tbb-mbedtls-dualroot-cc b/tf_config/fvp-aarch32-tbb-mbedtls-dualroot-cc
new file mode 100644
index 0000000..9cf6e78
--- /dev/null
+++ b/tf_config/fvp-aarch32-tbb-mbedtls-dualroot-cc
@@ -0,0 +1,10 @@
+AARCH32_SP=sp_min
+ARCH=aarch32
+ARM_ROTPK_LOCATION=devel_rsa
+CROSS_COMPILE=arm-none-eabi-
+COT=dualroot
+GENERATE_COT=1
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+TRUSTED_BOARD_BOOT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-aarch32-tbb-mbedtls-ecdsa-cc b/tf_config/fvp-aarch32-tbb-mbedtls-ecdsa-cc
new file mode 100644
index 0000000..ec60df4
--- /dev/null
+++ b/tf_config/fvp-aarch32-tbb-mbedtls-ecdsa-cc
@@ -0,0 +1,10 @@
+AARCH32_SP=sp_min
+ARCH=aarch32
+ARM_ROTPK_LOCATION=devel_ecdsa
+CROSS_COMPILE=arm-none-eabi-
+GENERATE_COT=1
+KEY_ALG=ecdsa
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem
+TRUSTED_BOARD_BOOT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-aarch32-tbb-mbedtls-rsa-3k-cert-cc b/tf_config/fvp-aarch32-tbb-mbedtls-rsa-3k-cert-cc
new file mode 100644
index 0000000..1e63a50
--- /dev/null
+++ b/tf_config/fvp-aarch32-tbb-mbedtls-rsa-3k-cert-cc
@@ -0,0 +1,10 @@
+AARCH32_SP=sp_min
+ARCH=aarch32
+ARM_ROTPK_LOCATION=devel_rsa
+CROSS_COMPILE=arm-none-eabi-
+GENERATE_COT=1
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+TRUSTED_BOARD_BOOT=1
+KEY_SIZE=3072
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-aarch32-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc b/tf_config/fvp-aarch32-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc
new file mode 100644
index 0000000..f2a662e
--- /dev/null
+++ b/tf_config/fvp-aarch32-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc
@@ -0,0 +1,11 @@
+AARCH32_SP=sp_min
+ARCH=aarch32
+ARM_ROTPK_LOCATION=devel_ecdsa
+CROSS_COMPILE=arm-none-eabi-
+GENERATE_COT=1
+KEY_ALG=rsa
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem
+TF_MBEDTLS_KEY_ALG=rsa+ecdsa
+TRUSTED_BOARD_BOOT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-aarch64-gicr-protection-cc b/tf_config/fvp-aarch64-gicr-protection-cc
new file mode 100644
index 0000000..4048e92
--- /dev/null
+++ b/tf_config/fvp-aarch64-gicr-protection-cc
@@ -0,0 +1,4 @@
+CROSS_COMPILE=aarch64-none-elf-
+PLAT=fvp
+FVP_GICR_REGION_PROTECTION=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-aarch64-only-cc b/tf_config/fvp-aarch64-only-cc
new file mode 100644
index 0000000..2d838af
--- /dev/null
+++ b/tf_config/fvp-aarch64-only-cc
@@ -0,0 +1,4 @@
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_AARCH32_REGS=0
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-aarch64-roxlattables-cc b/tf_config/fvp-aarch64-roxlattables-cc
new file mode 100644
index 0000000..4ebfa80
--- /dev/null
+++ b/tf_config/fvp-aarch64-roxlattables-cc
@@ -0,0 +1,5 @@
+CROSS_COMPILE=aarch64-none-elf-
+PLAT=fvp
+ALLOW_RO_XLAT_TABLES=1
+RECLAIM_INIT_CODE=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-aarch64-roxlattables-tspd-cc b/tf_config/fvp-aarch64-roxlattables-tspd-cc
new file mode 100644
index 0000000..f985ba3
--- /dev/null
+++ b/tf_config/fvp-aarch64-roxlattables-tspd-cc
@@ -0,0 +1,5 @@
+CROSS_COMPILE=aarch64-none-elf-
+PLAT=fvp
+ALLOW_RO_XLAT_TABLES=1
+SPD=tspd
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-aarch64-sdei-cc b/tf_config/fvp-aarch64-sdei-cc
index c98dfbf..4ab5350 100644
--- a/tf_config/fvp-aarch64-sdei-cc
+++ b/tf_config/fvp-aarch64-sdei-cc
@@ -1,5 +1,5 @@
CROSS_COMPILE=aarch64-none-elf-
EL3_EXCEPTION_HANDLING=1
-ENABLE_ASSERTIONS=0
PLAT=fvp
SDEI_SUPPORT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-aarch64-sdei-fconf-cc b/tf_config/fvp-aarch64-sdei-fconf-cc
new file mode 100644
index 0000000..de7f273
--- /dev/null
+++ b/tf_config/fvp-aarch64-sdei-fconf-cc
@@ -0,0 +1,6 @@
+CROSS_COMPILE=aarch64-none-elf-
+EL3_EXCEPTION_HANDLING=1
+PLAT=fvp
+SDEI_SUPPORT=1
+SDEI_IN_FCONF=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-aarch64-sec-int-fconf-cc b/tf_config/fvp-aarch64-sec-int-fconf-cc
new file mode 100644
index 0000000..4345a0f
--- /dev/null
+++ b/tf_config/fvp-aarch64-sec-int-fconf-cc
@@ -0,0 +1,4 @@
+CROSS_COMPILE=aarch64-none-elf-
+PLAT=fvp
+SEC_INT_DESC_IN_FCONF=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-bl31-separate-nobits-cc b/tf_config/fvp-bl31-separate-nobits-cc
new file mode 100644
index 0000000..ac87907
--- /dev/null
+++ b/tf_config/fvp-bl31-separate-nobits-cc
@@ -0,0 +1,6 @@
+ARM_BL31_IN_DRAM=1
+CROSS_COMPILE=aarch64-none-elf-
+PLAT=fvp
+RECLAIM_INIT_CODE=0
+SEPARATE_NOBITS_REGION=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-cas-spinlock-cc b/tf_config/fvp-cas-spinlock-cc
new file mode 100644
index 0000000..a8f38af
--- /dev/null
+++ b/tf_config/fvp-cas-spinlock-cc
@@ -0,0 +1,5 @@
+CROSS_COMPILE=aarch64-none-elf-
+PLAT=fvp
+ARM_ARCH_MINOR=3
+USE_SPINLOCK_CAS=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-crash-report-cc b/tf_config/fvp-crash-report-cc
new file mode 100644
index 0000000..06912d4
--- /dev/null
+++ b/tf_config/fvp-crash-report-cc
@@ -0,0 +1,5 @@
+CRASH_REPORTING=1
+CROSS_COMPILE=aarch64-none-elf-
+ENABLE_BACKTRACE=1
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-debugfs-cc b/tf_config/fvp-debugfs-cc
new file mode 100644
index 0000000..fc4a7d1
--- /dev/null
+++ b/tf_config/fvp-debugfs-cc
@@ -0,0 +1,4 @@
+CROSS_COMPILE=aarch64-none-elf-
+PLAT=fvp
+USE_DEBUGFS=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-default-cc b/tf_config/fvp-default-cc
index 1247532..f18dc14 100644
--- a/tf_config/fvp-default-cc
+++ b/tf_config/fvp-default-cc
@@ -1,3 +1,3 @@
CROSS_COMPILE=aarch64-none-elf-
-ENABLE_ASSERTIONS=0
PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-default-clang-bfd-cc b/tf_config/fvp-default-clang-bfd-cc
new file mode 100644
index 0000000..d8b33d4
--- /dev/null
+++ b/tf_config/fvp-default-clang-bfd-cc
@@ -0,0 +1,4 @@
+CC=clang
+LD=aarch64-none-elf-ld.bfd
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-default-clang-cc b/tf_config/fvp-default-clang-cc
new file mode 100644
index 0000000..bd7e3df
--- /dev/null
+++ b/tf_config/fvp-default-clang-cc
@@ -0,0 +1,3 @@
+CC=clang
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-detect-features-aarch64-only-cc b/tf_config/fvp-detect-features-aarch64-only-cc
new file mode 100644
index 0000000..28a7ca8
--- /dev/null
+++ b/tf_config/fvp-detect-features-aarch64-only-cc
@@ -0,0 +1,6 @@
+ARM_ARCH_MINOR=6
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_AARCH32_REGS=0
+FEATURE_DETECTION=1
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-ea-ffh-cc b/tf_config/fvp-ea-ffh-cc
index 103d6c6..b3add65 100644
--- a/tf_config/fvp-ea-ffh-cc
+++ b/tf_config/fvp-ea-ffh-cc
@@ -1,5 +1,5 @@
CROSS_COMPILE=aarch64-none-elf-
HANDLE_EA_EL3_FIRST_NS=1
PLATFORM_TEST_EA_FFH=1
-ENABLE_ASSERTIONS=0
PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-early-d-cache-cc b/tf_config/fvp-early-d-cache-cc
new file mode 100644
index 0000000..b3dd76d
--- /dev/null
+++ b/tf_config/fvp-early-d-cache-cc
@@ -0,0 +1,4 @@
+CROSS_COMPILE=aarch64-none-elf-
+PLAT=fvp
+WARMBOOT_ENABLE_DCACHE_EARLY=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-enable-runtime-instr-aarch64-only-cc b/tf_config/fvp-enable-runtime-instr-aarch64-only-cc
new file mode 100644
index 0000000..1a3d093
--- /dev/null
+++ b/tf_config/fvp-enable-runtime-instr-aarch64-only-cc
@@ -0,0 +1,5 @@
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_AARCH32_REGS=0
+ENABLE_RUNTIME_INSTRUMENTATION=1
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-enable-runtime-instr-cc b/tf_config/fvp-enable-runtime-instr-cc
index 7a30c8b..407feb4 100644
--- a/tf_config/fvp-enable-runtime-instr-cc
+++ b/tf_config/fvp-enable-runtime-instr-cc
@@ -1,4 +1,4 @@
CROSS_COMPILE=aarch64-none-elf-
-ENABLE_ASSERTIONS=0
ENABLE_RUNTIME_INSTRUMENTATION=1
PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-ext-pstate-ea-el3-aarch64-only-cc b/tf_config/fvp-ext-pstate-ea-el3-aarch64-only-cc
new file mode 100644
index 0000000..f17f8e5
--- /dev/null
+++ b/tf_config/fvp-ext-pstate-ea-el3-aarch64-only-cc
@@ -0,0 +1,7 @@
+ARM_RECOM_STATE_ID_ENC=1
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_AARCH32_REGS=0
+HANDLE_EA_EL3_FIRST_NS=1
+PLAT=fvp
+PSCI_EXTENDED_STATE_ID=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-ext-pstate-ea-el3-cc b/tf_config/fvp-ext-pstate-ea-el3-cc
index 5ca7f06..0b86d45 100644
--- a/tf_config/fvp-ext-pstate-ea-el3-cc
+++ b/tf_config/fvp-ext-pstate-ea-el3-cc
@@ -1,6 +1,6 @@
ARM_RECOM_STATE_ID_ENC=1
CROSS_COMPILE=aarch64-none-elf-
-ENABLE_ASSERTIONS=0
HANDLE_EA_EL3_FIRST_NS=1
PLAT=fvp
PSCI_EXTENDED_STATE_ID=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-gcc-lto-cc b/tf_config/fvp-gcc-lto-cc
new file mode 100644
index 0000000..b595fac
--- /dev/null
+++ b/tf_config/fvp-gcc-lto-cc
@@ -0,0 +1,5 @@
+CROSS_COMPILE=aarch64-none-elf-
+ENABLE_LTO=1
+PLAT=fvp
+
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-gicv4-cc b/tf_config/fvp-gicv4-cc
new file mode 100644
index 0000000..7f74993
--- /dev/null
+++ b/tf_config/fvp-gicv4-cc
@@ -0,0 +1,5 @@
+CROSS_COMPILE=aarch64-none-elf-
+GIC_ENABLE_V4_EXTN=1
+GIC_EXT_INTID=1
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-gpt-cc b/tf_config/fvp-gpt-cc
new file mode 100644
index 0000000..1421f91
--- /dev/null
+++ b/tf_config/fvp-gpt-cc
@@ -0,0 +1,4 @@
+ARM_GPT_SUPPORT=1
+CROSS_COMPILE=aarch64-none-elf-
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-hcx-aarch64-only-cc b/tf_config/fvp-hcx-aarch64-only-cc
new file mode 100644
index 0000000..70f964b
--- /dev/null
+++ b/tf_config/fvp-hcx-aarch64-only-cc
@@ -0,0 +1,5 @@
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_AARCH32_REGS=0
+ENABLE_FEAT_HCX=1
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-mb_hash256-tbb_hash256-romlib-cc b/tf_config/fvp-mb_hash256-tbb_hash256-romlib-cc
new file mode 100644
index 0000000..e4e9c1f
--- /dev/null
+++ b/tf_config/fvp-mb_hash256-tbb_hash256-romlib-cc
@@ -0,0 +1,10 @@
+ARM_ROTPK_LOCATION=devel_rsa
+CROSS_COMPILE=aarch64-none-elf-
+GENERATE_COT=1
+MEASURED_BOOT=1
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+MBOOT_EL_HASH_ALG=sha256
+TRUSTED_BOARD_BOOT=1
+USE_ROMLIB=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-mtpmu-disable-aarch64-only-cc b/tf_config/fvp-mtpmu-disable-aarch64-only-cc
new file mode 100644
index 0000000..886c636
--- /dev/null
+++ b/tf_config/fvp-mtpmu-disable-aarch64-only-cc
@@ -0,0 +1,6 @@
+ARM_ARCH_MINOR=6
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_AARCH32_REGS=0
+DISABLE_MTPMU=1
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-mtpmu-disable-cc b/tf_config/fvp-mtpmu-disable-cc
new file mode 100644
index 0000000..ea8048f
--- /dev/null
+++ b/tf_config/fvp-mtpmu-disable-cc
@@ -0,0 +1,5 @@
+ARM_ARCH_MINOR=6
+CROSS_COMPILE=aarch64-none-elf-
+DISABLE_MTPMU=1
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-no-brbe-regs-access-cc b/tf_config/fvp-no-brbe-regs-access-cc
new file mode 100644
index 0000000..624c499
--- /dev/null
+++ b/tf_config/fvp-no-brbe-regs-access-cc
@@ -0,0 +1,4 @@
+CROSS_COMPILE=aarch64-none-elf-
+ENABLE_BRBE_FOR_NS=0
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-no-cohmem-aarch64-only-cc b/tf_config/fvp-no-cohmem-aarch64-only-cc
new file mode 100644
index 0000000..fbd0744
--- /dev/null
+++ b/tf_config/fvp-no-cohmem-aarch64-only-cc
@@ -0,0 +1,5 @@
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_AARCH32_REGS=0
+PLAT=fvp
+USE_COHERENT_MEM=0
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-no-cohmem-cc b/tf_config/fvp-no-cohmem-cc
index f4417b3..c9d3b49 100644
--- a/tf_config/fvp-no-cohmem-cc
+++ b/tf_config/fvp-no-cohmem-cc
@@ -1,4 +1,4 @@
CROSS_COMPILE=aarch64-none-elf-
-ENABLE_ASSERTIONS=0
PLAT=fvp
USE_COHERENT_MEM=0
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-no-optimize-default-cc b/tf_config/fvp-no-optimize-default-cc
new file mode 100644
index 0000000..65b1077
--- /dev/null
+++ b/tf_config/fvp-no-optimize-default-cc
@@ -0,0 +1,6 @@
+CROSS_COMPILE=aarch64-none-elf-
+PLAT=fvp
+ARM_BL31_IN_DRAM=1
+LOG_LEVEL=20
+CFLAGS='-O0'
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-no-sys-regs-trace-access-aarch64-only-cc b/tf_config/fvp-no-sys-regs-trace-access-aarch64-only-cc
new file mode 100644
index 0000000..7c05143
--- /dev/null
+++ b/tf_config/fvp-no-sys-regs-trace-access-aarch64-only-cc
@@ -0,0 +1,5 @@
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_AARCH32_REGS=0
+ENABLE_SYS_REG_TRACE_FOR_NS=0
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-no-trbe-regs-access-aarch64-only-cc b/tf_config/fvp-no-trbe-regs-access-aarch64-only-cc
new file mode 100644
index 0000000..43be6ee
--- /dev/null
+++ b/tf_config/fvp-no-trbe-regs-access-aarch64-only-cc
@@ -0,0 +1,5 @@
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_AARCH32_REGS=0
+ENABLE_TRBE_FOR_NS=0
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-no-trf-regs-access-aarch64-only-cc b/tf_config/fvp-no-trf-regs-access-aarch64-only-cc
new file mode 100644
index 0000000..6082e7d
--- /dev/null
+++ b/tf_config/fvp-no-trf-regs-access-aarch64-only-cc
@@ -0,0 +1,5 @@
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_AARCH32_REGS=0
+ENABLE_TRF_FOR_NS=0
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-opteed-aarch64-only-cc b/tf_config/fvp-opteed-aarch64-only-cc
new file mode 100644
index 0000000..2e6116a
--- /dev/null
+++ b/tf_config/fvp-opteed-aarch64-only-cc
@@ -0,0 +1,6 @@
+ARM_TSP_RAM_LOCATION=tdram
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_AARCH32_REGS=0
+PLAT=fvp
+SPD=opteed
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-opteed-cc b/tf_config/fvp-opteed-cc
index 39dfc3d..775b8cf 100644
--- a/tf_config/fvp-opteed-cc
+++ b/tf_config/fvp-opteed-cc
@@ -1,5 +1,5 @@
ARM_TSP_RAM_LOCATION=tdram
CROSS_COMPILE=aarch64-none-elf-
-ENABLE_ASSERTIONS=0
PLAT=fvp
SPD=opteed
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-pauth-bti-romlib-cc b/tf_config/fvp-pauth-bti-romlib-cc
new file mode 100644
index 0000000..ec9ea11
--- /dev/null
+++ b/tf_config/fvp-pauth-bti-romlib-cc
@@ -0,0 +1,10 @@
+ARM_ARCH_MINOR=5
+ARM_ROTPK_LOCATION=devel_rsa
+BRANCH_PROTECTION=4
+CROSS_COMPILE=aarch64-none-elf-
+GENERATE_COT=1
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+TRUSTED_BOARD_BOOT=1
+USE_ROMLIB=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-pauth-bti-sdei-cc b/tf_config/fvp-pauth-bti-sdei-cc
new file mode 100644
index 0000000..fa96bfb
--- /dev/null
+++ b/tf_config/fvp-pauth-bti-sdei-cc
@@ -0,0 +1,7 @@
+ARM_ARCH_MINOR=5
+BRANCH_PROTECTION=4
+CROSS_COMPILE=aarch64-none-elf-
+EL3_EXCEPTION_HANDLING=1
+PLAT=fvp
+SDEI_SUPPORT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-pauth-bti-tsp-romlib-cc b/tf_config/fvp-pauth-bti-tsp-romlib-cc
new file mode 100644
index 0000000..98c1eb5
--- /dev/null
+++ b/tf_config/fvp-pauth-bti-tsp-romlib-cc
@@ -0,0 +1,12 @@
+ARM_ARCH_MINOR=5
+ARM_ROTPK_LOCATION=devel_rsa
+BRANCH_PROTECTION=4
+CROSS_COMPILE=aarch64-none-elf-
+GENERATE_COT=1
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+SPD=tspd
+TRUSTED_BOARD_BOOT=1
+TSP_NS_INTR_ASYNC_PREEMPT=1
+USE_ROMLIB=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-pauth-bti-tsp-sdei-cc b/tf_config/fvp-pauth-bti-tsp-sdei-cc
new file mode 100644
index 0000000..b798971
--- /dev/null
+++ b/tf_config/fvp-pauth-bti-tsp-sdei-cc
@@ -0,0 +1,9 @@
+ARM_ARCH_MINOR=5
+BRANCH_PROTECTION=4
+CROSS_COMPILE=aarch64-none-elf-
+EL3_EXCEPTION_HANDLING=1
+PLAT=fvp
+SDEI_SUPPORT=1
+SPD=tspd
+TSP_NS_INTR_ASYNC_PREEMPT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-pauth-ctx-sdei-cc b/tf_config/fvp-pauth-ctx-sdei-cc
new file mode 100644
index 0000000..f62047f
--- /dev/null
+++ b/tf_config/fvp-pauth-ctx-sdei-cc
@@ -0,0 +1,8 @@
+ARM_ARCH_MINOR=5
+BRANCH_PROTECTION=1
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_PAUTH_REGS=1
+EL3_EXCEPTION_HANDLING=1
+PLAT=fvp
+SDEI_SUPPORT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-pauth-ctx-tsp-sdei-cc b/tf_config/fvp-pauth-ctx-tsp-sdei-cc
new file mode 100644
index 0000000..8548d43
--- /dev/null
+++ b/tf_config/fvp-pauth-ctx-tsp-sdei-cc
@@ -0,0 +1,10 @@
+ARM_ARCH_MINOR=5
+BRANCH_PROTECTION=1
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_PAUTH_REGS=1
+EL3_EXCEPTION_HANDLING=1
+PLAT=fvp
+SDEI_SUPPORT=1
+SPD=tspd
+TSP_NS_INTR_ASYNC_PREEMPT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-pauth-pac-ret-leaf-sdei-cc b/tf_config/fvp-pauth-pac-ret-leaf-sdei-cc
new file mode 100644
index 0000000..246af00
--- /dev/null
+++ b/tf_config/fvp-pauth-pac-ret-leaf-sdei-cc
@@ -0,0 +1,8 @@
+ARM_ARCH_MINOR=5
+BRANCH_PROTECTION=3
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_PAUTH_REGS=1
+EL3_EXCEPTION_HANDLING=1
+PLAT=fvp
+SDEI_SUPPORT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-pauth-pac-ret-leaf-tsp-sdei-cc b/tf_config/fvp-pauth-pac-ret-leaf-tsp-sdei-cc
new file mode 100644
index 0000000..a5ba855
--- /dev/null
+++ b/tf_config/fvp-pauth-pac-ret-leaf-tsp-sdei-cc
@@ -0,0 +1,10 @@
+ARM_ARCH_MINOR=5
+BRANCH_PROTECTION=3
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_PAUTH_REGS=1
+EL3_EXCEPTION_HANDLING=1
+PLAT=fvp
+SDEI_SUPPORT=1
+SPD=tspd
+TSP_NS_INTR_ASYNC_PREEMPT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-pauth-pac-ret-sdei-cc b/tf_config/fvp-pauth-pac-ret-sdei-cc
new file mode 100644
index 0000000..3272a54
--- /dev/null
+++ b/tf_config/fvp-pauth-pac-ret-sdei-cc
@@ -0,0 +1,8 @@
+ARM_ARCH_MINOR=5
+BRANCH_PROTECTION=2
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_PAUTH_REGS=1
+EL3_EXCEPTION_HANDLING=1
+PLAT=fvp
+SDEI_SUPPORT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-pauth-pac-ret-tsp-sdei-cc b/tf_config/fvp-pauth-pac-ret-tsp-sdei-cc
new file mode 100644
index 0000000..69a6d16
--- /dev/null
+++ b/tf_config/fvp-pauth-pac-ret-tsp-sdei-cc
@@ -0,0 +1,10 @@
+ARM_ARCH_MINOR=5
+BRANCH_PROTECTION=2
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_PAUTH_REGS=1
+EL3_EXCEPTION_HANDLING=1
+PLAT=fvp
+SDEI_SUPPORT=1
+SPD=tspd
+TSP_NS_INTR_ASYNC_PREEMPT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-pauth-standard-romlib-cc b/tf_config/fvp-pauth-standard-romlib-cc
new file mode 100644
index 0000000..eaecfee
--- /dev/null
+++ b/tf_config/fvp-pauth-standard-romlib-cc
@@ -0,0 +1,11 @@
+ARM_ARCH_MINOR=5
+ARM_ROTPK_LOCATION=devel_rsa
+BRANCH_PROTECTION=1
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_PAUTH_REGS=1
+GENERATE_COT=1
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+TRUSTED_BOARD_BOOT=1
+USE_ROMLIB=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-pauth-standard-sdei-cc b/tf_config/fvp-pauth-standard-sdei-cc
new file mode 100644
index 0000000..f62047f
--- /dev/null
+++ b/tf_config/fvp-pauth-standard-sdei-cc
@@ -0,0 +1,8 @@
+ARM_ARCH_MINOR=5
+BRANCH_PROTECTION=1
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_PAUTH_REGS=1
+EL3_EXCEPTION_HANDLING=1
+PLAT=fvp
+SDEI_SUPPORT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-pauth-standard-tsp-romlib-cc b/tf_config/fvp-pauth-standard-tsp-romlib-cc
new file mode 100644
index 0000000..bc59898
--- /dev/null
+++ b/tf_config/fvp-pauth-standard-tsp-romlib-cc
@@ -0,0 +1,13 @@
+ARM_ARCH_MINOR=5
+ARM_ROTPK_LOCATION=devel_rsa
+BRANCH_PROTECTION=1
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_PAUTH_REGS=1
+GENERATE_COT=1
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+SPD=tspd
+TRUSTED_BOARD_BOOT=1
+TSP_NS_INTR_ASYNC_PREEMPT=1
+USE_ROMLIB=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-pauth-standard-tsp-sdei-cc b/tf_config/fvp-pauth-standard-tsp-sdei-cc
new file mode 100644
index 0000000..8548d43
--- /dev/null
+++ b/tf_config/fvp-pauth-standard-tsp-sdei-cc
@@ -0,0 +1,10 @@
+ARM_ARCH_MINOR=5
+BRANCH_PROTECTION=1
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_PAUTH_REGS=1
+EL3_EXCEPTION_HANDLING=1
+PLAT=fvp
+SDEI_SUPPORT=1
+SPD=tspd
+TSP_NS_INTR_ASYNC_PREEMPT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-pl33-cc b/tf_config/fvp-pl33-cc
index 1bc344c..425a62c 100644
--- a/tf_config/fvp-pl33-cc
+++ b/tf_config/fvp-pl33-cc
@@ -1,4 +1,4 @@
CROSS_COMPILE=aarch64-none-elf-
-ENABLE_ASSERTIONS=0
PLAT=fvp
PRELOADED_BL33_BASE=0x88000000
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-reclaim-init-code-cc b/tf_config/fvp-reclaim-init-code-cc
new file mode 100644
index 0000000..6309d78
--- /dev/null
+++ b/tf_config/fvp-reclaim-init-code-cc
@@ -0,0 +1,4 @@
+CROSS_COMPILE=aarch64-none-elf-
+PLAT=fvp
+RECLAIM_INIT_CODE=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-rng-trap-cc b/tf_config/fvp-rng-trap-cc
new file mode 100644
index 0000000..aecccf6
--- /dev/null
+++ b/tf_config/fvp-rng-trap-cc
@@ -0,0 +1,7 @@
+ARM_ARCH_FEATURE=rng
+ARM_ARCH_MINOR=5
+CROSS_COMPILE=aarch64-none-elf-
+ENABLE_FEAT_RNG=1
+ENABLE_FEAT_RNG_TRAP=1
+PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-spm-mm-cc b/tf_config/fvp-spm-mm-cc
index 8cdfdc1..f567e79 100644
--- a/tf_config/fvp-spm-mm-cc
+++ b/tf_config/fvp-spm-mm-cc
@@ -2,7 +2,7 @@
CROSS_COMPILE=aarch64-none-elf-
CTX_INCLUDE_FPREGS=1
EL3_EXCEPTION_HANDLING=1
-ENABLE_ASSERTIONS=0
ENABLE_SVE_FOR_NS=0
SPM_MM=1
PLAT=fvp
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tbb-mbedtls-ecdsa-cc b/tf_config/fvp-tbb-mbedtls-ecdsa-cc
new file mode 100644
index 0000000..5f0e5a9
--- /dev/null
+++ b/tf_config/fvp-tbb-mbedtls-ecdsa-cc
@@ -0,0 +1,9 @@
+ARM_ROTPK_LOCATION=devel_ecdsa
+CROSS_COMPILE=aarch64-none-elf-
+ENABLE_ASSERTIONS=0
+GENERATE_COT=1
+KEY_ALG=ecdsa
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem
+TRUSTED_BOARD_BOOT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tbb-mbedtls-ecdsa-sha512-cc b/tf_config/fvp-tbb-mbedtls-ecdsa-sha512-cc
new file mode 100644
index 0000000..a9bbf1e
--- /dev/null
+++ b/tf_config/fvp-tbb-mbedtls-ecdsa-sha512-cc
@@ -0,0 +1,9 @@
+ARM_ROTPK_LOCATION=devel_ecdsa
+CROSS_COMPILE=aarch64-none-elf-
+GENERATE_COT=1
+HASH_ALG=sha512
+KEY_ALG=ecdsa
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem
+TRUSTED_BOARD_BOOT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tbb-mbedtls-full-dev-rsa-key-cc b/tf_config/fvp-tbb-mbedtls-full-dev-rsa-key-cc
new file mode 100644
index 0000000..794cc21
--- /dev/null
+++ b/tf_config/fvp-tbb-mbedtls-full-dev-rsa-key-cc
@@ -0,0 +1,8 @@
+ARM_ROTPK_LOCATION=devel_full_dev_rsa_key
+CROSS_COMPILE=aarch64-none-elf-
+GENERATE_COT=1
+KEY_ALG=rsa
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+TRUSTED_BOARD_BOOT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tbb-mbedtls-romlib-cot-in-dtb-cc b/tf_config/fvp-tbb-mbedtls-romlib-cot-in-dtb-cc
new file mode 100644
index 0000000..1cb7d8e
--- /dev/null
+++ b/tf_config/fvp-tbb-mbedtls-romlib-cot-in-dtb-cc
@@ -0,0 +1,9 @@
+ARM_ROTPK_LOCATION=devel_rsa
+COT_DESC_IN_DTB=1
+CROSS_COMPILE=aarch64-none-elf-
+GENERATE_COT=1
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+TRUSTED_BOARD_BOOT=1
+USE_ROMLIB=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tbb-mbedtls-rsa-3k-cert-cc b/tf_config/fvp-tbb-mbedtls-rsa-3k-cert-cc
new file mode 100644
index 0000000..05614f8
--- /dev/null
+++ b/tf_config/fvp-tbb-mbedtls-rsa-3k-cert-cc
@@ -0,0 +1,11 @@
+ARM_ROTPK_LOCATION=devel_rsa
+CROSS_COMPILE=aarch64-none-elf-
+ENABLE_ASSERTIONS=0
+GENERATE_COT=1
+KEY_ALG=rsa
+KEY_SIZE=3072
+LOG_LEVEL=20
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+TRUSTED_BOARD_BOOT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tbb-mbedtls-rsa-4k-cert-cc b/tf_config/fvp-tbb-mbedtls-rsa-4k-cert-cc
new file mode 100644
index 0000000..deb0183
--- /dev/null
+++ b/tf_config/fvp-tbb-mbedtls-rsa-4k-cert-cc
@@ -0,0 +1,11 @@
+ARM_ROTPK_LOCATION=devel_rsa
+CROSS_COMPILE=aarch64-none-elf-
+ENABLE_ASSERTIONS=0
+GENERATE_COT=1
+KEY_ALG=rsa
+KEY_SIZE=4096
+LOG_LEVEL=20
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+TRUSTED_BOARD_BOOT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc b/tf_config/fvp-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc
new file mode 100644
index 0000000..6244675
--- /dev/null
+++ b/tf_config/fvp-tbb-mbedtls-rsa-ecdsa-with-ecdsa-rotpk-rsa-cert-cc
@@ -0,0 +1,11 @@
+ARM_ROTPK_LOCATION=devel_ecdsa
+CROSS_COMPILE=aarch64-none-elf-
+ENABLE_ASSERTIONS=0
+GENERATE_COT=1
+KEY_ALG=rsa
+LOG_LEVEL=20
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem
+TF_MBEDTLS_KEY_ALG=rsa+ecdsa
+TRUSTED_BOARD_BOOT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tbb-mbedtls-rsa-ecdsa-with-rsa-rotpk-ecdsa-cert-cc b/tf_config/fvp-tbb-mbedtls-rsa-ecdsa-with-rsa-rotpk-ecdsa-cert-cc
new file mode 100644
index 0000000..61253df
--- /dev/null
+++ b/tf_config/fvp-tbb-mbedtls-rsa-ecdsa-with-rsa-rotpk-ecdsa-cert-cc
@@ -0,0 +1,11 @@
+ARM_ROTPK_LOCATION=devel_rsa
+CROSS_COMPILE=aarch64-none-elf-
+ENABLE_ASSERTIONS=0
+GENERATE_COT=1
+KEY_ALG=ecdsa
+LOG_LEVEL=20
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+TF_MBEDTLS_KEY_ALG=rsa+ecdsa
+TRUSTED_BOARD_BOOT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tbb-mbedtls-upcounter-cc b/tf_config/fvp-tbb-mbedtls-upcounter-cc
new file mode 100644
index 0000000..761fc51
--- /dev/null
+++ b/tf_config/fvp-tbb-mbedtls-upcounter-cc
@@ -0,0 +1,8 @@
+ARM_ROTPK_LOCATION=devel_rsa
+CROSS_COMPILE=aarch64-none-elf-
+GENERATE_COT=1
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+TFW_NVCTR_VAL=32
+TRUSTED_BOARD_BOOT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tspd-aarch64-only-cc b/tf_config/fvp-tspd-aarch64-only-cc
new file mode 100644
index 0000000..878cbd4
--- /dev/null
+++ b/tf_config/fvp-tspd-aarch64-only-cc
@@ -0,0 +1,5 @@
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_AARCH32_REGS=0
+PLAT=fvp
+SPD=tspd
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tspd-cc b/tf_config/fvp-tspd-cc
index 1ec3ef5..184a3c6 100644
--- a/tf_config/fvp-tspd-cc
+++ b/tf_config/fvp-tspd-cc
@@ -1,4 +1,4 @@
CROSS_COMPILE=aarch64-none-elf-
-ENABLE_ASSERTIONS=0
PLAT=fvp
SPD=tspd
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tspd-quad-cluster-cc b/tf_config/fvp-tspd-quad-cluster-cc
new file mode 100644
index 0000000..e4de770
--- /dev/null
+++ b/tf_config/fvp-tspd-quad-cluster-cc
@@ -0,0 +1,5 @@
+CROSS_COMPILE=aarch64-none-elf-
+FVP_CLUSTER_COUNT=4
+PLAT=fvp
+SPD=tspd
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tspd-tbb-mbedtls-cc b/tf_config/fvp-tspd-tbb-mbedtls-cc
index 64a598b..655d8ca 100644
--- a/tf_config/fvp-tspd-tbb-mbedtls-cc
+++ b/tf_config/fvp-tspd-tbb-mbedtls-cc
@@ -1,8 +1,8 @@
ARM_ROTPK_LOCATION=devel_rsa
CROSS_COMPILE=aarch64-none-elf-
-ENABLE_ASSERTIONS=0
GENERATE_COT=1
PLAT=fvp
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
SPD=tspd
TRUSTED_BOARD_BOOT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tspd-tbb-mbedtls-dualroot-cc b/tf_config/fvp-tspd-tbb-mbedtls-dualroot-cc
new file mode 100644
index 0000000..52be814
--- /dev/null
+++ b/tf_config/fvp-tspd-tbb-mbedtls-dualroot-cc
@@ -0,0 +1,9 @@
+ARM_ROTPK_LOCATION=devel_rsa
+COT=dualroot
+CROSS_COMPILE=aarch64-none-elf-
+GENERATE_COT=1
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+SPD=tspd
+TRUSTED_BOARD_BOOT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tspd-tbb-mbedtls-ecdsa-dualroot-cc b/tf_config/fvp-tspd-tbb-mbedtls-ecdsa-dualroot-cc
new file mode 100644
index 0000000..dda259f
--- /dev/null
+++ b/tf_config/fvp-tspd-tbb-mbedtls-ecdsa-dualroot-cc
@@ -0,0 +1,12 @@
+ARM_ROTPK_LOCATION=devel_ecdsa
+COT=dualroot
+CROSS_COMPILE=aarch64-none-elf-
+ENABLE_ASSERTIONS=0
+GENERATE_COT=1
+KEY_ALG=ecdsa
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem
+SPD=tspd
+TF_MBEDTLS_KEY_ALG=rsa+ecdsa
+TRUSTED_BOARD_BOOT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tspd-tbb-mbedtls-pauth-cc b/tf_config/fvp-tspd-tbb-mbedtls-pauth-cc
index 7b4d333..9659b73 100644
--- a/tf_config/fvp-tspd-tbb-mbedtls-pauth-cc
+++ b/tf_config/fvp-tspd-tbb-mbedtls-pauth-cc
@@ -3,9 +3,10 @@
BRANCH_PROTECTION=1
CROSS_COMPILE=aarch64-none-elf-
CTX_INCLUDE_PAUTH_REGS=1
-ENABLE_ASSERTIONS=0
GENERATE_COT=1
PLAT=fvp
ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
SPD=tspd
TRUSTED_BOARD_BOOT=1
+USE_ROMLIB=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tspd-tbb-mbedtls-rsa-4k-cert-cc b/tf_config/fvp-tspd-tbb-mbedtls-rsa-4k-cert-cc
new file mode 100644
index 0000000..fed5232
--- /dev/null
+++ b/tf_config/fvp-tspd-tbb-mbedtls-rsa-4k-cert-cc
@@ -0,0 +1,9 @@
+ARM_ROTPK_LOCATION=devel_rsa
+CROSS_COMPILE=aarch64-none-elf-
+GENERATE_COT=1
+PLAT=fvp
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+SPD=tspd
+TRUSTED_BOARD_BOOT=1
+KEY_SIZE=4096
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-tspd-tsp-async-ehf-cc b/tf_config/fvp-tspd-tsp-async-ehf-cc
new file mode 100644
index 0000000..b9fe555
--- /dev/null
+++ b/tf_config/fvp-tspd-tsp-async-ehf-cc
@@ -0,0 +1,7 @@
+CROSS_COMPILE=aarch64-none-elf-
+EL3_EXCEPTION_HANDLING=1
+PLAT=fvp
+SPD=tspd
+TSP_INIT_ASYNC=1
+TSP_NS_INTR_ASYNC_PREEMPT=1
+ENABLE_ASSERTIONS=0
diff --git a/tf_config/fvp-ubsan-cc b/tf_config/fvp-ubsan-cc
new file mode 100644
index 0000000..65469b7
--- /dev/null
+++ b/tf_config/fvp-ubsan-cc
@@ -0,0 +1,4 @@
+CROSS_COMPILE=aarch64-none-elf-
+PLAT=fvp
+SANITIZE_UB=trap
+ENABLE_ASSERTIONS=0