TF-A: Add build and coverity config for RD-N2 platform
Add build configuration for SPMC AT EL3 and SP at SEL0 on RD-N2
platform to tf-l1-build-fvp build group and include it in coverity
makefile.
Change-Id: Ia66de33f7f1ffba2b9248a8db7700c7fe54d0cd6
Signed-off-by: Nishant Sharma <nishant.sharma@arm.com>
diff --git a/group/tf-l1-build-fvp/fvp-rdn2-tbb-el3_spmc_sel0_sp:nil b/group/tf-l1-build-fvp/fvp-rdn2-tbb-el3_spmc_sel0_sp:nil
new file mode 100644
index 0000000..c473896
--- /dev/null
+++ b/group/tf-l1-build-fvp/fvp-rdn2-tbb-el3_spmc_sel0_sp:nil
@@ -0,0 +1,6 @@
+#
+# Copyright (c) 2023, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
diff --git a/script/tf-coverity/tf-cov-make b/script/tf-coverity/tf-cov-make
index eda85ec..66e184d 100755
--- a/script/tf-coverity/tf-cov-make
+++ b/script/tf-coverity/tf-cov-make
@@ -262,6 +262,10 @@
# RAS Extension Support
make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} ENABLE_FEAT_RAS=1 \
RAS_FFH_SUPPORT=1 HANDLE_EA_EL3_FIRST_NS=1 SDEI_SUPPORT=1 SPM_MM=1 all
+# SPMC At EL3 Support
+make $(common_flags) PLAT=rdn2 ${ARM_TBB_OPTIONS} SPMC_AT_EL3=1 SPD=spmd \
+ SPMD_SPM_AT_SEL2=0 BL32=1 SPMC_AT_EL3_SEL0_SP=1 EL3_EXCEPTION_HANDLING=1 \
+ PLAT_RO_XLAT_TABLES=1 all
#
# Neoverse N1 SDP platform
diff --git a/tf_config/fvp-rdn2-tbb-el3_spmc_sel0_sp b/tf_config/fvp-rdn2-tbb-el3_spmc_sel0_sp
new file mode 100644
index 0000000..f069a56
--- /dev/null
+++ b/tf_config/fvp-rdn2-tbb-el3_spmc_sel0_sp
@@ -0,0 +1,14 @@
+ARM_ROTPK_LOCATION=devel_rsa
+CREATE_KEYS=1
+CROSS_COMPILE=aarch64-none-elf-
+GENERATE_COT=1
+PLAT=rdn2
+ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem
+TRUSTED_BOARD_BOOT=1
+SPMC_AT_EL3=1
+SPD=spmd
+SPMD_SPM_AT_SEL2=0
+BL32=1
+SPMC_AT_EL3_SEL0_SP=1
+EL3_EXCEPTION_HANDLING=1
+PLAT_RO_XLAT_TABLES=1