commit c3c572e4cfc206acdd345b437231173f0276d8b5
author Olivier Deprez <olivier.deprez@arm.com> Wed Mar 16 10:54:45 2022 +0100
committer Olivier Deprez <olivier.deprez@arm.com> Fri Apr 29 09:00:48 2022 +0200
tree a3f69390668ac53076192e5f63cd165544f2aa8e
parent 86e7f6882415d47405ebf3e6a3b81e8a509716fb

feat(smmu): add SMMU root register page parameter

Add the SMMU Root register page offset as model parameter when
a run config specifies has_smmuv3_params=1 and has_rme=1.
Add the smmu generic trace for RME enabled test cases.
Refactor to use a common set of smmu model parameters for both RME and
non-RME enabled case. The only parameter difference is SMMU_IDR5
defining 48 bits physical address size for RME enabled cases.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Ie53f0e29f592cd1e04b42feb04148f1c018d054c

model/base-aemva-common.sh

diff --git a/model/base-aemva-common.sh b/model/base-aemva-common.sh
index 1187d61..2d02364 100644
--- a/model/base-aemva-common.sh
+++ b/model/base-aemva-common.sh
@@ -195,28 +195,10 @@
 EOF
 
 if [ "$has_smmuv3_params" = "1" ]; then
-# The pci.pci_smmuv3.mmu.SMMU_IDR5
-# parameter is modified for 48 bit
-# physical address if rme is enabled.
-# Also ignores the tracing parameters.
-	if [ "$has_rme" = "1" ]; then
 		cat <<EOF >>"$model_param_file"
 -C pci.pci_smmuv3.mmu.SMMU_AIDR=2
--C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B
 -C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002
 -C pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714
--C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0475
--C pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002
--C pci.pci_smmuv3.mmu.SMMU_S_IDR2=0
--C pci.pci_smmuv3.mmu.SMMU_S_IDR3=0
-EOF
-	else
-		cat <<EOF >>"$model_param_file"
--C pci.pci_smmuv3.mmu.SMMU_AIDR=2
--C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B
--C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002
--C pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714
--C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472
 -C pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002
 -C pci.pci_smmuv3.mmu.SMMU_S_IDR2=0
 -C pci.pci_smmuv3.mmu.SMMU_S_IDR3=0
@@ -225,10 +207,32 @@
 -C pci.tbu0_pre_smmu_logger.trace_snoops=1
 -C pci.tbu0_pre_smmu_logger.trace_debug=1
 -C pci.pci_smmuv3.mmu.all_error_messages_through_trace=1
-
 -C TRACE.GenericTrace.trace-sources=verbose_commentary,smmu_initial_transaction,smmu_final_transaction,*.pci.pci_smmuv3.mmu.*,*.pci.smmulogger.*,*.pci.tbu0_pre_smmu_logger.*,smmu_poison_tw_data
 --plugin $warehouse/SysGen/PVModelLib/$model_version/$model_build/external/plugins/$model_flavour/GenericTrace.so
 EOF
+
+# If RME is implemented:
+# * pci.pci_smmuv3.mmu.SMMU_IDR5 defines 48 bit physical address size aligned
+#   with the model configuration for the PE.
+# * pci.pci_smmuv3.mmu.root_register_page_offset defines the (platform
+#   dependent) SMMU Root register page offset.
+# * SMMU_IDR0.RME_IMPL=1: RME features supported for non-secure and secure
+#   programming interface.
+# * pci.pci_smmuv3.mmu.SMMU_ROOT_IDR0=3: ROOT_IMPL=1/BGPTM=1.
+# * pci.pci_smmuv3.mmu.SMMU_ROOT_IIDR=0x43B: JEP106 Arm implementer code.
+	if [ "$has_rme" = "1" ]; then
+		cat <<EOF >>"$model_param_file"
+-C pci.pci_smmuv3.mmu.SMMU_IDR0=0x4046123b
+-C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0475
+-C pci.pci_smmuv3.mmu.SMMU_ROOT_IDR0=3
+-C pci.pci_smmuv3.mmu.SMMU_ROOT_IIDR=0x43B
+-C pci.pci_smmuv3.mmu.root_register_page_offset=0x20000
+EOF
+	else
+		cat <<EOF >>"$model_param_file"
+-C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B
+-C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472
+EOF
 	fi
 fi