diff --git a/group/tf-l1-build-fvp/fvp-errata-all:nil b/group/tf-l1-build-fvp/fvp-errata-all:nil
new file mode 100644
index 0000000..8e42dc9
--- /dev/null
+++ b/group/tf-l1-build-fvp/fvp-errata-all:nil
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2025 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/script/tf-coverity/tf-cov-make b/script/tf-coverity/tf-cov-make
index 2c77fa1..7c19a7e 100755
--- a/script/tf-coverity/tf-cov-make
+++ b/script/tf-coverity/tf-cov-make
@@ -1,6 +1,6 @@
 #!/usr/bin/env bash
 #
-# Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -259,6 +259,10 @@
 clean_build $fvp_common_flags CTX_INCLUDE_AARCH32_REGS=0 HW_ASSISTED_COHERENCY=1 \
     USE_COHERENT_MEM=0 BUILD_CPUS_WITH_NO_FVP_MODEL=1 FVP_TRUSTED_SRAM_SIZE=384
 
+# Build all CPU's with all errata's with FVP platform.
+clean_build $fvp_common_flags CTX_INCLUDE_AARCH32_REGS=0 HW_ASSISTED_COHERENCY=1 \
+    USE_COHERENT_MEM=0 ENABLE_ERRATA_ALL=1 FVP_TRUSTED_SRAM_SIZE=384
+
 # Sign Realm tokens with EL3 signing service
 clean_build $fvp_common_flags ENABLE_RME=1 RMMD_ENABLE_EL3_TOKEN_SIGN=1
 
diff --git a/tf_config/fvp-errata-all b/tf_config/fvp-errata-all
new file mode 100644
index 0000000..fcfea37
--- /dev/null
+++ b/tf_config/fvp-errata-all
@@ -0,0 +1,7 @@
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_AARCH32_REGS=0
+ENABLE_ERRATA_ALL=1
+FVP_TRUSTED_SRAM_SIZE=384
+HW_ASSISTED_COHERENCY=1
+PLAT=fvp
+USE_COHERENT_MEM=0