Sync run_config files with internal CI
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
Change-Id: I0b8e637832f85ad9f36355632ece115c696a8274
diff --git a/run_config/coverity-misra.full b/run_config/coverity-misra.full
index 419859a..0efabfa 100644
--- a/run_config/coverity-misra.full
+++ b/run_config/coverity-misra.full
@@ -10,7 +10,7 @@
append_hook_var "cov_options" " ${coverity_default_checkers[*]}"
append_hook_var "cov_options" \
- " --coding-standard-config $ci_root/coverity/MISRA_c2012_1_ARM_TF.config"
+ " --coding-standard-config $ci_root/coverity/MISRA_c2012_2_ARM_TF.config"
# Branch description
set_hook_var "cov_checker" "misra"
diff --git a/run_config/fip.dummy b/run_config/fip.dummy
new file mode 100644
index 0000000..5c0a556
--- /dev/null
+++ b/run_config/fip.dummy
@@ -0,0 +1,21 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# This run fragment is used to generate a dummy FIP. The resulting file is not
+# functional and cannot be used in a real run on a platform.
+#
+# This is useful in cases where we want to build a FIP in addition to the
+# individual firmware binaries.
+
+post_tf_build() {
+ # Create non-empty dummy images to include in the FIP.
+ local dummy_file="$(mktempfile)"
+ echo "hello world" > "$dummy_file"
+
+ build_fip BL33="$dummy_file" BL32="$dummy_file" \
+ BL32_EXTRA1="$dummy_file" BL32_EXTRA2="$dummy_file"
+}
diff --git a/run_config/fvp-aem8a.singlecluster b/run_config/fvp-aem8a.singlecluster
new file mode 100755
index 0000000..e38dadd
--- /dev/null
+++ b/run_config/fvp-aem8a.singlecluster
@@ -0,0 +1,15 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="base-aemv8a" \
+ cluster_0_num_cores="4" \
+ cluster_1_num_cores="0" \
+ cluster_2_num_cores="0" \
+ cluster_3_num_cores="0" \
+ gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.8_5 b/run_config/fvp-aemv8a.8_5
new file mode 100644
index 0000000..e2922fe
--- /dev/null
+++ b/run_config/fvp-aemv8a.8_5
@@ -0,0 +1,12 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="base-aemv8a" \
+ arch_version="8.5" \
+ gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.8_5+mte b/run_config/fvp-aemv8a.8_5+mte
new file mode 100644
index 0000000..3663550
--- /dev/null
+++ b/run_config/fvp-aemv8a.8_5+mte
@@ -0,0 +1,16 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="base-aemv8a" \
+ model_version="11.8" \
+ model_build="37" \
+ arch_version="8.5" \
+ cache_state_modelled="0" \
+ memory_tagging_support_level="2" \
+ gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.8_5.bmcov b/run_config/fvp-aemv8a.8_5.bmcov
new file mode 100644
index 0000000..038db14
--- /dev/null
+++ b/run_config/fvp-aemv8a.8_5.bmcov
@@ -0,0 +1,13 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ bmcov_plugin=1 bmcov_plugin_path="${coverage_trace_plugin}" \
+ model="base-aemv8a" \
+ arch_version="8.5" \
+ gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.NVM_reboot b/run_config/fvp-aemv8a.NVM_reboot
new file mode 100644
index 0000000..cca71c2
--- /dev/null
+++ b/run_config/fvp-aemv8a.NVM_reboot
@@ -0,0 +1,34 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_archive() {
+ echo "Creating flash files which serve as Non-volatile Memory across reboots"
+ rm -f "$archive/flash0"
+ rm -f "$archive/flash1"
+ touch "$archive/flash0"
+ touch "$archive/flash1"
+
+ set_run_env "run_tftf_reboot_tests" "1"
+ # Contents of Non Volatile Memory are written to this file
+ set_run_env "NVM_file" "flash0"
+}
+
+post_fetch_tf_resource() {
+ uart0_log=$(echo uart-0-`date "+%H:%M:%S"`.log)
+ uart1_log=$(echo uart-1-`date "+%H:%M:%S"`.log)
+ set_run_env "uart0_file" "$uart0_log"
+ set_run_env "uart1_file" "$uart1_log"
+
+ model="base-aemv8a" retain_flash="1" secure_memory="0" \
+ cluster_0_num_cores="1" cluster_1_num_cores="1" \
+ cache_state_modelled="0" \
+ uart0_out="$uart0_log" \
+ uart1_out="$uart1_log" \
+ flashloader0_fwrite="flash0" \
+ flashloader1_fwrite="flash1" \
+ gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.aarch32+8_4 b/run_config/fvp-aemv8a.aarch32+8_4
new file mode 100644
index 0000000..1e15bf6
--- /dev/null
+++ b/run_config/fvp-aemv8a.aarch32+8_4
@@ -0,0 +1,11 @@
+#!/bin/bash
+#
+# Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ aarch32="1" model="base-aemv8a" arch_version="8.4" \
+ gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.aarch32+bl2_el3 b/run_config/fvp-aemv8a.aarch32+bl2_el3
new file mode 100644
index 0000000..1567d7d
--- /dev/null
+++ b/run_config/fvp-aemv8a.aarch32+bl2_el3
@@ -0,0 +1,15 @@
+#!/bin/bash
+#
+# Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ bl2_at_el3="1" \
+ aarch32="1" \
+ bl2_addr="0x4022000" \
+ model="base-aemv8a" gen_model_params
+
+ uart="0" set_expect_variable "skip_early_boot_msgs" "1"
+}
diff --git a/run_config/fvp-aemv8a.aarch32+memprotect b/run_config/fvp-aemv8a.aarch32+memprotect
new file mode 100644
index 0000000..83b4422
--- /dev/null
+++ b/run_config/fvp-aemv8a.aarch32+memprotect
@@ -0,0 +1,18 @@
+#!/bin/bash
+#
+# Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ image=$(mktempfile)
+ printf '\1\0\0\0' > "$image"
+
+ aarch32="1" \
+ reset_to_spmin="1" \
+ cache_state_modelled="0" \
+ memprotect="$image" \
+ memprotect_addr="0xBFC0000" \
+ model="base-aemv8a" gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.aarch32+regreset b/run_config/fvp-aemv8a.aarch32+regreset
new file mode 100644
index 0000000..9e54b20
--- /dev/null
+++ b/run_config/fvp-aemv8a.aarch32+regreset
@@ -0,0 +1,13 @@
+#!/bin/bash
+#
+# Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ cluster_0_reg_reset="0xffffffff" \
+ cluster_1_reg_reset="0xffffffff" \
+ aarch32=1 \
+ model="base-aemv8a" gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.aarch32.8_3 b/run_config/fvp-aemv8a.aarch32.8_3
new file mode 100644
index 0000000..d38f0f0
--- /dev/null
+++ b/run_config/fvp-aemv8a.aarch32.8_3
@@ -0,0 +1,13 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="base-aemv8a" \
+ arch_version="8.3" \
+ aarch32="1" \
+ gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.aarch32.NVM_reboot b/run_config/fvp-aemv8a.aarch32.NVM_reboot
new file mode 100644
index 0000000..c3b3621
--- /dev/null
+++ b/run_config/fvp-aemv8a.aarch32.NVM_reboot
@@ -0,0 +1,34 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_archive() {
+ echo "Creating flash files which serve as Non-volatile Memory across reboots"
+ rm -f "$archive/flash0"
+ rm -f "$archive/flash1"
+ touch "$archive/flash0"
+ touch "$archive/flash1"
+
+ set_run_env "run_tftf_reboot_tests" "1"
+ # Contents of Non Volatile Memory are written to this file
+ set_run_env "NVM_file" "flash0"
+}
+
+post_fetch_tf_resource() {
+ uart0_log=$(echo uart-0-`date "+%H:%M:%S"`.log)
+ uart1_log=$(echo uart-1-`date "+%H:%M:%S"`.log)
+ set_run_env "uart0_file" "$uart0_log"
+ set_run_env "uart1_file" "$uart1_log"
+
+ aarch32="1" model="base-aemv8a" retain_flash="1" \
+ cluster_0_num_cores="1" cluster_1_num_cores="1" \
+ cache_state_modelled="0" secure_memory="0" \
+ uart0_out="$uart0_log" \
+ uart1_out="$uart1_log" \
+ flashloader0_fwrite="flash0" \
+ flashloader1_fwrite="flash1" \
+ gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.aarch32.nocache b/run_config/fvp-aemv8a.aarch32.nocache
new file mode 100644
index 0000000..7464390
--- /dev/null
+++ b/run_config/fvp-aemv8a.aarch32.nocache
@@ -0,0 +1,10 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ cache_state_modelled="0" aarch32="1" model="base-aemv8a" gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.aarch32.roxlattables.spmin_panic b/run_config/fvp-aemv8a.aarch32.roxlattables.spmin_panic
new file mode 100644
index 0000000..727d97d
--- /dev/null
+++ b/run_config/fvp-aemv8a.aarch32.roxlattables.spmin_panic
@@ -0,0 +1,25 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+pre_tf_build() {
+ # Apply a patch which attempts to write to the translation tables (by
+ # changing the memory attributes of a region) immediately after the
+ # translation tables have been made read-only, triggering a data abort.
+ apply_tf_patch "readonly_xlat_tables/arm_sp_min_setup_write_after_readonly.patch"
+ # Apply patch which allows a 'Panic at PC:...' message to be printed
+ # when the data abort happens.
+ apply_tf_patch "readonly_xlat_tables/sp_min_data_abort_print_panic_message.patch"
+}
+
+post_tf_archive() {
+ aarch32="1" model="base-aemv8a" gen_model_params
+}
+
+fetch_tf_resource() {
+ uart="0" timeout="60" file="timeout_spmin_roxlattables.exp" track_expect
+ uart="1" timeout="60" file="crash_panic.exp" track_expect
+}
diff --git a/run_config/fvp-aemv8a.amu b/run_config/fvp-aemv8a.amu
new file mode 100644
index 0000000..a329d76
--- /dev/null
+++ b/run_config/fvp-aemv8a.amu
@@ -0,0 +1,9 @@
+#!/bin/bash
+
+post_fetch_tf_resource() {
+ model="base-aemv8a" \
+ arch_version="8.4" \
+ amu_present="1" \
+ cache_state_modelled="0" \
+ gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.amu.aarch32 b/run_config/fvp-aemv8a.amu.aarch32
new file mode 100644
index 0000000..32f635e
--- /dev/null
+++ b/run_config/fvp-aemv8a.amu.aarch32
@@ -0,0 +1,10 @@
+#!/bin/bash
+
+post_fetch_tf_resource() {
+ model="base-aemv8a" \
+ arch_version="8.4" \
+ amu_present="1" \
+ aarch32="1" \
+ cache_state_modelled="0" \
+ gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.amu.bmcov b/run_config/fvp-aemv8a.amu.bmcov
new file mode 100644
index 0000000..3fb574e
--- /dev/null
+++ b/run_config/fvp-aemv8a.amu.bmcov
@@ -0,0 +1,10 @@
+#!/bin/bash
+
+post_fetch_tf_resource() {
+ bmcov_plugin=1 bmcov_plugin_path="${coverage_trace_plugin}" \
+ model="base-aemv8a" \
+ arch_version="8.4" \
+ amu_present="1" \
+ cache_state_modelled="0" \
+ gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.assymetric.bmcov b/run_config/fvp-aemv8a.assymetric.bmcov
new file mode 100644
index 0000000..5a608cc
--- /dev/null
+++ b/run_config/fvp-aemv8a.assymetric.bmcov
@@ -0,0 +1,19 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ bmcov_plugin=1 bmcov_plugin_path="${coverage_trace_plugin}" \
+ arch_version="8.3" \
+ cluster_0_reg_reset="0xffffffff" \
+ cluster_0_has_el2="0" \
+ cluster_1_reg_reset="0xffffffff" \
+ cluster_1_has_el2="0" \
+ cluster_0_num_cores="2" \
+ cluster_1_num_cores="3" \
+ model="base-aemv8a" gen_model_params
+ uart="0" set_expect_variable "num_cpus" "5"
+}
diff --git a/run_config/fvp-aemv8a.bmcov b/run_config/fvp-aemv8a.bmcov
new file mode 100644
index 0000000..dc2e984
--- /dev/null
+++ b/run_config/fvp-aemv8a.bmcov
@@ -0,0 +1,11 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ bmcov_plugin=1 bmcov_plugin_path="${coverage_trace_plugin}" \
+ model="base-aemv8a" gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.crash b/run_config/fvp-aemv8a.crash
new file mode 100644
index 0000000..edf3058
--- /dev/null
+++ b/run_config/fvp-aemv8a.crash
@@ -0,0 +1,23 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+
+pre_tf_build() {
+ # Apply fault injection patches
+ apply_tf_patch "fault_inject/injected-fault-in-absence-of-ras.patch"
+ apply_tf_patch "fault_inject/explicit-events.patch"
+}
+
+post_tf_archive() {
+ model="base-aemv8a" fault_inject="1" arch_version="8.4" \
+ gen_model_params
+}
+
+fetch_tf_resource() {
+ uart="0" timeout="60" file="timeout_test.exp" track_expect
+ uart="1" timeout="60" file="crash_test.exp" track_expect
+}
diff --git a/run_config/fvp-aemv8a.gicv3_spi b/run_config/fvp-aemv8a.gicv3_spi
new file mode 100644
index 0000000..d1250d5
--- /dev/null
+++ b/run_config/fvp-aemv8a.gicv3_spi
@@ -0,0 +1,12 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="base-aemv8a" \
+ gicv3_spi_count="988" \
+ gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.gicv4 b/run_config/fvp-aemv8a.gicv4
new file mode 100644
index 0000000..d847f7a
--- /dev/null
+++ b/run_config/fvp-aemv8a.gicv4
@@ -0,0 +1,19 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="base-aemv8a" \
+ gicd_are_fixed_one="1" \
+ gicd_ext_ppi_count="64" \
+ gicd_ext_spi_count="1024" \
+ gicd_its_count="1" \
+ gicd_virtual_lpi="1" \
+ gicv3_ext_interrupt_range="1" \
+ gicv3_spi_count="988" \
+ has_gicv4_1="0" \
+ gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.invalid_nvcounter b/run_config/fvp-aemv8a.invalid_nvcounter
new file mode 100644
index 0000000..bca24e0
--- /dev/null
+++ b/run_config/fvp-aemv8a.invalid_nvcounter
@@ -0,0 +1,13 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ # The Trusted non-volatile counter is invalid. Authentication of BL2
+ # image is expected to fail.
+ uart="0" file="trusted-firmware-load-error.exp" track_expect
+ model="base-aemv8a" nvcounter_diag="4" gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.nvcounter_v1 b/run_config/fvp-aemv8a.nvcounter_v1
new file mode 100644
index 0000000..b416faf
--- /dev/null
+++ b/run_config/fvp-aemv8a.nvcounter_v1
@@ -0,0 +1,12 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ # Version 1 of the non-volatile counter may be incremented in a
+ # monotonic fashion (unlike version 0, which is fixed).
+ model="base-aemv8a" nvcounter_version="r1" nvcounter_diag="4" gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.pl33.bmcov b/run_config/fvp-aemv8a.pl33.bmcov
new file mode 100644
index 0000000..a0b51d5
--- /dev/null
+++ b/run_config/fvp-aemv8a.pl33.bmcov
@@ -0,0 +1,18 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ # Build FIP without any BL33 image (it is preloaded)
+ build_fip
+}
+
+post_fetch_tf_resource() {
+ bmcov_plugin=1 bmcov_plugin_path="${coverage_trace_plugin}" \
+ preload_bl33="1" \
+ preload_bl33_bin="tftf.bin" \
+ model="base-aemv8a" gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.quad b/run_config/fvp-aemv8a.quad
new file mode 100644
index 0000000..25e7294
--- /dev/null
+++ b/run_config/fvp-aemv8a.quad
@@ -0,0 +1,13 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="base-aemv8a-quad" \
+ cache_state_modelled="0" \
+ gen_model_params
+ uart="0" set_expect_variable "num_cpus" "16"
+}
diff --git a/run_config/fvp-aemv8a.roxlattables.bl31_panic b/run_config/fvp-aemv8a.roxlattables.bl31_panic
new file mode 100644
index 0000000..6ad697d
--- /dev/null
+++ b/run_config/fvp-aemv8a.roxlattables.bl31_panic
@@ -0,0 +1,23 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+pre_tf_build() {
+ # Apply a patch which attempts to write to the translation tables (by
+ # changing the memory attributes of a region) immediately after the
+ # translation tables have been made read-only, triggering an unhandled
+ # exception at EL3.
+ apply_tf_patch "readonly_xlat_tables/arm_bl31_setup_write_after_readonly.patch"
+}
+
+post_tf_archive() {
+ model="base-aemv8a" gen_model_params
+}
+
+fetch_tf_resource() {
+ uart="0" timeout="60" file="timeout.exp" track_expect
+ uart="1" timeout="60" file="crash_roxlattables_unhandled_exception_at_el3.exp" track_expect
+}
diff --git a/run_config/fvp-aemv8a.roxlattables.tspd_panic b/run_config/fvp-aemv8a.roxlattables.tspd_panic
new file mode 100644
index 0000000..31a47af
--- /dev/null
+++ b/run_config/fvp-aemv8a.roxlattables.tspd_panic
@@ -0,0 +1,27 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+pre_tf_build() {
+ # Apply a patch which attempts to write to the translation tables (by
+ # changing the memory attributes of a region) immediately after the
+ # translation tables have been made read-only, triggering a synchronous
+ # exception.
+ apply_tf_patch "readonly_xlat_tables/arm_tsp_setup_write_after_readonly.patch"
+ # Apply patch which allows a 'Panic at PC:...' message to be printed
+ # when the synchronous exception happens.
+ apply_tf_patch "readonly_xlat_tables/tsp_sync_exception_print_panic_message.patch"
+}
+
+post_tf_archive() {
+ model="base-aemv8a" gen_model_params
+}
+
+fetch_tf_resource() {
+ uart="0" timeout="60" file="timeout.exp" track_expect
+ uart="1" timeout="60" file="crash_panic.exp" track_expect
+ uart="2" timeout="60" file="readonly_el1_xlat_tables.exp" track_expect
+}
diff --git a/run_config/fvp-aemv8a.rstspmin b/run_config/fvp-aemv8a.rstspmin
new file mode 100644
index 0000000..32c84ad
--- /dev/null
+++ b/run_config/fvp-aemv8a.rstspmin
@@ -0,0 +1,12 @@
+#!/bin/bash
+#
+# Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ reset_to_spmin="1" \
+ aarch32="1" \
+ model="base-aemv8a" gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.singlecore.bmcov b/run_config/fvp-aemv8a.singlecore.bmcov
new file mode 100644
index 0000000..2701771
--- /dev/null
+++ b/run_config/fvp-aemv8a.singlecore.bmcov
@@ -0,0 +1,13 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ bmcov_plugin=1 bmcov_plugin_path="${coverage_trace_plugin}" \
+ model="base-aemv8a" cluster_0_num_cores="1" cluster_1_num_cores="0" \
+ gen_model_params
+ uart="0" set_expect_variable "num_cpus" "1"
+}
diff --git a/run_config/fvp-aemv8a.sve.bmcov b/run_config/fvp-aemv8a.sve.bmcov
new file mode 100644
index 0000000..e7ec951
--- /dev/null
+++ b/run_config/fvp-aemv8a.sve.bmcov
@@ -0,0 +1,12 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ bmcov_plugin=1 bmcov_plugin_path="${coverage_trace_plugin}" \
+ sve_plugin=1 \
+ model="base-aemv8a" gen_model_params
+}
diff --git a/run_config/fvp-aemv8a.tbb.disable_dyn_auth b/run_config/fvp-aemv8a.tbb.disable_dyn_auth
new file mode 100644
index 0000000..feda3f3
--- /dev/null
+++ b/run_config/fvp-aemv8a.tbb.disable_dyn_auth
@@ -0,0 +1,20 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+pre_tf_build() {
+ # Apply a patch which disables dynamic authentication
+ # of images during trusted board boot.
+ apply_tf_patch "tbb_dyn_auth/disable_dyn_auth.patch"
+}
+
+post_tf_archive() {
+ model="base-aemv8a" gen_model_params
+}
+
+fetch_tf_resource() {
+ uart="0" timeout="60" file="disable_dyn_auth.exp" track_expect
+}
diff --git a/run_config/fvp-aemv8a.ubsan_test b/run_config/fvp-aemv8a.ubsan_test
new file mode 100644
index 0000000..ac2da46
--- /dev/null
+++ b/run_config/fvp-aemv8a.ubsan_test
@@ -0,0 +1,21 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+pre_tf_build() {
+ # Apply ubsan test patch
+ apply_tf_patch "ubsan/ubsan_test.patch"
+}
+
+post_tf_archive() {
+ model="base-aemv8a" \
+ gen_model_params
+}
+
+fetch_tf_resource() {
+ # Expect trap message on uart 1
+ uart="1" set_primary="1" file="ubsan-test-trap.exp" track_expect
+}
diff --git a/run_config/fvp-aemva b/run_config/fvp-aemva
new file mode 100644
index 0000000..89f9a71
--- /dev/null
+++ b/run_config/fvp-aemva
@@ -0,0 +1,12 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="base-aemva" \
+ gen_model_params
+ uart="0" set_expect_variable "num_cpus" "4"
+}
diff --git a/run_config/fvp-aemva.8_6 b/run_config/fvp-aemva.8_6
new file mode 100644
index 0000000..cd8f285
--- /dev/null
+++ b/run_config/fvp-aemva.8_6
@@ -0,0 +1,13 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="base-aemva" \
+ arch_version="8.6" \
+ gen_model_params
+ uart="0" set_expect_variable "num_cpus" "4"
+}
diff --git a/run_config/fvp-aemva.aarch32 b/run_config/fvp-aemva.aarch32
new file mode 100644
index 0000000..ebf9443
--- /dev/null
+++ b/run_config/fvp-aemva.aarch32
@@ -0,0 +1,10 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ aarch32="1" model="base-aemva" gen_model_params
+}
diff --git a/run_config/fvp-cortexa55x4 b/run_config/fvp-cortexa55x4
index 3651771..ed6529a 100644
--- a/run_config/fvp-cortexa55x4
+++ b/run_config/fvp-cortexa55x4
@@ -6,6 +6,8 @@
#
post_fetch_tf_resource() {
- model="cortex-a55x4" gen_model_params
+ model="cortex-a55x4" \
+ cache_state_modelled="0" \
+ gen_model_params
uart="0" set_expect_variable "num_cpus" "4"
}
diff --git a/run_config/fvp-cortexa55x4a75x4 b/run_config/fvp-cortexa55x4a75x4
index b5d50ba..96b5e1f 100644
--- a/run_config/fvp-cortexa55x4a75x4
+++ b/run_config/fvp-cortexa55x4a75x4
@@ -6,5 +6,7 @@
#
post_fetch_tf_resource() {
- model="cortex-a55x4-a75x4" gen_model_params
+ model="cortex-a55x4-a75x4" \
+ cache_state_modelled="0" \
+ gen_model_params
}
diff --git a/run_config/fvp-cortexa55x4a76x2 b/run_config/fvp-cortexa55x4a76x2
new file mode 100644
index 0000000..fbb13c5
--- /dev/null
+++ b/run_config/fvp-cortexa55x4a76x2
@@ -0,0 +1,13 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="cortex-a55x4-a76x2" \
+ cache_state_modelled="0" \
+ gen_model_params
+ uart="0" set_expect_variable "num_cpus" "6"
+}
diff --git a/run_config/fvp-cortexa65aex8 b/run_config/fvp-cortexa65aex8
new file mode 100644
index 0000000..5881038
--- /dev/null
+++ b/run_config/fvp-cortexa65aex8
@@ -0,0 +1,13 @@
+#!/bin/bash
+#
+# Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="cortex-a65aex8" \
+ data_instance="cluster0.cpu0.thread0" \
+ gen_model_params
+ uart="0" set_expect_variable "num_cpus" "16"
+}
diff --git a/run_config/fvp-cortexa65x4 b/run_config/fvp-cortexa65x4
new file mode 100644
index 0000000..20bc423
--- /dev/null
+++ b/run_config/fvp-cortexa65x4
@@ -0,0 +1,16 @@
+#!/bin/bash
+#
+# Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# data_instance must be set to cluster0.cpu0.thread0 because the model does not accept --data
+# parameter on the default cluster0.cpu0 instance.
+
+post_fetch_tf_resource() {
+ model="cortex-a65x4" \
+ data_instance="cluster0.cpu0.thread0" \
+ gen_model_params
+ uart="0" set_expect_variable "num_cpus" "8"
+}
diff --git a/run_config/fvp-cortexa75x4 b/run_config/fvp-cortexa75x4
index 4c8cb1c..110834b 100644
--- a/run_config/fvp-cortexa75x4
+++ b/run_config/fvp-cortexa75x4
@@ -6,6 +6,8 @@
#
post_fetch_tf_resource() {
- model="cortex-a75x4" gen_model_params
+ model="cortex-a75x4" \
+ cache_state_modelled="0" \
+ gen_model_params
uart="0" set_expect_variable "num_cpus" "4"
}
diff --git a/run_config/fvp-cortexa76aex4 b/run_config/fvp-cortexa76aex4
new file mode 100644
index 0000000..a376978
--- /dev/null
+++ b/run_config/fvp-cortexa76aex4
@@ -0,0 +1,13 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="cortex-a76aex4" \
+ cache_state_modelled="0" \
+ gen_model_params
+ uart="0" set_expect_variable "num_cpus" "4"
+}
diff --git a/run_config/fvp-cortexa76x4 b/run_config/fvp-cortexa76x4
index acba38b..196cd5e 100644
--- a/run_config/fvp-cortexa76x4
+++ b/run_config/fvp-cortexa76x4
@@ -6,6 +6,8 @@
#
post_fetch_tf_resource() {
- model="cortex-a76x4" gen_model_params
+ model="cortex-a76x4" \
+ cache_state_modelled="0" \
+ gen_model_params
uart="0" set_expect_variable "num_cpus" "4"
}
diff --git a/run_config/fvp-cortexa77x4 b/run_config/fvp-cortexa77x4
new file mode 100644
index 0000000..8bbf9c4
--- /dev/null
+++ b/run_config/fvp-cortexa77x4
@@ -0,0 +1,13 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="cortex-a77x4" \
+ cache_state_modelled="0" \
+ gen_model_params
+ uart="0" set_expect_variable "num_cpus" "4"
+}
diff --git a/run_config/fvp-dtb.aarch32.1t b/run_config/fvp-dtb.aarch32.1t
new file mode 100644
index 0000000..9b2e983
--- /dev/null
+++ b/run_config/fvp-dtb.aarch32.1t
@@ -0,0 +1,11 @@
+#!/bin/bash
+#
+# Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+fetch_tf_resource() {
+ dtb_type="fvp-base-gicv3-psci-aarch32-1t" get_dtb
+ update_fip_hw_config
+}
diff --git a/run_config/fvp-dtb.dyn.2t b/run_config/fvp-dtb.dyn.2t
new file mode 100644
index 0000000..a852003
--- /dev/null
+++ b/run_config/fvp-dtb.dyn.2t
@@ -0,0 +1,11 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+fetch_tf_resource() {
+ dtb_type="fvp-base-gicv3-psci-dynamiq-2t" get_dtb
+ update_fip_hw_config
+}
diff --git a/run_config/fvp-dtb.quad b/run_config/fvp-dtb.quad
new file mode 100644
index 0000000..f81c81b
--- /dev/null
+++ b/run_config/fvp-dtb.quad
@@ -0,0 +1,11 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+fetch_tf_resource() {
+ dtb_type="fvp-base-quad-cluster-gicv3-psci" get_dtb
+ update_fip_hw_config
+}
diff --git a/run_config/fvp-fip.tc0 b/run_config/fvp-fip.tc0
new file mode 100644
index 0000000..d3096f7
--- /dev/null
+++ b/run_config/fvp-fip.tc0
@@ -0,0 +1,19 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ url="$tc_prebuilts/u-boot.bin" fetch_file
+ archive_file "u-boot.bin"
+
+ # Use SCP binary from SCP build if it exists, or fetch pre-built ones.
+ if [ ! -f "$archive/scp_ramfw.bin" ]; then
+ url="$tc_prebuilts/scp_ramfw.bin" fetch_file
+ archive_file "scp_ramfw.bin"
+ fi
+
+ build_fip BL33="$archive/u-boot.bin" SCP_BL2="$archive/scp_ramfw.bin"
+}
diff --git a/run_config/fvp-foundationv8.bmcov b/run_config/fvp-foundationv8.bmcov
new file mode 100644
index 0000000..528d638
--- /dev/null
+++ b/run_config/fvp-foundationv8.bmcov
@@ -0,0 +1,12 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ bmcov_plugin=1 bmcov_plugin_path="${coverage_trace_plugin}" \
+ model="foundationv8" gen_model_params
+ uart="0" set_expect_variable "num_cpus" "4"
+}
diff --git a/run_config/fvp-hercules b/run_config/fvp-hercules
new file mode 100644
index 0000000..746bb16
--- /dev/null
+++ b/run_config/fvp-hercules
@@ -0,0 +1,8 @@
+#!/bin/bash
+
+post_fetch_tf_resource() {
+ model="hercules" \
+ cache_state_modelled="0" \
+ gen_model_params
+ uart="0" set_expect_variable "num_cpus" "4"
+}
diff --git a/run_config/fvp-linux.quad b/run_config/fvp-linux.quad
new file mode 100644
index 0000000..a2b4edc
--- /dev/null
+++ b/run_config/fvp-linux.quad
@@ -0,0 +1,12 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+fetch_tf_resource() {
+ kernel_type="fvp-quad-busybox-uboot" get_kernel
+ initrd_type="default" get_initrd
+ uart="0" file="linux-rd-busybox.exp" track_expect
+}
diff --git a/run_config/fvp-linux.tc0 b/run_config/fvp-linux.tc0
new file mode 100644
index 0000000..4d2f607
--- /dev/null
+++ b/run_config/fvp-linux.tc0
@@ -0,0 +1,12 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+fetch_tf_resource() {
+ kernel_type="fvp-tc-kernel" get_kernel
+ initrd_type="fvp-tc-ramdisk" get_initrd
+ uart="1" set_primary="1" file="linux-rd-busybox.exp" track_expect
+}
diff --git a/run_config/fvp-linux32.rstspmin b/run_config/fvp-linux32.rstspmin
index f9e09ff..a827471 100644
--- a/run_config/fvp-linux32.rstspmin
+++ b/run_config/fvp-linux32.rstspmin
@@ -1,6 +1,6 @@
#!/bin/bash
#
-# Copyright (c) 2019, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2020, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -8,5 +8,6 @@
fetch_tf_resource() {
kernel_type="fvp-aarch32-zimage" get_kernel
initrd_type="aarch32-ramdisk" get_initrd
- uart="0" file="linux-rd-aarch32-rst-sp-min.exp" track_expect
+ uart="0" file="linux-rd-busybox-aarch32.exp" track_expect
+ uart="0" set_expect_variable "skip_early_boot_msgs" "1"
}
diff --git a/run_config/fvp-neoverse_e1x1 b/run_config/fvp-neoverse_e1x1
new file mode 100644
index 0000000..2df5db3
--- /dev/null
+++ b/run_config/fvp-neoverse_e1x1
@@ -0,0 +1,14 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="neoverse_e1x1" \
+ cache_state_modelled="1" \
+ data_instance="cluster0.cpu0.thread0" \
+ gen_model_params
+ uart="0" set_expect_variable "num_cpus" "2"
+}
diff --git a/run_config/fvp-neoverse_e1x2 b/run_config/fvp-neoverse_e1x2
new file mode 100644
index 0000000..c48e798
--- /dev/null
+++ b/run_config/fvp-neoverse_e1x2
@@ -0,0 +1,14 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="neoverse_e1x2" \
+ cache_state_modelled="1" \
+ data_instance="cluster0.cpu0.thread0" \
+ gen_model_params
+ uart="0" set_expect_variable "num_cpus" "4"
+}
diff --git a/run_config/fvp-neoverse_e1x4 b/run_config/fvp-neoverse_e1x4
new file mode 100644
index 0000000..938a025
--- /dev/null
+++ b/run_config/fvp-neoverse_e1x4
@@ -0,0 +1,14 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="neoverse_e1x4" \
+ cache_state_modelled="1" \
+ data_instance="cluster0.cpu0.thread0" \
+ gen_model_params
+ uart="0" set_expect_variable "num_cpus" "8"
+}
diff --git a/run_config/fvp-neoverse_n1x4 b/run_config/fvp-neoverse_n1x4
index f28994c..e990f30 100644
--- a/run_config/fvp-neoverse_n1x4
+++ b/run_config/fvp-neoverse_n1x4
@@ -6,6 +6,8 @@
#
post_fetch_tf_resource() {
- model="neoverse_n1" gen_model_params
+ model="neoverse_n1" \
+ cache_state_modelled="0" \
+ gen_model_params
uart="0" set_expect_variable "num_cpus" "4"
}
diff --git a/run_config/fvp-romlib b/run_config/fvp-romlib
index 0310866..3b47119 100644
--- a/run_config/fvp-romlib
+++ b/run_config/fvp-romlib
@@ -8,3 +8,7 @@
post_tf_build() {
fvp_romlib_runtime
}
+
+post_tf_archive() {
+ fvp_romlib_cleanup
+}
diff --git a/run_config/fvp-spm b/run_config/fvp-spm
new file mode 100644
index 0000000..6549551
--- /dev/null
+++ b/run_config/fvp-spm
@@ -0,0 +1,26 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ url="$project_filer/ci-files/spm-05-19-2020/secure_hafnium.bin" fetch_file
+
+ archive_file "secure_hafnium.bin"
+
+ build_fip BL33="$archive/tftf.bin" BL32="$archive/secure_hafnium.bin"
+}
+
+post_fetch_tf_resource() {
+ model="base-aemv8a" \
+ arch_version="8.4" \
+ gen_model_params
+}
+
+fetch_tf_resource() {
+ # Expect scripts
+ uart="0" file="tftf.exp" track_expect
+ uart="2" file="spm-uart2.exp" track_expect
+}
diff --git a/run_config/fvp-spm.linux b/run_config/fvp-spm.linux
new file mode 100644
index 0000000..29f7476
--- /dev/null
+++ b/run_config/fvp-spm.linux
@@ -0,0 +1,34 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ url="$project_filer/ci-files/spm-05-19-2020/hafnium.bin" fetch_file
+ url="$project_filer/ci-files/spm-05-19-2020/secure_hafnium.bin" fetch_file
+ url="$project_filer/ci-files/spm-05-19-2020/initrd.img" fetch_file
+ url="$project_filer/ci-files/spm-05-19-2020/manifest.dtb" fetch_file
+
+ archive_file "hafnium.bin"
+ archive_file "secure_hafnium.bin"
+ archive_file "initrd.img"
+ archive_file "manifest.dtb"
+
+ build_fip BL33="$archive/hafnium.bin" BL32="$archive/secure_hafnium.bin"
+}
+
+post_fetch_tf_resource() {
+ model="base-aemv8a" \
+ arch_version="8.4" \
+ initrd_bin="initrd.img" \
+ el3_payload_bin="manifest.dtb" \
+ gen_model_params
+}
+
+fetch_tf_resource() {
+ # Expect scripts
+ uart="0" file="spm-linux-uart0.exp" track_expect
+ uart="2" file="spm-uart2.exp" track_expect
+}
diff --git a/run_config/fvp-spm.optee b/run_config/fvp-spm.optee
new file mode 100644
index 0000000..e9df884
--- /dev/null
+++ b/run_config/fvp-spm.optee
@@ -0,0 +1,24 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ url="$project_filer/ci-files/spm-05-19-2020/tee-pager_v2.bin" fetch_file
+
+ archive_file "tee-pager_v2.bin"
+
+ build_fip BL33="$archive/tftf.bin" BL32="$archive/tee-pager_v2.bin"
+}
+
+post_fetch_tf_resource() {
+ model="base-aemv8a" \
+ gen_model_params
+}
+
+fetch_tf_resource() {
+ # Expect scripts
+ uart="0" file="tftf.exp" track_expect
+}
diff --git a/run_config/fvp-tc0 b/run_config/fvp-tc0
new file mode 100644
index 0000000..31be770
--- /dev/null
+++ b/run_config/fvp-tc0
@@ -0,0 +1,26 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+fetch_tf_resource() {
+ # Use SCP binary from SCP build if it exists, or fetch pre-built ones.
+ if [ ! -f "$archive/scp_romfw.bin" ]; then
+ url="$tc_prebuilts/scp_romfw.bin" fetch_file
+ archive_file "scp_romfw.bin"
+ fi
+
+ # Hold terminal_uart_aon
+ uart="2" file="hold_uart.exp" track_expect
+}
+
+post_fetch_tf_resource() {
+ # Needed by the Total Compute Fast Model
+ set_model_env "FASTSIM_CMN_INTERNAL_RNSAM" "1"
+ model="tc0" gen_model_params
+ set_run_env "ports_script" "$ci_root/model/tc0-ports.awk"
+ set_run_env "num_uarts" "3"
+ uart="1" set_expect_variable "num_cpus" "4"
+}
diff --git a/run_config/fvp-tftf.aarch32 b/run_config/fvp-tftf.aarch32
new file mode 100644
index 0000000..ec91d56
--- /dev/null
+++ b/run_config/fvp-tftf.aarch32
@@ -0,0 +1,11 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+fetch_tf_resource() {
+ uart="0" file="tftf-aarch32.exp" track_expect
+ uart="1" file="hold_uart.exp" track_expect
+}
diff --git a/run_config/fvp-tftf.aarch32+fwu b/run_config/fvp-tftf.aarch32+fwu
new file mode 100644
index 0000000..9d43a9c
--- /dev/null
+++ b/run_config/fvp-tftf.aarch32+fwu
@@ -0,0 +1,28 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+pre_tftf_build() {
+ # Build TFTF and FWU images for this config
+ targets="tftf ns_bl1u ns_bl2u" set_tftf_build_targets
+}
+
+
+# Perform FWU steps after all build products have been archived.
+post_tf_build() {
+ fip_targets="fip fwu_fip" build_fip \
+ BL33="$archive/tftf.bin" \
+ NS_BL2U="$archive/ns_bl2u.bin"
+}
+
+post_tf_archive() {
+ echo "Backing up FIP..."
+ cp "$archive/fip.bin" "$archive/backup_fip.bin"
+}
+
+fetch_tf_resource() {
+ uart="0" timeout="900" file="tftf-aarch32.exp" track_expect
+}
diff --git a/run_config/fvp-zeus b/run_config/fvp-zeus
new file mode 100644
index 0000000..122fdfd
--- /dev/null
+++ b/run_config/fvp-zeus
@@ -0,0 +1,13 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_fetch_tf_resource() {
+ model="zeus" \
+ cache_state_modelled="0" \
+ gen_model_params
+ uart="0" set_expect_variable "num_cpus" "4"
+}
diff --git a/run_config/juno-linux.optee b/run_config/juno-linux.optee
new file mode 100644
index 0000000..960b113
--- /dev/null
+++ b/run_config/juno-linux.optee
@@ -0,0 +1,18 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ get_scp_bl2_bin
+ get_uboot_bin
+ get_optee_bin
+ build_fip BL33="$archive/uboot.bin" BL32="$archive/bl32.bin" SCP_BL2="$archive/scp_bl2.bin"
+}
+
+post_fetch_tf_resource() {
+ gen_recovery_image "$archive/bl1.bin" "$archive/fip.bin"
+ payload_type="linux" gen_juno_yaml
+}
diff --git a/run_config/juno-linux.reboot b/run_config/juno-linux.reboot
new file mode 100644
index 0000000..a4f3ee6
--- /dev/null
+++ b/run_config/juno-linux.reboot
@@ -0,0 +1,17 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ get_scp_bl2_bin
+ get_uboot_bin
+ build_fip BL33="$archive/uboot.bin" SCP_BL2="$archive/scp_bl2.bin"
+}
+
+post_fetch_tf_resource() {
+ gen_recovery_image "$archive/bl1.bin" "$archive/fip.bin"
+ payload_type="linux_reboot" gen_juno_yaml
+}
diff --git a/run_config/juno-linux.reboot+aarch32 b/run_config/juno-linux.reboot+aarch32
new file mode 100644
index 0000000..e1452a7
--- /dev/null
+++ b/run_config/juno-linux.reboot+aarch32
@@ -0,0 +1,23 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ get_scp_bl2_bin
+ get_uboot32_bin
+
+ # Building FIP for this config requries a BL32 built in AArch32, but
+ # we'll only build that later. An appropriate BL32 image must be updated
+ # in the FIP before the recovery image is built
+ local tmp_bl32="$(mktempfile)"
+ build_fip BL32="$tmp_bl32" BL33="$archive/uboot.bin" SCP_BL2="$archive/scp_bl2.bin"
+}
+
+post_fetch_tf_resource() {
+ gen_recovery_image32_oe "$archive/bl1.bin" "$archive/fip.bin"
+ bootloader_prompt="juno32#" payload_type="linux_reboot" os="oe" nfs_rootfs="$juno32_rootfs_url" \
+ gen_juno_yaml
+}
diff --git a/run_config/juno-manual.linuxshutdown b/run_config/juno-manual.linuxshutdown
new file mode 100644
index 0000000..a2ba962
--- /dev/null
+++ b/run_config/juno-manual.linuxshutdown
@@ -0,0 +1,20 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ # Override the default URL since it points to OE and we need Busybox
+ url="$linaro_release/juno-latest-busybox-uboot/SOFTWARE/scp_bl2.bin" get_scp_bl2_bin
+ url="$linaro_release/juno-latest-busybox-uboot/SOFTWARE/bl33-uboot.bin" get_uboot_bin
+ build_fip BL33="$archive/uboot.bin" SCP_BL2="$archive/scp_bl2.bin"
+}
+
+post_fetch_tf_resource() {
+ # Override the default URL since it points to OE and we need Busybox
+ url="$linaro_release/juno-latest-busybox-uboot" gen_recovery_image "$archive/bl1.bin" "$archive/fip.bin"
+ # Linux manual shutdown test, 600 second timeout
+ juno_manual_test_run "linux-manual-shutdown" "600" "$archive/run.log"
+}
diff --git a/run_config/juno-manual.linuxshutdown+aarch32 b/run_config/juno-manual.linuxshutdown+aarch32
new file mode 100644
index 0000000..97877b3
--- /dev/null
+++ b/run_config/juno-manual.linuxshutdown+aarch32
@@ -0,0 +1,23 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ get_scp_bl2_bin
+ get_uboot32_bin
+
+ # Building FIP for this config requires a BL32 built in AArch32, but
+ # we'll only build that later. For now, provide a dummy file; we'll
+ # update the FIP with real BL32 image later.
+ local tmp_bl32="$(mktempfile)"
+ build_fip BL32="$tmp_bl32" BL33="$archive/uboot.bin" SCP_BL2="$archive/scp_bl2.bin"
+}
+
+post_fetch_tf_resource() {
+ gen_recovery_image32 "$archive/bl1.bin" "$archive/fip.bin"
+ # Linux manual shutdown test, 600 second timeout
+ juno_manual_test_run "linux-manual-shutdown" "600" "$archive/juno.log"
+}
diff --git a/run_config/juno-manual.tftf b/run_config/juno-manual.tftf
new file mode 100644
index 0000000..ba5845b
--- /dev/null
+++ b/run_config/juno-manual.tftf
@@ -0,0 +1,17 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ get_scp_bl2_bin
+ build_fip BL33="$archive/tftf.bin" SCP_BL2="$archive/scp_bl2.bin"
+}
+
+post_fetch_tf_resource() {
+ gen_recovery_image "$archive/bl1.bin" "$archive/fip.bin"
+ # TFTF generic test, 600 second timeout
+ juno_manual_test_run "tftf-manual-generic" "600" "$archive/run.log"
+}
diff --git a/run_config/juno-manual.tftf+aarch32 b/run_config/juno-manual.tftf+aarch32
new file mode 100644
index 0000000..2fab409
--- /dev/null
+++ b/run_config/juno-manual.tftf+aarch32
@@ -0,0 +1,22 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ get_scp_bl2_bin
+
+ # Building FIP for this config requires a BL32 built in AArch32, but
+ # we'll only build that later. For now, provide a dummy file; we'll
+ # update the FIP with real BL32 image later.
+ local tmp_bl32="$(mktempfile)"
+ build_fip BL32="$tmp_bl32" BL33="$archive/tftf.bin" SCP_BL2="$archive/scp_bl2.bin"
+}
+
+post_fetch_tf_resource() {
+ gen_recovery_image32 "$archive/bl1.bin" "$archive/fip.bin"
+ # TFTF generic test, 600 second timeout
+ juno_manual_test_run "tftf-manual-generic" "600" "$archive/juno.log"
+}
diff --git a/run_config/juno-r1 b/run_config/juno-r1
new file mode 100644
index 0000000..e3e29cf
--- /dev/null
+++ b/run_config/juno-r1
@@ -0,0 +1,11 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_archive() {
+ set_hook_var "juno_revision" "juno-r1"
+ echo "Choosing juno revision r1"
+}
diff --git a/run_config/juno-r2 b/run_config/juno-r2
new file mode 100644
index 0000000..79298b8
--- /dev/null
+++ b/run_config/juno-r2
@@ -0,0 +1,11 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_archive() {
+ set_hook_var "juno_revision" "juno-r2"
+ echo "Choosing juno revision r2"
+}
diff --git a/run_config/juno-rt32.instr b/run_config/juno-rt32.instr
new file mode 100644
index 0000000..6ebb193
--- /dev/null
+++ b/run_config/juno-rt32.instr
@@ -0,0 +1,11 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_archive() {
+ config_file="$ci_root/tf_config/juno-aarch32-rst-to-sp-min-enable-runtime-instr" \
+ juno_aarch32_runtime
+}
diff --git a/run_config/juno-scmi b/run_config/juno-scmi
new file mode 100644
index 0000000..b9187eb
--- /dev/null
+++ b/run_config/juno-scmi
@@ -0,0 +1,40 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+test_setup() {
+ # Only need to run on debug
+ echo "Building only in DEBUG mode."
+ set_hook_var "bin_mode" "debug"
+}
+
+pre_tf_build() {
+ build_scmi_lib_scp_tools
+}
+
+post_tf_archive() {
+ build_tf_for_scp_tools
+
+ build_fip_for_scp_tools
+}
+
+post_fetch_tf_resource() {
+ echo "archive.. $archive"
+
+ cp "$archive/scp_rom_bypass.bin" "$archive/scp_bl1.bin"
+
+ gen_recovery_image \
+ "$archive/bl1.bin" \
+ "$archive/bl2.bin" \
+ "$archive/bl31.bin" \
+ "$archive/fip.bin" \
+ "$archive/scp_bl1.bin"
+
+ payload_type="scp_tests_scmi" gen_juno_yaml
+}
+
+post_package() {
+ use_debug_bins
+}
diff --git a/run_config/juno-tftf+aarch32.reboot b/run_config/juno-tftf+aarch32.reboot
new file mode 100644
index 0000000..b1a01e7
--- /dev/null
+++ b/run_config/juno-tftf+aarch32.reboot
@@ -0,0 +1,21 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ get_psci_reset2_scp_bl2_bin
+
+ # Building FIP for this config requires a BL32 built in AArch32, but
+ # we'll only build that later. For now, provide a dummy file; we'll
+ # update the FIP with real BL32 image later.
+ local tmp_bl32="$(mktempfile)"
+ build_fip BL32="$tmp_bl32" BL33="$archive/tftf.bin" SCP_BL2="$archive/scp_bl2.bin"
+}
+
+post_fetch_tf_resource() {
+ gen_recovery_image32 "$archive/bl1.bin" "$archive/fip.bin"
+ payload_type="tftf" gen_juno_yaml
+}
diff --git a/run_config/juno-tftf.fwu b/run_config/juno-tftf.fwu
index dc9bccc..f1de31a 100644
--- a/run_config/juno-tftf.fwu
+++ b/run_config/juno-tftf.fwu
@@ -32,3 +32,7 @@
"$archive/fwu_fip.bin" \
"$archive/ns_bl1u.bin"
}
+
+post_fetch_tf_resource() {
+ payload_type="tftf" gen_juno_yaml
+}
diff --git a/run_config/juno-tftf.reboot b/run_config/juno-tftf.reboot
new file mode 100644
index 0000000..0c5e758
--- /dev/null
+++ b/run_config/juno-tftf.reboot
@@ -0,0 +1,16 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ get_psci_reset2_scp_bl2_bin
+ build_fip BL33="$archive/tftf.bin" SCP_BL2="$archive/scp_bl2.bin"
+}
+
+post_fetch_tf_resource() {
+ gen_recovery_image "$archive/bl1.bin" "$archive/fip.bin"
+ payload_type="tftf" gen_juno_yaml
+}
diff --git a/run_config/norun b/run_config/norun
new file mode 100644
index 0000000..290130c
--- /dev/null
+++ b/run_config/norun
@@ -0,0 +1,6 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/run_config/scan_build-tf b/run_config/scan_build-tf
new file mode 100644
index 0000000..6136b35
--- /dev/null
+++ b/run_config/scan_build-tf
@@ -0,0 +1,21 @@
+#!/bin/bash
+#
+# Copyright (c) 2019, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+test_setup() {
+ # Coverity scan only need to run on debug builds
+ echo "Building only in DEBUG mode."
+ set_hook_var "bin_mode" "debug"
+}
+
+pre_tf_build() {
+ wrapper="scan_build" setup_tf_build_wrapper
+}
+
+post_tf_archive() {
+ # Save scan-build reports to artefacts directory for offline analysis.
+ find $workspace -name scan-build-reports -exec cp -rf {} $archive \; &> /dev/null
+}
diff --git a/run_config/scp_juno-linux.uboot b/run_config/scp_juno-linux.uboot
new file mode 100644
index 0000000..939a482
--- /dev/null
+++ b/run_config/scp_juno-linux.uboot
@@ -0,0 +1,26 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+test_setup() {
+ echo "Building only in RELEASE mode."
+ set_hook_var "bin_mode" "release"
+}
+
+post_tf_build() {
+ path_bypass_rom="$scp_root/build/product/juno/scp_romfw_bypass/$mode/bin"
+
+ cp "$path_bypass_rom/scp_romfw_bypass.bin" "$path_bypass_rom/scp_bl1.bin"
+ archive_file "$path_bypass_rom/scp_bl1.bin"
+
+ archive_file "$scp_root/build/product/juno/scp_ramfw/$mode/bin/scp_ramfw.bin"
+ get_uboot_bin
+ build_fip BL33="$archive/uboot.bin" SCP_BL2="$archive/scp_ramfw.bin"
+}
+
+post_fetch_tf_resource() {
+ gen_recovery_image "$archive/bl1.bin" "$archive/fip.bin" "$archive/scp_bl1.bin"
+ payload_type="linux" gen_juno_yaml
+}
diff --git a/run_config/scp_juno-tftf b/run_config/scp_juno-tftf
new file mode 100644
index 0000000..58e5b25
--- /dev/null
+++ b/run_config/scp_juno-tftf
@@ -0,0 +1,22 @@
+#!/bin/bash
+#
+# Copyright (c) 2020, Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+post_tf_build() {
+ path_bypass_rom="$scp_root/build/product/juno/scp_romfw_bypass/$mode/bin"
+
+ cp "$path_bypass_rom/scp_romfw_bypass.bin" "$path_bypass_rom/scp_bl1.bin"
+ archive_file "$path_bypass_rom/scp_bl1.bin"
+
+ archive_file "$scp_root/build/product/juno/scp_ramfw/$mode/bin/scp_ramfw.bin"
+
+ build_fip BL33="$archive/tftf.bin" SCP_BL2="$archive/scp_ramfw.bin"
+}
+
+post_fetch_tf_resource() {
+ gen_recovery_image "$archive/bl1.bin" "$archive/fip.bin" "$archive/scp_bl1.bin"
+ payload_type="tftf" gen_juno_yaml
+}