ci: build all errata
Add TF build config and Coverity option to build all available CPUs
with all errata on the FVP platform.
Change-Id: Ibf87726e597f10b7c00b2217ac258cd1dde764ee
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
(cherry picked from commit dff55c91e9ad69348f0403b4fda64758ff81cd87)
diff --git a/group/tf-l1-build-fvp/fvp-errata-all:nil b/group/tf-l1-build-fvp/fvp-errata-all:nil
new file mode 100644
index 0000000..8e42dc9
--- /dev/null
+++ b/group/tf-l1-build-fvp/fvp-errata-all:nil
@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2025 Arm Limited. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
diff --git a/script/tf-coverity/tf-cov-make b/script/tf-coverity/tf-cov-make
index 462e15e..df81d8d 100755
--- a/script/tf-coverity/tf-cov-make
+++ b/script/tf-coverity/tf-cov-make
@@ -1,6 +1,6 @@
#!/usr/bin/env bash
#
-# Copyright (c) 2019-2023, Arm Limited. All rights reserved.
+# Copyright (c) 2019-2025, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -242,6 +242,10 @@
# OPTEE_ALLOW_SMC_LOAD feature
clean_build $fvp_common_flags ${ARM_TBB_OPTIONS} SPD=opteed OPTEE_ALLOW_SMC_LOAD=1 PLAT_XLAT_TABLES_DYNAMIC=1 FVP_TRUSTED_SRAM_SIZE=384
+# Build all CPU's with all errata's with FVP platform.
+clean_build $fvp_common_flags CTX_INCLUDE_AARCH32_REGS=0 HW_ASSISTED_COHERENCY=1 \
+ USE_COHERENT_MEM=0 ENABLE_ERRATA_ALL=1 FVP_TRUSTED_SRAM_SIZE=384
+
#
# Juno platform
# We'll use the following flags for all Juno builds.
diff --git a/tf_config/fvp-errata-all b/tf_config/fvp-errata-all
new file mode 100644
index 0000000..fcfea37
--- /dev/null
+++ b/tf_config/fvp-errata-all
@@ -0,0 +1,7 @@
+CROSS_COMPILE=aarch64-none-elf-
+CTX_INCLUDE_AARCH32_REGS=0
+ENABLE_ERRATA_ALL=1
+FVP_TRUSTED_SRAM_SIZE=384
+HW_ASSISTED_COHERENCY=1
+PLAT=fvp
+USE_COHERENT_MEM=0