RSE: Add test run on TC2 FVP
Signed-off-by: Jamie Fox <jamie.fox@arm.com>
Change-Id: Ia5861f5d5a1735e1a559fc31fd0b5ae10e8ad41d
diff --git a/build_helper/build_helper_configs.py b/build_helper/build_helper_configs.py
index 1d2f576..3f671bf 100755
--- a/build_helper/build_helper_configs.py
+++ b/build_helper/build_helper_configs.py
@@ -139,6 +139,21 @@
"-o %(ci_build_root_dir)s/"
"spe/bin/tfm.hex -Intel;"
"fi;"),
+ "arm/rse/tc": ("srec_cat "
+ "%(ci_build_root_dir)s/spe/bin/bl1_1.bin -Binary -offset 0x0 "
+ "%(ci_build_root_dir)s/spe/bin/rom_dma_ics.bin -Binary -offset 0x1F000 "
+ "-o %(ci_build_root_dir)s/spe/bin/rom.bin -Binary;"
+ "curl --fail --no-progress-meter --connect-timeout 10 --retry 6 -LS -o fiptool https://downloads.trustedfirmware.org/tf-m/rse/tc/fiptool;"
+ "chmod 755 fiptool;"
+ "curl --fail --no-progress-meter --connect-timeout 10 --retry 6 -LS -o fip.bin https://downloads.trustedfirmware.org/tf-m/rse/tc/fip.bin;"
+ "./fiptool update "
+ "--align 8192 --rss-bl2 %(ci_build_root_dir)s/spe/bin/bl2_signed.bin "
+ "--align 8192 --rss-s %(ci_build_root_dir)s/spe/bin/tfm_s_encrypted.bin "
+ "--align 8192 --rss-ns %(ci_build_root_dir)s/nspe/bin/tfm_ns_encrypted.bin "
+ "--align 8192 --rss-sic-tables-s %(ci_build_root_dir)s/spe/bin/tfm_s_sic_tables_signed.bin "
+ "--align 8192 --rss-sic-tables-ns %(ci_build_root_dir)s/nspe/bin/tfm_ns_sic_tables_signed.bin "
+ "--out %(ci_build_root_dir)s/spe/bin/host_flash.bin "
+ "fip.bin"),
"stm/stm32l562e_dk": ("echo 'STM32L562E-DK board post process';"
"%(ci_build_root_dir)s/spe/api_ns/postbuild.sh;"
"pushd %(ci_build_root_dir)s/spe/api_ns;"
@@ -233,7 +248,12 @@
"%(ci_build_root_dir)s/spe/bin/"
"bl2.bin",
"%(ci_build_root_dir)s/spe/bin/"
- "tfm_sign.bin"]
+ "tfm_sign.bin"],
+ "arm/rse/tc": [
+ "%(ci_build_root_dir)s/spe/bin/rom.bin",
+ "%(ci_build_root_dir)s/spe/bin/encrypted_cm_provisioning_bundle_0.bin",
+ "%(ci_build_root_dir)s/spe/bin/encrypted_dm_provisioning_bundle_0.bin",
+ "%(ci_build_root_dir)s/spe/bin/host_flash.bin"]
}
}
@@ -350,12 +370,12 @@
# MUSCA_S1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_CC_DRIVER_PSA
("arm/musca_s1", "GCC_10_3", "1",
"RegBL2, RegS, RegNS", "OFF", "Release", True, "", "CC_DRIVER_PSA"),
- # RSE_TC_GCC_2_Release_BL2_PSOFF
+ # RSE_TC_GCC_2_RegS_RegNS_Release_BL2
("arm/rse/tc", "GCC_10_3", "2",
- "RegS, RegNS", "OFF", "Release", True, "", "PSOFF"),
- # RSE_RDFremont_GCC_2_Release_BL2_NSOFF_PSOFF_CFG0
+ "RegS, RegNS", "OFF", "Release", True, "", ""),
+ # RSE_RDFremont_GCC_2_Release_BL2_NSOFF_CFG0
("arm/rse/rdfremont", "GCC_10_3", "2",
- "OFF", "OFF", "Release", True, "", "NSOFF, PSOFF, CFG0"),
+ "OFF", "OFF", "Release", True, "", "NSOFF, CFG0"),
# stm32l562e_dk_ARMCLANG_1_RegS_RegNS_Release_BL2_CRYPTO_OFF
("stm/stm32l562e_dk", "ARMCLANG_6_21", "1",
"RegS, RegNS", "OFF", "Release", True, "", "CRYPTO_OFF"),
@@ -896,12 +916,12 @@
"tfm_platform": ["arm/rse/tc"],
"compiler": ["GCC_10_3"],
"isolation_level": ["1", "2"],
- "test_regression": ["OFF", "RegBL2, RegS, RegNS"],
+ "test_regression": ["OFF", "RegS, RegNS"],
"test_psa_api": ["OFF"],
"cmake_build_type": ["Debug", "Release"],
"with_bl2": [True],
"profile": [""],
- "extra_params": ["PSOFF"]
+ "extra_params": [""]
},
"common_params": _common_tfm_builder_cfg,
"invalid": _common_tfm_invalid_configs + [
@@ -920,7 +940,7 @@
"cmake_build_type": ["Debug", "Release"],
"with_bl2": [True],
"profile": [""],
- "extra_params": ["NSOFF, PSOFF, CFG0"]
+ "extra_params": ["NSOFF, CFG0"]
},
"common_params": _common_tfm_builder_cfg,
"invalid": _common_tfm_invalid_configs + []
diff --git a/lava_helper/jinja2_templates/fvp_rse_tc.jinja2 b/lava_helper/jinja2_templates/fvp_rse_tc.jinja2
new file mode 100644
index 0000000..1474549
--- /dev/null
+++ b/lava_helper/jinja2_templates/fvp_rse_tc.jinja2
@@ -0,0 +1,80 @@
+{#------------------------------------------------------------------------------
+# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-----------------------------------------------------------------------------#}
+{% extends 'jinja2_templates/base.jinja2' %}
+{% block metadata %}
+{{ super() }}
+{% endblock %}
+{% block base %}
+{{ super() }}
+{% endblock %}
+{% block actions %}
+context:
+ kernel_start_message: ''
+
+actions:
+- deploy:
+ namespace: docker
+ to: fvp
+ images:
+ rom:
+ url: {{ rom_url }}
+ cm_provisioning_bundle:
+ url: {{ cm_provisioning_bundle_url }}
+ dm_provisioning_bundle:
+ url: {{ dm_provisioning_bundle_url }}
+ flash:
+ url: {{ flash_url }}
+- boot:
+ failure_retry: 3
+ namespace: docker
+ method: fvp
+ docker:
+ name: {{ docker_prefix }}/fvp:fvp_tc2_0.0_8260_linux64
+ local: true
+ prompts:
+ - 'root@lava '
+ image: /opt/model/FVP_TC2/models/Linux64_GCC-9.3/FVP_TC2
+ timeout:
+ minutes: 10
+ console_string: 'terminal_s1: Listening for serial connection on port (?P<PORT>\d+)'
+ license_variable: '{{ license_variable }}'
+ use_telnet: True
+ arguments:
+ - "-M 1"
+ - "--simlimit 900"
+ - "-C css.rss.rom.raw_image={ROM}"
+ - "--data css.rss.sram0={CM_PROVISIONING_BUNDLE}@0x400"
+ - "--data css.rss.sram1={DM_PROVISIONING_BUNDLE}@0x0"
+ - "-C board.flashloader0.fname={FLASH}"
+ - "-C displayController=2"
+ - "-C css.rss.sic.SIC_AUTH_ENABLE=1"
+ - "-C css.rss.sic.SIC_DECRYPT_ENABLE=1"
+ - "-C css.rss.VMADDRWIDTH=16"
+ - "-C css.rss.intchecker.ICBC_RESET_VALUE=0x0000011B"
+ - "-C soc.pl011_uart1.shutdown_on_eot=1"
+ - "-C disable_visualisation=1"
+
+ prompts:
+ - '(.*)'
+
+- test:
+ namespace: target
+ monitors:
+ {%- for monitor in monitors %}
+ - name: "{{monitor.name}}"
+ start: "{{monitor.start}}"
+ end: "{{monitor.end}}"
+ pattern: "{{monitor.pattern}}"
+ fixupdict:
+ '{{monitor.fixup.pass}}': pass
+ '{{monitor.fixup.fail}}': fail
+ {%- if monitor.fixup.skip %}
+ '{{monitor.fixup.skip}}': skip
+ {%- endif %}
+ {%- endfor %}
+
+{% endblock %}
diff --git a/lava_helper/lava_helper_configs.py b/lava_helper/lava_helper_configs.py
index ef8f1f9..7482a0a 100644
--- a/lava_helper/lava_helper_configs.py
+++ b/lava_helper/lava_helper_configs.py
@@ -8,7 +8,7 @@
__copyright__ = """
/*
- * Copyright (c) 2018-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -206,6 +206,27 @@
}
}
+# RSE on TC FVP
+fvp_rse_tc = {
+ "templ": "fvp_rse_tc.jinja2",
+ "job_name": "fvp_rse_tc",
+ "device_type": "fvp",
+ "job_timeout": 15,
+ "action_timeout": 10,
+ "monitor_timeout": 15,
+ "poweroff_timeout": 1,
+ "platforms": {"arm/rse/tc": ""},
+ "binaries": {
+ "rom": "spe/bin/rom.bin",
+ "cm_provisioning_bundle": "spe/bin/encrypted_cm_provisioning_bundle_0.bin",
+ "dm_provisioning_bundle": "spe/bin/encrypted_dm_provisioning_bundle_0.bin",
+ "flash": "spe/bin/host_flash.bin"
+ },
+ "monitors": {
+ 'no_reg_tests': no_reg_tests_monitors,
+ 'reg_tests': reg_tests_monitors,
+ }
+}
# QEMU for AN521 with BL2 bootloader
qemu_mps2_bl2 = {
@@ -349,6 +370,7 @@
"fvp_mps2_an521_bl2": fvp_mps2_an521_bl2,
"fvp_mps2_an519_bl2": fvp_mps2_an519_bl2,
"fvp_corstone1000": fvp_corstone1000,
+ "fvp_rse_tc": fvp_rse_tc,
"qemu_mps2_bl2": qemu_mps2_bl2,
"musca_b1": musca_b1_bl2,
"stm32l562e_dk": stm32l562e_dk,