Submit LAVA Test for OTP Enabled Config
LAVA test will be submitted in nightly and release jobs
for a specified config with OTP enabled.
Signed-off-by: Xinyu Zhang <xinyu.zhang@arm.com>
Change-Id: Id9e353c1ab3f85e93cd2730df6e5a60d89b7a192
diff --git a/lava_helper/lava_helper_configs.py b/lava_helper/lava_helper_configs.py
index 1373c21..c77ab37 100644
--- a/lava_helper/lava_helper_configs.py
+++ b/lava_helper/lava_helper_configs.py
@@ -8,7 +8,7 @@
__copyright__ = """
/*
- * Copyright (c) 2018-2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
@@ -2820,6 +2820,78 @@
},
}
+# Musca-B1 with BL2 bootloader and OTP enabled
+# unified hex file comprising of both bl2.bin and tfm_s_ns_signed.bin
+# srec_cat bin/bl2.bin -Binary -offset 0xA000000 bin/tfm_s_ns_signed.bin -Binary -offset 0xA020000 -o tfm.hex -Intel
+musca_b1_otp_bl2 = {
+ "templ": "musca_b1_otp.jinja2",
+ "job_name": "musca_b1_opt_bl2",
+ "device_type": "musca-b",
+ "job_timeout": 24,
+ "action_timeout": 12,
+ "monitor_timeout": 10,
+ "poweroff_timeout": 40,
+ "platforms": {"MUSCA_B1_OTP": ""},
+ "compilers": ["ARMCLANG"],
+ "build_types": ["Debug"],
+ "boot_types": ["BL2"],
+ "tests": {
+ "RegressionIPCTfmLevel3": {
+ "binaries": {
+ "firmware": "tfm.hex",
+ },
+ "monitors": [
+ {
+ 'name': 'Secure_Test_Suites_Summary',
+ 'start': 'Secure test suites summary',
+ 'end': 'End of Secure test suites',
+ 'pattern': r"Test suite '(?P<"
+ r"test_case_id>[^\n]+)' has (.*) "
+ r"(?P<result>PASSED|FAILED)",
+ 'fixup': {"pass": "PASSED", "fail": "FAILED"},
+ 'required': [
+ ("psa_protected_storage_"
+ "s_interface_tests_tfm_sst_test_2xxx_"),
+ "sst_reliability_tests_tfm_sst_test_3xxx_",
+ "sst_rollback_protection_tests_tfm_sst_test_4xxx_",
+ ("psa_internal_trusted_storage_"
+ "s_interface_tests_tfm_its_test_2xxx_"),
+ "its_reliability_tests_tfm_its_test_3xxx_",
+ ("audit_"
+ "logging_secure_interface_test_tfm_audit_test_1xxx_"),
+ "crypto_secure_interface_tests_tfm_crypto_test_5xxx_",
+ ("initial_attestation_service_"
+ "secure_interface_tests_tfm_attest_test_1xxx_"),
+ ]
+ },
+ {
+ 'name': 'Non_Secure_Test_Suites_Summary',
+ 'start': 'Non-secure test suites summary',
+ 'end': r'End of Non-secure test suites',
+ 'pattern': r"Test suite '(?P<"
+ r"test_case_id>[^\n]+)' has (.*) "
+ r"(?P<result>PASSED|FAILED)",
+ 'fixup': {"pass": "PASSED", "fail": "FAILED"},
+ 'required': [
+ ("psa_protected_storage"
+ "_ns_interface_tests_tfm_sst_test_1xxx_"),
+ ("psa_internal_trusted_storage"
+ "_ns_interface_tests_tfm_its_test_1xxx_"),
+ ("auditlog_"
+ "non_secure_interface_test_tfm_audit_test_1xxx_"),
+ ("crypto_"
+ "non_secure_interface_test_tfm_crypto_test_6xxx_"),
+ ("initial_attestation_service_"
+ "non_secure_interface_tests_tfm_attest_test_2xxx_"),
+ "core_non_secure_positive_tests_tfm_core_test_1xxx_"
+ ]
+ }
+ ] # Monitors
+ },
+ },
+}
+
+
# All configurations should be mapped here
lava_gen_config_map = {
"mps2_an521_bl2": tfm_mps2_sse_200,
@@ -2829,6 +2901,7 @@
"fvp_mps2_an519_nobl2": fvp_mps2_an519_nobl2,
"qemu_mps2_bl2": qemu_mps2_bl2,
"musca_b1": musca_b1_bl2,
+ "musca_b1_otp": musca_b1_otp_bl2,
}
lavagen_config_sort_order = [