RSE: TC: Rename TC->TC2
RSE TC platform support has been modified to create a common TC
directory and move the TC2 specific code into its own directory. This
change clarifies the TC platform in the CI by renaming it to TC2 and
also updates the platform path in the TF-M directory.
Change-Id: I72dc65c7b89e121c9ac37c340b983cc44e39942a
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>
diff --git a/build_helper/build_helper_config_maps.py b/build_helper/build_helper_config_maps.py
index 74c44b8..6a3aab9 100644
--- a/build_helper/build_helper_config_maps.py
+++ b/build_helper/build_helper_config_maps.py
@@ -25,7 +25,7 @@
"arm/corstone1000" : "corstone1000",
"arm/mps4/corstone315" : "corstone315",
"arm/mps3/corstone310/fvp" : "corstone310",
- "arm/rse/tc" : "RSE_TC",
+ "arm/rse/tc/tc2" : "RSE_TC2",
"arm/rse/rdfremont" : "RSE_RDFremont",
"arm/rse/automotive_rd/rd1ae" : "RSE_RD1AE",
"cypress/psoc64" : "psoc64",
diff --git a/build_helper/build_helper_configs.py b/build_helper/build_helper_configs.py
index f501ac7..01f482d 100755
--- a/build_helper/build_helper_configs.py
+++ b/build_helper/build_helper_configs.py
@@ -115,7 +115,7 @@
"-o %(ci_build_root_dir)s/"
"spe/bin/tfm.hex -Intel; "
"fi;"),
- "arm/rse/tc": ("srec_cat "
+ "arm/rse/tc/tc2": ("srec_cat "
"%(ci_build_root_dir)s/spe/bin/bl1_1.bin -Binary -offset 0x0 "
"%(ci_build_root_dir)s/spe/bin/rom_dma_ics.bin -Binary -offset 0x1F000 "
"-o %(ci_build_root_dir)s/spe/bin/rom.bin -Binary;"
@@ -225,7 +225,7 @@
"bl2.bin",
"%(ci_build_root_dir)s/spe/bin/"
"tfm_sign.bin"],
- "arm/rse/tc": [
+ "arm/rse/tc/tc2": [
"%(ci_build_root_dir)s/spe/bin/rom.bin",
"%(ci_build_root_dir)s/spe/bin/encrypted_cm_provisioning_bundle_0.bin",
"%(ci_build_root_dir)s/spe/bin/encrypted_dm_provisioning_bundle_0.bin",
@@ -346,8 +346,8 @@
# MUSCA_S1_GCC_1_RegBL2_RegS_RegNS_Release_BL2_CC_DRIVER_PSA
("arm/musca_s1", "GCC_10_3", "1",
"RegBL2, RegS, RegNS", "OFF", "Release", True, "", "CC_DRIVER_PSA"),
- # RSE_TC_GCC_2_RegS_RegNS_Debug_BL2
- ("arm/rse/tc", "GCC_10_3", "2",
+ # RSE_TC2_GCC_2_RegS_RegNS_Debug_BL2
+ ("arm/rse/tc/tc2", "GCC_10_3", "2",
"RegS, RegNS", "OFF", "Debug", True, "", ""),
# RSE_RDFremont_GCC_2_Release_BL2_NSOFF_CFG0
("arm/rse/rdfremont", "GCC_10_3", "2",
@@ -892,7 +892,7 @@
}
config_rse = {"seed_params": {
- "tfm_platform": ["arm/rse/tc"],
+ "tfm_platform": ["arm/rse/tc/tc2"],
"compiler": ["GCC_10_3"],
"isolation_level": ["1", "2"],
"test_regression": ["OFF", "RegS, RegNS"],
@@ -905,7 +905,7 @@
"common_params": _common_tfm_builder_cfg,
"invalid": _common_tfm_invalid_configs + [
# BL2 is too large for RSE in Debug builds with tests
- ("arm/rse/tc", "GCC_10_3", "*", "RegBL2, RegS, RegNS", "*",
+ ("arm/rse/tc/tc2", "GCC_10_3", "*", "RegBL2, RegS, RegNS", "*",
"Debug", True, "*", "*"),
]
}
diff --git a/lava_helper/jinja2_templates/fvp_rse_tc.jinja2 b/lava_helper/jinja2_templates/fvp_rse_tc2.jinja2
similarity index 100%
rename from lava_helper/jinja2_templates/fvp_rse_tc.jinja2
rename to lava_helper/jinja2_templates/fvp_rse_tc2.jinja2
diff --git a/lava_helper/lava_helper_configs.py b/lava_helper/lava_helper_configs.py
index d10e788..31311a4 100644
--- a/lava_helper/lava_helper_configs.py
+++ b/lava_helper/lava_helper_configs.py
@@ -266,16 +266,16 @@
}
}
-# RSE on TC FVP
-fvp_rse_tc = {
- "templ": "fvp_rse_tc.jinja2",
- "job_name": "fvp_rse_tc",
+# RSE on TC2 FVP
+fvp_rse_tc2 = {
+ "templ": "fvp_rse_tc2.jinja2",
+ "job_name": "fvp_rse_tc2",
"device_type": "fvp",
"job_timeout": 15,
"action_timeout": 10,
"monitor_timeout": 15,
"poweroff_timeout": 1,
- "platforms": {"arm/rse/tc": ""},
+ "platforms": {"arm/rse/tc/tc2": ""},
"binaries": {
"rom": {
"data": "spe/bin/rom.bin"
@@ -459,7 +459,7 @@
"fvp_mps2_an519_bl2": fvp_mps2_an519_bl2,
"fvp_mps4_cs315_bl1_bl2": fvp_mps4_cs315_bl1_bl2,
"fvp_corstone1000": fvp_corstone1000,
- "fvp_rse_tc": fvp_rse_tc,
+ "fvp_rse_tc2": fvp_rse_tc2,
"qemu_mps2_bl2": qemu_mps2_bl2,
"musca_b1": musca_b1_bl2,
"stm32l562e_dk": stm32l562e_dk,