Prepare for 0.1.0 release
Prepare for 0.1.0 release by adding documentation, updating
dependencies, and updating Cargo.toml.
Change-Id: I0e9a61629d00985a79a663b707d3a5306e5ed0fe
Signed-off-by: Imre Kis <imre.kis@arm.com>
diff --git a/src/lib.rs b/src/lib.rs
index 0126c94..b328a86 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -1,17 +1,15 @@
// SPDX-FileCopyrightText: Copyright 2023-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
// SPDX-License-Identifier: MIT OR Apache-2.0
-//! Arm Watchdog Module (SP805) driver
-//!
-//! Driver implementation for the [SP805 watchdog module](https://developer.arm.com/documentation/ddi0270/latest/).
-
#![no_std]
+#![doc = include_str!("../README.md")]
+#![deny(clippy::undocumented_unsafe_blocks)]
use bitflags::bitflags;
+pub use safe_mmio::UniqueMmioPointer;
use safe_mmio::{
field,
fields::{ReadPure, ReadPureWrite, WriteOnly},
- UniqueMmioPointer,
};
use zerocopy::{FromBytes, Immutable, IntoBytes, KnownLayout};
@@ -41,7 +39,7 @@
}
}
-/// SP805 register map.
+/// SP805 Watchdog register map.
#[derive(Clone, Eq, FromBytes, Immutable, IntoBytes, KnownLayout, PartialEq)]
#[repr(C, align(4))]
pub struct SP805Registers {
@@ -109,16 +107,13 @@
self.with_unlock(|mut regs| {
field!(regs, wdog_load).write(load_value);
field!(regs, wdog_intclr).write(1);
- field!(regs, wdog_control)
- .write(ControlRegister::INTEN | ControlRegister::RESEN);
+ field!(regs, wdog_control).write(ControlRegister::INTEN | ControlRegister::RESEN);
});
}
/// Disable watchdog
pub fn disable(&mut self) {
- self.with_unlock(|mut regs| {
- field!(regs, wdog_control).write(ControlRegister::empty())
- });
+ self.with_unlock(|mut regs| field!(regs, wdog_control).write(ControlRegister::empty()));
}
/// Update watchdog
@@ -143,7 +138,7 @@
use super::*;
use zerocopy::transmute_mut;
- const LOAD_VALUE : u32 = 0xabcd_ef01;
+ const LOAD_VALUE: u32 = 0xabcd_ef01;
#[repr(align(4096))]
pub struct FakeSp805Registers {
@@ -183,7 +178,7 @@
#[test]
fn enable() {
- let mut regs = FakeSp805Registers::new();
+ let mut regs = FakeSp805Registers::new();
{
// Enable
@@ -219,4 +214,4 @@
assert_eq!(LOAD_VALUE, regs.reg_read(0x00));
}
-}
\ No newline at end of file
+}