Add support for EL2 and EL3 translation regimes
* Assign translation regime to Xlat instance on creating
* Mark activate function as unsafe
* Remove half-baked TLB invalidation for TTBR1_EL1. The correct TLB
invalidation method for all translation regimes is implemented in the
next commit.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: Idacc85abf3df6bf7f0c6ad263d3890e1ad5dfab4
diff --git a/src/kernel_space.rs b/src/kernel_space.rs
index 1069c1c..d0be315 100644
--- a/src/kernel_space.rs
+++ b/src/kernel_space.rs
@@ -11,11 +11,9 @@
use super::{
address::{PhysicalAddress, VirtualAddress, VirtualAddressRange},
page_pool::{Page, PagePool},
- MemoryAccessRights, Xlat, XlatError,
+ MemoryAccessRights, RegimeVaRange, TranslationRegime, Xlat, XlatError,
};
-static mut KERNEL_SPACE_INSTANCE: Option<KernelSpace> = None;
-
#[derive(Clone)]
pub struct KernelSpace {
xlat: Arc<Mutex<Xlat>>,
@@ -37,9 +35,11 @@
/// * page_pool: Page pool for allocation kernel translation tables
pub fn new(page_pool: PagePool) -> Self {
Self {
- xlat: Arc::new(Mutex::new(Xlat::new(page_pool, unsafe {
- VirtualAddressRange::from_range(0x0000_0000..0x10_0000_0000)
- }))),
+ xlat: Arc::new(Mutex::new(Xlat::new(
+ page_pool,
+ unsafe { VirtualAddressRange::from_range(0x0000_0000..0x10_0000_0000) },
+ TranslationRegime::EL1_0(RegimeVaRange::Upper, 0),
+ ))),
}
}
@@ -115,8 +115,13 @@
}
/// Activate kernel address space mapping
- pub fn activate(&self) {
- self.xlat.lock().activate(0, super::TTBR::TTBR1_EL1);
+ ///
+ /// # Safety
+ /// This changes the mapping of the running execution context. The caller
+ /// must ensure that existing references will be mapped to the same address
+ /// after activation.
+ pub unsafe fn activate(&self) {
+ self.xlat.lock().activate();
}
/// Rounds a value down to a kernel space page boundary