Merge changes I368088ec,Ia246235a into lts-v2.8
* changes:
fix(spmd): avoid restoring ctx during first entry into spmc
feat(spmd): initialize SCR_EL3.EEL2 bit at RESET
diff --git a/.gitignore b/.gitignore
index 1f4efb6..cdb6441 100644
--- a/.gitignore
+++ b/.gitignore
@@ -11,6 +11,7 @@
# Ignore build products from tools
tools/**/*.o
+tools/**/*.d
tools/renesas/rcar_layout_create/*.bin
tools/renesas/rcar_layout_create/*.srec
tools/renesas/rcar_layout_create/*.map
diff --git a/Makefile b/Makefile
index 353513e..ec3d69f 100644
--- a/Makefile
+++ b/Makefile
@@ -9,7 +9,7 @@
#
VERSION_MAJOR := 2
VERSION_MINOR := 8
-VERSION_PATCH := 16
+VERSION_PATCH := 18
VERSION := ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH}
# Default goal is build all images
diff --git a/bl31/ehf.c b/bl31/ehf.c
index b328380..4ea5db9 100644
--- a/bl31/ehf.c
+++ b/bl31/ehf.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -203,10 +203,20 @@
* one stashed earlier if there are no more to deactivate.
*/
cur_pri_idx = get_pe_highest_active_idx(pe_data);
- if (cur_pri_idx == EHF_INVALID_IDX)
+
+#if GIC600_ERRATA_WA_2384374
+ if (cur_pri_idx == EHF_INVALID_IDX) {
+ old_mask = plat_ic_deactivate_priority(pe_data->init_pri_mask);
+ } else {
+ old_mask = plat_ic_deactivate_priority(priority);
+ }
+#else
+ if (cur_pri_idx == EHF_INVALID_IDX) {
old_mask = plat_ic_set_priority_mask(pe_data->init_pri_mask);
- else
+ } else {
old_mask = plat_ic_set_priority_mask(priority);
+ }
+#endif
if (old_mask > priority) {
ERROR("Deactivation priority (0x%x) lower than Priority Mask (0x%x)\n",
diff --git a/docs/change-log.md b/docs/change-log.md
index 136ab75..195942c 100644
--- a/docs/change-log.md
+++ b/docs/change-log.md
@@ -3,6 +3,66 @@
This document contains a summary of the new features, changes, fixes and known
issues in each release of Trusted Firmware-A.
+## [lts-2.8.18](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/lts-v2.8.17..refs/tags/lts-v2.8.18) (2024-04-26)
+
+### New Features
+
+- **Drivers**
+
+ - **Authentication**
+
+ - **mbedTLS**
+
+ - upgrade to version v2.28.8 ([a1cb5f6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a1cb5f656e5e19741e840e452aa51f71fe24efbb))
+
+## [lts-2.8.17](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/lts-v2.8.16..refs/tags/lts-v2.8.17) (2024-04-12)
+
+### Code Refactoring
+
+- **Services**
+
+ - **ERRATA ABI**
+
+ - optimize errata ABI using errata framework ([5c41582](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5c41582ce9bda0857602af7da4be9bcfcc95ac94))
+ - workaround platforms non-arm interconnect ([992bc50](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/992bc50a1d037679c333ab3286be6a0a15a08bbd))
+
+### Miscellaneous
+
+- add dependency files generated by tools to .gitignore ([49fdb33](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/49fdb333b06f6152ea3f3568ec341f5eec0b59d5))
+- rearrange the fvp_cpu_errata.mk file ([5bd17d8](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/5bd17d849da4a07a72778956dab21c55ffe23cbe))
+- rename Poseidon to Neoverse V3 ([a1bd6dc](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/a1bd6dc766ab433a79f84fd6cb38bcc24be460d3))
+
+### Resolved Issues
+
+- **Libraries**
+
+ - **CPU Support**
+
+ - add erratum 2701951 to Cortex-X3's list ([538c637](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/538c637ed2ea9438f7d6afd93c1df3ebb0c0204f))
+ - fix a defect in Cortex-A715 erratum 2561034 ([f14464e](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f14464ed5728e8d3fd9fc9687508745e30a089b6))
+ - workaround for Cortex-A715 erratum 2331818 ([877e934](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/877e9341c662aaa4f2f76f7b8495e9210b36b09e))
+ - workaround for Cortex-A715 erratum 2344187 ([bd32e62](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/bd32e62e8a2944f8739fc862b0be3adcb8ef23f2))
+ - workaround for Cortex-A715 erratum 2413290 ([39e3e65](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/39e3e65ff9f2ca2a616c960d7ea8b3b6c5c20d41))
+ - workaround for Cortex-A715 erratum 2413290 ([81270d9](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/81270d9ac7db339fca74ad36e389e82bacbd6891))
+ - workaround for Cortex-A715 erratum 2420947 ([84e8de6](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/84e8de60cc7f53ec86fb42ccbc424de0046772c9))
+ - workaround for Cortex-A715 erratum 2429384 ([6a8a867](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/6a8a8671c692bf603550dcd98ce24f1e47885252))
+ - workaround for Cortex-A720 erratum 2926083 ([205980a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/205980a83a4b8388e7e1ca384ab6b71008103148))
+ - workaround for Cortex-A720 erratum 2940794 ([4696806](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/469680668282cf4c24adb90a4ddca5815fe533dc))
+ - workaround for Cortex-X3 erratum 2372204 ([f3557c4](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/f3557c49e34a11444b3a9760f4da9a0c91da82ee))
+ - workaround for Cortex-X4 erratum 2701112 ([656c431](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/656c431e0cf036cdac8bf0cc3f512496fe975906))
+
+- **Drivers**
+
+ - **Arm**
+
+ - **GIC**
+
+ - **GICv3**
+
+ - **GIC-600**
+
+ - workaround for Part 1 of GIC600 erratum 2384374 ([abf8a21](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/abf8a21b546a8dd7d101809a833887c1fa75fcbb))
+
## [lts-2.8.16](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trusted-firmware-a/+/refs/tags/lts-v2.8.15..refs/tags/lts-v2.8.16) (2024-02-08)
### Resolved Issues
diff --git a/docs/components/platform-interrupt-controller-API.rst b/docs/components/platform-interrupt-controller-API.rst
index 069c87b..aaafd2e 100644
--- a/docs/components/platform-interrupt-controller-API.rst
+++ b/docs/components/platform-interrupt-controller-API.rst
@@ -282,9 +282,28 @@
that it's overwriting.
In case of Arm standard platforms using GIC, the implementation of the API
-inserts to order memory updates before updating mask, then writes to the GIC
-*Priority Mask Register*, and make sure memory updates are visible before
-potential trigger due to mask update.
+inserts barriers to order memory updates before updating mask,
+then writes to the GIC *Priority Mask Register*, and make sure memory updates
+are visible before potential trigger due to mask update.
+
+Function: unsigned int plat_ic_deactivate_priority(unsigned int id); [optional]
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+::
+
+ Argument : unsigned int
+ Return : int
+
+This API performs the operations of plat_ic_set_priority_mask along with
+calling the errata workaround gicv3_apply_errata_wa_2384374(). This is
+performed when priority mask is restored to it's older value. This API returns
+the current priority value that it's overwriting.
+
+In case of Arm standard platforms using GIC, the implementation of the API
+inserts barriers to order memory updates before updating mask, then writes
+to the GIC *Priority Mask Register*, and make sure memory updates
+are visible before potential trigger due to mask update, and
+applies 2384374 GIC errata workaround to process pending interrupt packets.
.. _plat_ic_get_interrupt_id:
diff --git a/docs/conf.py b/docs/conf.py
index 6a89e22..9ccea09 100644
--- a/docs/conf.py
+++ b/docs/conf.py
@@ -14,8 +14,8 @@
project = "Trusted Firmware-A"
author = "Trusted Firmware-A contributors"
-version = "2.8.16"
-release = "2.8.16"
+version = "2.8.18"
+release = "2.8.18"
# -- General configuration ---------------------------------------------------
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index abd9f87..7a61008 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -795,6 +795,11 @@
CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU.
It is fixed in r1p1.
+- ``ERRATA_X3_2701951``: This applies erratum 2701951 workaround to Cortex-X3
+ CPU and affects system configurations that do not use an ARM interconnect
+ IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed
+ in r1p2.
+
- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to
Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
r1p1. It is fixed in r1p2.
@@ -807,6 +812,16 @@
CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
CPU. It is fixed in r1p2.
+For Cortex-X4, the following errata build flags are defined :
+
+- ``ERRATA_X4_2701112``: This applies erratum 2701112 workaround to Cortex-X4
+ CPU and affects system configurations that do not use an Arm interconnect IP.
+ This needs to be enabled for revisions r0p0 and is fixed in r0p1.
+ The workaround for this erratum is not implemented in EL3, but the flag can
+ be enabled/disabled at the platform level. The flag is used when the errata ABI
+ feature is enabled and can assist the Kernel in the process of
+ mitigation of the erratum.
+
For Cortex-A510, the following errata build flags are defined :
- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
@@ -872,14 +887,40 @@
For Cortex-A715, the following errata build flags are defined :
+- ``ERRATA_A715_2331818``: This applies errata 2331818 workaround to
+ Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0.
+ It is fixed in r1p1.
+
+- ``ERRATA_A715_2344187``: This applies errata 2344187 workaround to
+ Cortex-A715 CPU. This needs to be enabled for revisions r0p0 and r1p0. It is
+ fixed in r1p1.
+
+- ``ERRATA_A715_2413290``: This applies errata 2413290 workaround to
+ Cortex-A715 CPU. This needs to be enabled only for revision r1p0 and
+ when SPE(Statistical profiling extension)=True. The errata is fixed
+ in r1p1.
+
+- ``ERRATA_A715_2420947``: This applies errata 2420947 workaround to
+ Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
+ It is fixed in r1p1.
+
+- ``ERRATA_A715_2429384``: This applies errata 2429384 workaround to
+ Cortex-A715 CPU. This needs to be enabled for revision r1p0. There is no
+ workaround for revision r0p0. It is fixed in r1p1.
+
- ``ERRATA_A715_2561034``: This applies errata 2561034 workaround to
Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
It is fixed in r1p1.
-- ``ERRATA_A715_2701951``: This applies erratum 2701951 workaround to Cortex-A715
- CPU and affects system configurations that do not use an ARM interconnect
- IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed
- in r1p2.
+For Cortex-A720, the following errata build flags are defined :
+
+- ``ERRATA_A720_2926083``: This applies errata 2926083 workaround to
+ Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1.
+ It is fixed in r0p2.
+
+- ``ERRATA_A720_2940794``: This applies errata 2940794 workaround to
+ Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1.
+ It is fixed in r0p2.
DSU Errata Workarounds
----------------------
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index ec547b5..e3b33e4 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -71,7 +71,7 @@
The following libraries are required for Trusted Board Boot and Measured Boot
support:
-- mbed TLS == 2.28.5 (tag: ``mbedtls-2.28.5``)
+- mbed TLS == 2.28.8 (tag: ``mbedtls-2.28.8``)
These tools are optional:
@@ -178,7 +178,7 @@
--------------
-*Copyright (c) 2021-2023, Arm Limited. All rights reserved.*
+*Copyright (c) 2021-2024, Arm Limited. All rights reserved.*
.. _Arm Developer website: https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/downloads
.. _Gerrit Code Review: https://www.gerritcodereview.com/
diff --git a/docs/security_advisories/security-advisory-tfv-9.rst b/docs/security_advisories/security-advisory-tfv-9.rst
index 762801d..014221e 100644
--- a/docs/security_advisories/security-advisory-tfv-9.rst
+++ b/docs/security_advisories/security-advisory-tfv-9.rst
@@ -87,7 +87,7 @@
+----------------------+
| Neoverse-V2 |
+----------------------+
-| Neoverse-Poseidon |
+| Neoverse-V3 |
+----------------------+
For all other cores impacted by Spectre-BHB, some of which that do not implement
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index 7a67384..22761fb 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -14,6 +14,7 @@
#include <drivers/arm/gic600_multichip.h>
#include <drivers/arm/gicv3.h>
#include <lib/spinlock.h>
+#include <plat/common/platform.h>
#include "gicv3_private.h"
@@ -1296,6 +1297,31 @@
}
/*******************************************************************************
+ * This function restores the PMR register to old value and also triggers
+ * gicv3_apply_errata_wa_2384374() that flushes the GIC buffer allowing any
+ * pending interrupts to processed. Returns the original PMR.
+ ******************************************************************************/
+unsigned int gicv3_deactivate_priority(unsigned int mask)
+{
+
+ unsigned int old_mask, proc_num;
+ uintptr_t gicr_base;
+
+ old_mask = gicv3_set_pmr(mask);
+
+ proc_num = plat_my_core_pos();
+ gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+ assert(gicr_base != 0UL);
+
+ /* Add DSB to ensure visibility of System register writes */
+ dsb();
+
+ gicv3_apply_errata_wa_2384374(gicr_base);
+
+ return old_mask;
+}
+
+/*******************************************************************************
* This function delegates the responsibility of discovering the corresponding
* Redistributor frames to each CPU itself. It is a modified version of
* gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index f63e923..67028bc 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -1281,6 +1281,8 @@
#define RGSR_EL1 S3_0_C1_C0_5
#define GCR_EL1 S3_0_C1_C0_6
+#define GCR_EL1_RRND_BIT (UL(1) << 16)
+
/*******************************************************************************
* FEAT_HCX - Extended Hypervisor Configuration Register
******************************************************************************/
diff --git a/include/drivers/arm/gicv3.h b/include/drivers/arm/gicv3.h
index 5bb22fd..824b075 100644
--- a/include/drivers/arm/gicv3.h
+++ b/include/drivers/arm/gicv3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -588,6 +588,7 @@
void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num);
void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num);
unsigned int gicv3_set_pmr(unsigned int mask);
+unsigned int gicv3_deactivate_priority(unsigned int mask);
void gicv3_get_component_prodid_rev(const uintptr_t gicd_base,
unsigned int *gic_prod_id,
diff --git a/include/lib/cpus/aarch64/cortex_a715.h b/include/lib/cpus/aarch64/cortex_a715.h
index 366894d..c7f50db 100644
--- a/include/lib/cpus/aarch64/cortex_a715.h
+++ b/include/lib/cpus/aarch64/cortex_a715.h
@@ -13,6 +13,11 @@
#define CORTEX_A715_BHB_LOOP_COUNT U(38)
/*******************************************************************************
+ * CPU Auxiliary Control register 1 specific definitions.
+ ******************************************************************************/
+#define CORTEX_A715_CPUACTLR_EL1 S3_0_C15_C1_0
+
+/*******************************************************************************
* CPU Auxiliary Control register 2 specific definitions.
******************************************************************************/
#define CORTEX_A715_CPUACTLR2_EL1 S3_0_C15_C1_1
@@ -22,6 +27,11 @@
******************************************************************************/
#define CORTEX_A715_CPUECTLR_EL1 S3_0_C15_C1_4
+#define CORTEX_A715_CPUPSELR_EL3 S3_6_C15_C8_0
+#define CORTEX_A715_CPUPCR_EL3 S3_6_C15_C8_1
+#define CORTEX_A715_CPUPOR_EL3 S3_6_C15_C8_2
+#define CORTEX_A715_CPUPMR_EL3 S3_6_C15_C8_3
+
/*******************************************************************************
* CPU Power Control register specific definitions
******************************************************************************/
diff --git a/include/lib/cpus/aarch64/cortex_a720.h b/include/lib/cpus/aarch64/cortex_a720.h
index 47bbbc0..fb27f79 100644
--- a/include/lib/cpus/aarch64/cortex_a720.h
+++ b/include/lib/cpus/aarch64/cortex_a720.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,6 +13,16 @@
#define CORTEX_A720_BHB_LOOP_COUNT U(132)
/*******************************************************************************
+ * CPU Auxiliary Control register 1 specific definitions.
+ ******************************************************************************/
+#define CORTEX_A720_CPUACTLR_EL1 S3_0_C15_C1_0
+
+/*******************************************************************************
+ * CPU Auxiliary Control register 2 specific definitions.
+ ******************************************************************************/
+#define CORTEX_A720_CPUACTLR2_EL1 S3_0_C15_C1_1
+
+/*******************************************************************************
* CPU Extended Control register specific definitions
******************************************************************************/
#define CORTEX_A720_CPUECTLR_EL1 S3_0_C15_C1_4
diff --git a/include/lib/cpus/aarch64/neoverse_poseidon.h b/include/lib/cpus/aarch64/neoverse_poseidon.h
deleted file mode 100644
index 798ecd1..0000000
--- a/include/lib/cpus/aarch64/neoverse_poseidon.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2022, ARM Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef NEOVERSE_POSEIDON_H
-#define NEOVERSE_POSEIDON_H
-
-
-#define NEOVERSE_POSEIDON_MIDR U(0x410FD830)
-
-/* Neoverse Poseidon loop count for CVE-2022-23960 mitigation */
-#define NEOVERSE_POSEIDON_BHB_LOOP_COUNT U(132)
-
-/*******************************************************************************
- * CPU Extended Control register specific definitions.
- ******************************************************************************/
-#define NEOVERSE_POSEIDON_CPUECTLR_EL1 S3_0_C15_C1_4
-
-/*******************************************************************************
- * CPU Power Control register specific definitions
- ******************************************************************************/
-#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1 S3_0_C15_C2_7
-#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
-
-#endif /* NEOVERSE_POSEIDON_H */
diff --git a/include/lib/cpus/aarch64/neoverse_v3.h b/include/lib/cpus/aarch64/neoverse_v3.h
new file mode 100644
index 0000000..be9530e
--- /dev/null
+++ b/include/lib/cpus/aarch64/neoverse_v3.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2022, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NEOVERSE_V3_H
+#define NEOVERSE_V3_H
+
+
+#define NEOVERSE_V3_VNAE_MIDR U(0x410FD830)
+#define NEOVERSE_V3_MIDR U(0x410FD840)
+
+/* Neoverse V3 loop count for CVE-2022-23960 mitigation */
+#define NEOVERSE_V3_BHB_LOOP_COUNT U(132)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_V3_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define NEOVERSE_V3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* NEOVERSE_V3_H */
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index 472ed34..26e668b 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -128,6 +128,7 @@
void plat_ic_set_interrupt_pending(unsigned int id);
void plat_ic_clear_interrupt_pending(unsigned int id);
unsigned int plat_ic_set_priority_mask(unsigned int mask);
+unsigned int plat_ic_deactivate_priority(unsigned int mask);
unsigned int plat_ic_get_interrupt_id(unsigned int raw);
/*******************************************************************************
diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S
index 0faa276..a5be22d 100644
--- a/lib/cpus/aarch64/cortex_a715.S
+++ b/lib/cpus/aarch64/cortex_a715.S
@@ -26,9 +26,71 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715
#endif /* WORKAROUND_CVE_2022_23960 */
-workaround_runtime_start cortex_a715, ERRATUM(2561034), ERRATA_A715_2561034
+workaround_reset_start cortex_a715, ERRATUM(2331818), ERRATA_A715_2331818
+ sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(20)
+workaround_reset_end cortex_a715, ERRATUM(2331818)
+
+check_erratum_ls cortex_a715, ERRATUM(2331818), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a715, ERRATUM(2344187), ERRATA_A715_2344187
+ /* GCR_EL1 is only present with FEAT_MTE2. */
+ mrs x1, ID_AA64PFR1_EL1
+ ubfx x0, x1, ID_AA64PFR1_EL1_MTE_SHIFT, #4
+ cmp x0, #MTE_IMPLEMENTED_ELX
+ bne #1f
+ sysreg_bit_set GCR_EL1, GCR_EL1_RRND_BIT
+
+1:
+ /* Mitigation upon ERETAA and ERETAB. */
+ mov x0, #2
+ msr CORTEX_A715_CPUPSELR_EL3, x0
+ isb
+ ldr x0, =0xd69f0bff
+ msr CORTEX_A715_CPUPOR_EL3, x0
+ ldr x0, =0xfffffbff
+ msr CORTEX_A715_CPUPMR_EL3, x0
+ mov x1, #0
+ orr x1, x1, #(1<<0)
+ orr x1, x1, #(3<<4)
+ orr x1, x1, #(0xf<<6)
+ orr x1, x1, #(1<<13)
+ orr x1, x1, #(1<<53)
+ msr CORTEX_A715_CPUPCR_EL3, x1
+workaround_reset_end cortex_a715, ERRATUM(2344187)
+
+check_erratum_ls cortex_a715, ERRATUM(2344187), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a715, ERRATUM(2413290), ERRATA_A715_2413290
+/* Erratum 2413290 workaround is required only if SPE is enabled */
+#if ENABLE_SPE_FOR_NS != 0
+ /* Check if Static profiling extension is implemented or present. */
+ mrs x1, id_aa64dfr0_el1
+ ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4
+ cbz x0, 1f
+ /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */
+ sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(57)
+ sysreg_bit_set CORTEX_A715_CPUACTLR_EL1, BIT(58)
+1:
+#endif
+workaround_reset_end cortex_a715, ERRATUM(2413290)
+
+check_erratum_range cortex_a715, ERRATUM(2413290), CPU_REV(1,0), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a715, ERRATUM(2420947), ERRATA_A715_2420947
+ sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(33)
+workaround_reset_end cortex_a715, ERRATUM(2420947)
+
+check_erratum_range cortex_a715, ERRATUM(2420947), CPU_REV(1, 0), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a715, ERRATUM(2429384), ERRATA_A715_2429384
+ sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(27)
+workaround_reset_end cortex_a715, ERRATUM(2429384)
+
+check_erratum_range cortex_a715, ERRATUM(2429384), CPU_REV(1, 0), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a715, ERRATUM(2561034), ERRATA_A715_2561034
sysreg_bit_set CORTEX_A715_CPUACTLR2_EL1, BIT(26)
-workaround_runtime_end cortex_a715, ERRATUM(2561034), NO_ISB
+workaround_reset_end cortex_a715, ERRATUM(2561034)
check_erratum_range cortex_a715, ERRATUM(2561034), CPU_REV(1, 0), CPU_REV(1, 0)
diff --git a/lib/cpus/aarch64/cortex_a720.S b/lib/cpus/aarch64/cortex_a720.S
index 4b28fdb..53a1b78 100644
--- a/lib/cpus/aarch64/cortex_a720.S
+++ b/lib/cpus/aarch64/cortex_a720.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,6 +26,28 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720
#endif /* WORKAROUND_CVE_2022_23960 */
+workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083
+/* Erratum 2926083 workaround is required only if SPE is enabled */
+#if ENABLE_SPE_FOR_NS != 0
+ /* Check if Static profiling extension is implemented or present. */
+ mrs x1, id_aa64dfr0_el1
+ ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4
+ cbz x0, 1f
+ /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */
+ sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(57)
+ sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, BIT(58)
+1:
+#endif
+workaround_reset_end cortex_a720, ERRATUM(2926083)
+
+check_erratum_ls cortex_a720, ERRATUM(2926083), CPU_REV(0, 1)
+
+workaround_reset_start cortex_a720, ERRATUM(2940794), ERRATA_A720_2940794
+ sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(37)
+workaround_reset_end cortex_a720, ERRATUM(2940794)
+
+check_erratum_ls cortex_a720, ERRATUM(2940794), CPU_REV(0, 1)
+
workaround_reset_start cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
/*
diff --git a/lib/cpus/aarch64/neoverse_poseidon.S b/lib/cpus/aarch64/neoverse_poseidon.S
deleted file mode 100644
index 3b3245d..0000000
--- a/lib/cpus/aarch64/neoverse_poseidon.S
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <common/bl_common.h>
-#include <neoverse_poseidon.h>
-#include <cpu_macros.S>
-#include <plat_macros.S>
-#include "wa_cve_2022_23960_bhb_vector.S"
-
-/* Hardware handled coherency */
-#if HW_ASSISTED_COHERENCY == 0
-#error "Neoverse Poseidon must be compiled with HW_ASSISTED_COHERENCY enabled"
-#endif
-
-/* 64-bit only core */
-#if CTX_INCLUDE_AARCH32_REGS == 1
-#error "Neoverse Poseidon supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
-#endif
-
-#if WORKAROUND_CVE_2022_23960
- wa_cve_2022_23960_bhb_vector_table NEOVERSE_POSEIDON_BHB_LOOP_COUNT, neoverse_poseidon
-#endif /* WORKAROUND_CVE_2022_23960 */
-
-workaround_reset_start neoverse_poseidon, CVE(2022,23960), WORKAROUND_CVE_2022_23960
-#if IMAGE_BL31
- /*
- * The Neoverse-poseidon generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- override_vector_table wa_cve_vbar_neoverse_poseidon
-
-#endif /* IMAGE_BL31 */
-workaround_reset_end neoverse_poseidon, CVE(2022,23960)
-
-check_erratum_chosen neoverse_poseidon, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-
- /* ---------------------------------------------
- * HW will do the cache maintenance while powering down
- * ---------------------------------------------
- */
-func neoverse_poseidon_core_pwr_dwn
- /* ---------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------
- */
- sysreg_bit_set NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, \
- NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-
- isb
- ret
-endfunc neoverse_poseidon_core_pwr_dwn
-
-cpu_reset_func_start neoverse_poseidon
- /* Disable speculative loads */
- msr SSBS, xzr
-cpu_reset_func_end neoverse_poseidon
-
-errata_report_shim neoverse_poseidon
-
- /* ---------------------------------------------
- * This function provides Neoverse-Poseidon specific
- * register information for crash reporting.
- * It needs to return with x6 pointing to
- * a list of register names in ascii and
- * x8 - x15 having values of registers to be
- * reported.
- * ---------------------------------------------
- */
-.section .rodata.neoverse_poseidon_regs, "aS"
-neoverse_poseidon_regs: /* The ascii list of register names to be reported */
- .asciz "cpuectlr_el1", ""
-
-func neoverse_poseidon_cpu_reg_dump
- adr x6, neoverse_poseidon_regs
- mrs x8, NEOVERSE_POSEIDON_CPUECTLR_EL1
- ret
-endfunc neoverse_poseidon_cpu_reg_dump
-
-declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_MIDR, \
- neoverse_poseidon_reset_func, \
- neoverse_poseidon_core_pwr_dwn
diff --git a/lib/cpus/aarch64/neoverse_v3.S b/lib/cpus/aarch64/neoverse_v3.S
new file mode 100644
index 0000000..67258c8
--- /dev/null
+++ b/lib/cpus/aarch64/neoverse_v3.S
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <neoverse_v3.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+#include "wa_cve_2022_23960_bhb_vector.S"
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Neoverse V3 must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Neoverse V3 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+#if WORKAROUND_CVE_2022_23960
+ wa_cve_2022_23960_bhb_vector_table NEOVERSE_V3_BHB_LOOP_COUNT, neoverse_v3
+#endif /* WORKAROUND_CVE_2022_23960 */
+
+workaround_reset_start neoverse_v3, CVE(2022,23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Neoverse V3 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
+ */
+ override_vector_table wa_cve_vbar_neoverse_v3
+
+#endif /* IMAGE_BL31 */
+workaround_reset_end neoverse_v3, CVE(2022,23960)
+
+check_erratum_chosen neoverse_v3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+
+ /* ---------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ---------------------------------------------
+ */
+func neoverse_v3_core_pwr_dwn
+ /* ---------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------
+ */
+ sysreg_bit_set NEOVERSE_V3_CPUPWRCTLR_EL1, \
+ NEOVERSE_V3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+
+ isb
+ ret
+endfunc neoverse_v3_core_pwr_dwn
+
+cpu_reset_func_start neoverse_v3
+ /* Disable speculative loads */
+ msr SSBS, xzr
+cpu_reset_func_end neoverse_v3
+
+errata_report_shim neoverse_v3
+
+ /* ---------------------------------------------
+ * This function provides Neoverse V3 specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.neoverse_v3_regs, "aS"
+neoverse_v3_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func neoverse_v3_cpu_reg_dump
+ adr x6, neoverse_v3_regs
+ mrs x8, NEOVERSE_V3_CPUECTLR_EL1
+ ret
+endfunc neoverse_v3_cpu_reg_dump
+
+declare_cpu_ops neoverse_v3, NEOVERSE_V3_VNAE_MIDR, \
+ neoverse_v3_reset_func, \
+ neoverse_v3_core_pwr_dwn
+
+declare_cpu_ops neoverse_v3, NEOVERSE_V3_MIDR, \
+ neoverse_v3_reset_func, \
+ neoverse_v3_core_pwr_dwn
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index c411d47..38de989 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -803,6 +803,10 @@
# to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1.
CPU_FLAG_LIST += ERRATA_X3_2641945
+# Flag to apply erratum 2701951 workaround for non-arm interconnect ip.
+# This erratum applies to revisions r0p0, r1p0, and r1p1. Its is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_X3_2701951
+
# Flag to apply erratum 2742421 workaround on reset. This erratum applies
# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_X3_2742421
@@ -815,6 +819,11 @@
# to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
CPU_FLAG_LIST += ERRATA_X3_2779509
+# Flag to apply erratum 2701112 workaround for platforms that do not use an
+# Arm interconnect IP. This erratum applies to revisions r0p0 of the Cortex-X4
+# cpu and is fixed in r0p1.
+CPU_FLAG_LIST += ERRATA_X4_2701112
+
# Flag to apply erratum 1922240 workaround during reset. This erratum applies
# to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_A510_1922240
@@ -908,13 +917,37 @@
# This erratum applies to revisions r0p0, r0p1. Fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2801372
+# Flag to apply erratum 2331818 workaround during reset. This erratum applies
+# to revisions r0p0 and r1p0. It is fixed in r1p1.
+CPU_FLAG_LIST += ERRATA_A715_2331818
+
+# Flag to apply erratum 2344187 workaround during reset. This erratum applies
+# to revisions r0p0, and r1p0. It is fixed in r1p1.
+CPU_FLAG_LIST += ERRATA_A715_2344187
+
+# Flag to apply erratum 2413290 workaround during reset. This erratum applies
+# only to revision r1p0. It is fixed in r1p1.
+CPU_FLAG_LIST += ERRATA_A715_2413290
+
+# Flag to apply erratum 2420947 workaround during reset. This erratum applies
+# only to revision r1p0. It is fixed in r1p1.
+CPU_FLAG_LIST += ERRATA_A715_2420947
+
+# Flag to apply erratum 2429384 workaround during reset. This erratum applies
+# to revision r1p0. There is no workaround for r0p0. It is fixed in r1p1.
+CPU_FLAG_LIST += ERRATA_A715_2429384
+
# Flag to apply erratum 2561034 workaround during reset. This erratum applies
# only to revision r1p0. It is fixed in r1p1.
CPU_FLAG_LIST += ERRATA_A715_2561034
-# Flag to apply erratum 2701951 workaround for non-arm interconnect ip.
-# This erratum applies to revisions r0p0, r1p0, and r1p1. Its is fixed in r1p2.
-CPU_FLAG_LIST += ERRATA_A715_2701951
+# Flag to apply erratum 2926083 workaround during reset. This erratum applies
+# to revisions r0p0 and r0p1. It is fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_A720_2926083
+
+# Flag to apply erratum 2940794 workaround during reset. This erratum applies
+# to revisions r0p0 and r0p1. It is fixed in r0p2.
+CPU_FLAG_LIST += ERRATA_A720_2940794
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
# Applying the workaround results in higher DSU power consumption on idle.
diff --git a/package-lock.json b/package-lock.json
index 4203e07..edd700f 100644
--- a/package-lock.json
+++ b/package-lock.json
@@ -1,12 +1,12 @@
{
"name": "trusted-firmware-a",
- "version": "2.8.16",
+ "version": "2.8.18",
"lockfileVersion": 2,
"requires": true,
"packages": {
"": {
"name": "trusted-firmware-a",
- "version": "2.8.16",
+ "version": "2.8.18",
"hasInstallScript": true,
"license": "BSD-3-Clause",
"devDependencies": {
diff --git a/package.json b/package.json
index 2a99e7d..ee75925 100644
--- a/package.json
+++ b/package.json
@@ -1,6 +1,6 @@
{
"name": "trusted-firmware-a",
- "version": "2.8.16",
+ "version": "2.8.18",
"license": "BSD-3-Clause",
"private": true,
"scripts": {
diff --git a/plat/arm/board/fvp/fvp_cpu_errata.mk b/plat/arm/board/fvp/fvp_cpu_errata.mk
index b8fa4ea..b26fa80 100644
--- a/plat/arm/board/fvp/fvp_cpu_errata.mk
+++ b/plat/arm/board/fvp/fvp_cpu_errata.mk
@@ -1,63 +1,32 @@
#
-# Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
-
-#/*
-# * TODO: below lines of code to be removed
-# * after abi and framework are synchronized
-# */
+# Flags to enable the cpu structures in the Errata ABI file
+# file: services/std_svc/errata_abi/errata_abi_main.c. This is specifically
+# for platforms that need to enable errata based on non-arm interconnect IP.
ifeq (${ERRATA_ABI_SUPPORT}, 1)
-# enable the cpu macros for errata abi interface
-ifeq (${ARCH}, aarch64)
-ifeq (${HW_ASSISTED_COHERENCY}, 0)
-CORTEX_A35_H_INC := 1
-CORTEX_A53_H_INC := 1
-CORTEX_A57_H_INC := 1
-CORTEX_A72_H_INC := 1
-CORTEX_A73_H_INC := 1
-$(eval $(call add_define, CORTEX_A35_H_INC))
-$(eval $(call add_define, CORTEX_A53_H_INC))
-$(eval $(call add_define, CORTEX_A57_H_INC))
-$(eval $(call add_define, CORTEX_A72_H_INC))
-$(eval $(call add_define, CORTEX_A73_H_INC))
-else
+ifeq (${ERRATA_NON_ARM_INTERCONNECT}, 1)
ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0)
-CORTEX_A76_H_INC := 1
-CORTEX_A77_H_INC := 1
+CORTEX_A710_H_INC := 1
CORTEX_A78_H_INC := 1
-NEOVERSE_N1_H_INC := 1
+CORTEX_A78_AE_H_INC := 1
+CORTEX_A78C_H_INC := 1
+CORTEX_X3_H_INC := 1
+CORTEX_X4_H_INC := 1
NEOVERSE_N2_H_INC := 1
NEOVERSE_V1_H_INC := 1
-CORTEX_A78_AE_H_INC := 1
-CORTEX_A510_H_INC := 1
-CORTEX_A710_H_INC := 1
-CORTEX_A715_H_INC := 1
-CORTEX_A78C_H_INC := 1
-CORTEX_X2_H_INC := 1
-$(eval $(call add_define, CORTEX_A76_H_INC))
-$(eval $(call add_define, CORTEX_A77_H_INC))
+$(eval $(call add_define, CORTEX_A710_H_INC))
$(eval $(call add_define, CORTEX_A78_H_INC))
-$(eval $(call add_define, NEOVERSE_N1_H_INC))
+$(eval $(call add_define, CORTEX_A78_AE_H_INC))
+$(eval $(call add_define, CORTEX_A78C_H_INC))
+$(eval $(call add_define, CORTEX_X3_H_INC))
+$(eval $(call add_define, CORTEX_X4_H_INC))
$(eval $(call add_define, NEOVERSE_N2_H_INC))
$(eval $(call add_define, NEOVERSE_V1_H_INC))
-$(eval $(call add_define, CORTEX_A78_AE_H_INC))
-$(eval $(call add_define, CORTEX_A510_H_INC))
-$(eval $(call add_define, CORTEX_A710_H_INC))
-$(eval $(call add_define, CORTEX_A715_H_INC))
-$(eval $(call add_define, CORTEX_A78C_H_INC))
-$(eval $(call add_define, CORTEX_X2_H_INC))
endif
-CORTEX_A55_H_INC := 1
-CORTEX_A75_H_INC := 1
-$(eval $(call add_define, CORTEX_A55_H_INC))
-$(eval $(call add_define, CORTEX_A75_H_INC))
-endif
-else
-CORTEX_A32_H_INC := 1
-$(eval $(call add_define, CORTEX_A32_H_INC))
endif
endif
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 2a7d4c9..9f926ea 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -132,12 +132,15 @@
lib/cpus/aarch64/cortex_a78.S \
lib/cpus/aarch64/cortex_a78c.S \
lib/cpus/aarch64/cortex_a710.S \
+ lib/cpus/aarch64/cortex_a715.S \
+ lib/cpus/aarch64/cortex_a720.S \
lib/cpus/aarch64/neoverse_n_common.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_n2.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/neoverse_e1.S \
- lib/cpus/aarch64/cortex_x2.S
+ lib/cpus/aarch64/cortex_x2.S \
+ lib/cpus/aarch64/cortex_x4.S
endif
# AArch64/AArch32 cores
FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
diff --git a/plat/common/plat_gicv3.c b/plat/common/plat_gicv3.c
index e1420bb..c5b6ade 100644
--- a/plat/common/plat_gicv3.c
+++ b/plat/common/plat_gicv3.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
* Portions copyright (c) 2021-2022, ProvenRun S.A.S. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -313,6 +313,11 @@
return gicv3_set_pmr(mask);
}
+unsigned int plat_ic_deactivate_priority(unsigned int mask)
+{
+ return gicv3_deactivate_priority(mask);
+}
+
unsigned int plat_ic_get_interrupt_id(unsigned int raw)
{
unsigned int id = raw & INT_ID_MASK;
diff --git a/pyproject.toml b/pyproject.toml
index f5a8ec2..0cef587 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -1,6 +1,6 @@
[tool.poetry]
name = "trusted-firmware-a"
-version = "2.8.16"
+version = "2.8.18"
description = "Trusted Firmware-A (TF-A) Python dependencies."
authors = ["Arm Ltd."]
license = "BSD-3-Clause"
diff --git a/readme.rst b/readme.rst
index 148d477..c8cb86f 100644
--- a/readme.rst
+++ b/readme.rst
@@ -49,3 +49,5 @@
.. _view the full documentation: https://www.trustedfirmware.org/docs/tf-a
.. _trustedfirmware.org: http://www.trustedfirmware.org
+
+
diff --git a/services/std_svc/errata_abi/cpu_errata_info.h b/services/std_svc/errata_abi/cpu_errata_info.h
index 02dd3a8..2d59fc9 100644
--- a/services/std_svc/errata_abi/cpu_errata_info.h
+++ b/services/std_svc/errata_abi/cpu_errata_info.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2023-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,42 +11,25 @@
#include <arch_helpers.h>
#if __aarch64__
-#include <cortex_a35.h>
-#include <cortex_a510.h>
-#include <cortex_a520.h>
-#include <cortex_a53.h>
-#include <cortex_a57.h>
-#include <cortex_a55.h>
#include <cortex_a710.h>
-#include <cortex_a72.h>
-#include <cortex_a73.h>
-#include <cortex_a75.h>
-#include <cortex_a76.h>
-#include <cortex_a77.h>
#include <cortex_a78.h>
#include <cortex_a78_ae.h>
#include <cortex_a78c.h>
-#include <cortex_a715.h>
-#include <cortex_x1.h>
#include <cortex_x2.h>
#include <cortex_x3.h>
-#include <neoverse_n1.h>
+#include <cortex_x4.h>
#include <neoverse_n2.h>
#include <neoverse_v1.h>
#include <neoverse_v2.h>
-#else
-#include <cortex_a15.h>
-#include <cortex_a17.h>
-#include <cortex_a57.h>
-#include <cortex_a9.h>
#endif
-#define MAX_ERRATA_ENTRIES 32
+/* Max number of platform based errata with no workaround in EL3 */
+#define MAX_PLAT_CPU_ERRATA_ENTRIES 2
-#define ERRATA_LIST_END (MAX_ERRATA_ENTRIES - 1)
+#define ERRATA_LIST_END (MAX_PLAT_CPU_ERRATA_ENTRIES - 1)
/* Default values for unused memory in the array */
-#define UNDEF_ERRATA {UINT_MAX, UCHAR_MAX, UCHAR_MAX, false, false}
+#define UNDEF_ERRATA {UINT_MAX, UCHAR_MAX, UCHAR_MAX}
#define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
@@ -59,15 +42,11 @@
unsigned int em_errata_id;
unsigned char em_rxpx_lo; /* lowest revision of errata applicable for the cpu */
unsigned char em_rxpx_hi; /* highest revision of errata applicable for the cpu */
- bool errata_enabled; /* indicate if errata enabled */
- /* flag to indicate if errata query is based out of non-arm interconnect */
- bool non_arm_interconnect;
};
struct em_cpu_list{
- /* field to hold cpu specific part number defined in midr reg */
- unsigned long cpu_partnumber;
- struct em_cpu cpu_errata_list[MAX_ERRATA_ENTRIES];
+ unsigned long cpu_partnumber; /* cpu specific part number defined in midr reg */
+ struct em_cpu cpu_errata_list[MAX_PLAT_CPU_ERRATA_ENTRIES];
};
int32_t verify_errata_implemented(uint32_t errata_id, uint32_t forward_flag);
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index 811adcb..0a1d4f3 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -6,6 +6,8 @@
#include <assert.h>
#include "cpu_errata_info.h"
+#include <lib/cpus/cpu_ops.h>
+#include <lib/cpus/errata.h>
#include <lib/smccc.h>
#include <lib/utils_def.h>
#include <services/errata_abi_svc.h>
@@ -17,197 +19,14 @@
*/
struct em_cpu_list *cpu_ptr;
-extern uint8_t cpu_get_rev_var(void);
-
/* Structure array that holds CPU specific errata information */
struct em_cpu_list cpu_list[] = {
-#if CORTEX_A9_H_INC
-{
- .cpu_partnumber = CORTEX_A9_MIDR,
- .cpu_errata_list = {
- [0] = {794073, 0x00, 0xFF, ERRATA_A9_794073},
- [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
- }
-},
-#endif /* CORTEX_A9_H_INC */
-
-#if CORTEX_A15_H_INC
-{
- .cpu_partnumber = CORTEX_A15_MIDR,
- .cpu_errata_list = {
- [0] = {816470, 0x30, 0xFF, ERRATA_A15_816470},
- [1] = {827671, 0x30, 0xFF, ERRATA_A15_827671},
- [2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
- }
-},
-#endif /* CORTEX_A15_H_INC */
-
-#if CORTEX_A17_H_INC
-{
- .cpu_partnumber = CORTEX_A17_MIDR,
- .cpu_errata_list = {
- [0] = {852421, 0x00, 0x12, ERRATA_A17_852421},
- [1] = {852423, 0x00, 0x12, ERRATA_A17_852423},
- [2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
- }
-},
-#endif /* CORTEX_A17_H_INC */
-
-#if CORTEX_A35_H_INC
-{
- .cpu_partnumber = CORTEX_A35_MIDR,
- .cpu_errata_list = {
- [0] = {855472, 0x00, 0x00, ERRATA_A35_855472},
- [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
- }
-},
-#endif /* CORTEX_A35_H_INC */
-
-#if CORTEX_A53_H_INC
-{
- .cpu_partnumber = CORTEX_A53_MIDR,
- .cpu_errata_list = {
- [0] = {819472, 0x00, 0x01, ERRATA_A53_819472},
- [1] = {824069, 0x00, 0x02, ERRATA_A53_824069},
- [2] = {826319, 0x00, 0x02, ERRATA_A53_826319},
- [3] = {827319, 0x00, 0x02, ERRATA_A53_827319},
- [4] = {835769, 0x00, 0x04, ERRATA_A53_835769},
- [5] = {836870, 0x00, 0x03, ERRATA_A53_836870},
- [6] = {843419, 0x00, 0x04, ERRATA_A53_843419},
- [7] = {855873, 0x03, 0xFF, ERRATA_A53_855873},
- [8] = {1530924, 0x00, 0xFF, ERRATA_A53_1530924},
- [9 ... ERRATA_LIST_END] = UNDEF_ERRATA,
- }
-},
-#endif /* CORTEX_A53_H_INC */
-
-#if CORTEX_A55_H_INC
-{
- .cpu_partnumber = CORTEX_A55_MIDR,
- .cpu_errata_list = {
- [0] = {768277, 0x00, 0x00, ERRATA_A55_768277},
- [1] = {778703, 0x00, 0x00, ERRATA_A55_778703},
- [2] = {798797, 0x00, 0x00, ERRATA_A55_798797},
- [3] = {846532, 0x00, 0x01, ERRATA_A55_846532},
- [4] = {903758, 0x00, 0x01, ERRATA_A55_903758},
- [5] = {1221012, 0x00, 0x10, ERRATA_A55_1221012},
- [6] = {1530923, 0x00, 0xFF, ERRATA_A55_1530923},
- [7 ... ERRATA_LIST_END] = UNDEF_ERRATA,
- }
-},
-#endif /* CORTEX_A55_H_INC */
-
-#if CORTEX_A57_H_INC
-{
- .cpu_partnumber = CORTEX_A57_MIDR,
- .cpu_errata_list = {
- [0] = {806969, 0x00, 0x00, ERRATA_A57_806969},
- [1] = {813419, 0x00, 0x00, ERRATA_A57_813419},
- [2] = {813420, 0x00, 0x00, ERRATA_A57_813420},
- [3] = {814670, 0x00, 0x00, ERRATA_A57_814670},
- [4] = {817169, 0x00, 0x01, ERRATA_A57_817169},
- [5] = {826974, 0x00, 0x11, ERRATA_A57_826974},
- [6] = {826977, 0x00, 0x11, ERRATA_A57_826977},
- [7] = {828024, 0x00, 0x11, ERRATA_A57_828024},
- [8] = {829520, 0x00, 0x12, ERRATA_A57_829520},
- [9] = {833471, 0x00, 0x12, ERRATA_A57_833471},
- [10] = {859972, 0x00, 0x13, ERRATA_A57_859972},
- [11] = {1319537, 0x00, 0xFF, ERRATA_A57_1319537},
- [12 ... ERRATA_LIST_END] = UNDEF_ERRATA,
- }
-},
-#endif /* CORTEX_A57_H_INC */
-
-#if CORTEX_A72_H_INC
-{
- .cpu_partnumber = CORTEX_A72_MIDR,
- .cpu_errata_list = {
- [0] = {859971, 0x00, 0x03, ERRATA_A72_859971},
- [1] = {1319367, 0x00, 0xFF, ERRATA_A72_1319367},
- [2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
- }
-},
-#endif /* CORTEX_A72_H_INC */
-
-#if CORTEX_A73_H_INC
-{
- .cpu_partnumber = CORTEX_A73_MIDR,
- .cpu_errata_list = {
- [0] = {852427, 0x00, 0x00, ERRATA_A73_852427},
- [1] = {855423, 0x00, 0x01, ERRATA_A73_855423},
- [2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
- }
-},
-#endif /* CORTEX_A73_H_INC */
-
-#if CORTEX_A75_H_INC
-{
- .cpu_partnumber = CORTEX_A75_MIDR,
- .cpu_errata_list = {
- [0] = {764081, 0x00, 0x00, ERRATA_A75_764081},
- [1] = {790748, 0x00, 0x00, ERRATA_A75_790748},
- [2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
- }
-},
-#endif /* CORTEX_A75_H_INC */
-
-#if CORTEX_A76_H_INC
-{
- .cpu_partnumber = CORTEX_A76_MIDR,
- .cpu_errata_list = {
- [0] = {1073348, 0x00, 0x10, ERRATA_A76_1073348},
- [1] = {1130799, 0x00, 0x20, ERRATA_A76_1130799},
- [2] = {1165522, 0x00, 0xFF, ERRATA_A76_1165522},
- [3] = {1220197, 0x00, 0x20, ERRATA_A76_1220197},
- [4] = {1257314, 0x00, 0x30, ERRATA_A76_1257314},
- [5] = {1262606, 0x00, 0x30, ERRATA_A76_1262606},
- [6] = {1262888, 0x00, 0x30, ERRATA_A76_1262888},
- [7] = {1275112, 0x00, 0x30, ERRATA_A76_1275112},
- [8] = {1286807, 0x00, 0x30, ERRATA_A76_1286807},
- [9] = {1791580, 0x00, 0x40, ERRATA_A76_1791580},
- [10] = {1868343, 0x00, 0x40, ERRATA_A76_1868343},
- [11] = {1946160, 0x30, 0x41, ERRATA_A76_1946160},
- [12] = {2743102, 0x00, 0x41, ERRATA_A76_2743102},
- [13 ... ERRATA_LIST_END] = UNDEF_ERRATA,
- }
-},
-#endif /* CORTEX_A76_H_INC */
-
-#if CORTEX_A77_H_INC
-{
- .cpu_partnumber = CORTEX_A77_MIDR,
- .cpu_errata_list = {
- [0] = {1508412, 0x00, 0x10, ERRATA_A77_1508412},
- [1] = {1791578, 0x00, 0x11, ERRATA_A77_1791578},
- [2] = {1800714, 0x00, 0x11, ERRATA_A77_1800714},
- [3] = {1925769, 0x00, 0x11, ERRATA_A77_1925769},
- [4] = {1946167, 0x00, 0x11, ERRATA_A77_1946167},
- [5] = {2356587, 0x00, 0x11, ERRATA_A77_2356587},
- [6] = {2743100, 0x00, 0x11, ERRATA_A77_2743100},
- [7 ... ERRATA_LIST_END] = UNDEF_ERRATA,
- }
-},
-#endif /* CORTEX_A77_H_INC */
-
#if CORTEX_A78_H_INC
{
.cpu_partnumber = CORTEX_A78_MIDR,
.cpu_errata_list = {
- [0] = {1688305, 0x00, 0x10, ERRATA_A78_1688305},
- [1] = {1821534, 0x00, 0x10, ERRATA_A78_1821534},
- [2] = {1941498, 0x00, 0x11, ERRATA_A78_1941498},
- [3] = {1951500, 0x10, 0x11, ERRATA_A78_1951500},
- [4] = {1952683, 0x00, 0x00, ERRATA_A78_1952683},
- [5] = {2132060, 0x00, 0x12, ERRATA_A78_2132060},
- [6] = {2242635, 0x10, 0x12, ERRATA_A78_2242635},
- [7] = {2376745, 0x00, 0x12, ERRATA_A78_2376745},
- [8] = {2395406, 0x00, 0x12, ERRATA_A78_2395406},
- [9] = {2712571, 0x00, 0x12, ERRATA_A78_2712571, \
- ERRATA_NON_ARM_INTERCONNECT},
- [10] = {2742426, 0x00, 0x12, ERRATA_A78_2742426},
- [11] = {2772019, 0x00, 0x12, ERRATA_A78_2772019},
- [12] = {2779479, 0x00, 0x12, ERRATA_A78_2779479},
- [13 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [0] = {2712571, 0x00, 0x12},
+ [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_A78_H_INC */
@@ -216,13 +35,8 @@
{
.cpu_partnumber = CORTEX_A78_AE_MIDR,
.cpu_errata_list = {
- [0] = {1941500, 0x00, 0x01, ERRATA_A78_AE_1941500},
- [1] = {1951502, 0x00, 0x01, ERRATA_A78_AE_1951502},
- [2] = {2376748, 0x00, 0x02, ERRATA_A78_AE_2376748},
- [3] = {2395408, 0x00, 0x01, ERRATA_A78_AE_2395408},
- [4] = {2712574, 0x00, 0x02, ERRATA_A78_AE_2712574, \
- ERRATA_NON_ARM_INTERCONNECT},
- [5 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [0] = {2712574, 0x00, 0x02},
+ [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_A78_AE_H_INC */
@@ -231,82 +45,18 @@
{
.cpu_partnumber = CORTEX_A78C_MIDR,
.cpu_errata_list = {
- [0] = {1827430, 0x00, 0x00, ERRATA_A78C_1827430},
- [1] = {1827440, 0x00, 0x00, ERRATA_A78C_1827440},
- [2] = {2132064, 0x01, 0x02, ERRATA_A78C_2132064},
- [3] = {2242638, 0x01, 0x02, ERRATA_A78C_2242638},
- [4] = {2376749, 0x01, 0x02, ERRATA_A78C_2376749},
- [5] = {2395411, 0x01, 0x02, ERRATA_A78C_2395411},
- [6] = {2683027, 0x01, 0x02, ERRATA_A78C_2683027},
- [7] = {2712575, 0x01, 0x02, ERRATA_A78C_2712575, \
- ERRATA_NON_ARM_INTERCONNECT},
- [8] = {2743232, 0x01, 0x02, ERRATA_A78C_2743232},
- [9] = {2772121, 0x00, 0x02, ERRATA_A78C_2772121},
- [10] = {2779484, 0x01, 0x02, ERRATA_A78C_2779484},
- [11 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [0] = {2712575, 0x01, 0x02},
+ [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_A78C_H_INC */
-#if CORTEX_X1_H_INC
-{
- .cpu_partnumber = CORTEX_X1_MIDR,
- .cpu_errata_list = {
- [0] = {1688305, 0x00, 0x10, ERRATA_X1_1688305},
- [1] = {1821534, 0x00, 0x10, ERRATA_X1_1821534},
- [2] = {1827429, 0x00, 0x10, ERRATA_X1_1827429},
- [3 ... ERRATA_LIST_END] = UNDEF_ERRATA,
- }
-},
-#endif /* CORTEX_X1_H_INC */
-
-#if NEOVERSE_N1_H_INC
-{
- .cpu_partnumber = NEOVERSE_N1_MIDR,
- .cpu_errata_list = {
- [0] = {1043202, 0x00, 0x10, ERRATA_N1_1043202},
- [1] = {1073348, 0x00, 0x10, ERRATA_N1_1073348},
- [2] = {1130799, 0x00, 0x20, ERRATA_N1_1130799},
- [3] = {1165347, 0x00, 0x20, ERRATA_N1_1165347},
- [4] = {1207823, 0x00, 0x20, ERRATA_N1_1207823},
- [5] = {1220197, 0x00, 0x20, ERRATA_N1_1220197},
- [6] = {1257314, 0x00, 0x30, ERRATA_N1_1257314},
- [7] = {1262606, 0x00, 0x30, ERRATA_N1_1262606},
- [8] = {1262888, 0x00, 0x30, ERRATA_N1_1262888},
- [9] = {1275112, 0x00, 0x30, ERRATA_N1_1275112},
- [10] = {1315703, 0x00, 0x30, ERRATA_N1_1315703},
- [11] = {1542419, 0x30, 0x40, ERRATA_N1_1542419},
- [12] = {1868343, 0x00, 0x40, ERRATA_N1_1868343},
- [13] = {1946160, 0x30, 0x41, ERRATA_N1_1946160},
- [14] = {2743102, 0x00, 0x41, ERRATA_N1_2743102},
- [15 ... ERRATA_LIST_END] = UNDEF_ERRATA,
- }
-},
-#endif /* NEOVERSE_N1_H_INC */
-
#if NEOVERSE_V1_H_INC
{
.cpu_partnumber = NEOVERSE_V1_MIDR,
.cpu_errata_list = {
- [0] = {1618635, 0x00, 0x00, ERRATA_V1_1618635},
- [1] = {1774420, 0x00, 0x10, ERRATA_V1_1774420},
- [2] = {1791573, 0x00, 0x10, ERRATA_V1_1791573},
- [3] = {1852267, 0x00, 0x10, ERRATA_V1_1852267},
- [4] = {1925756, 0x00, 0x11, ERRATA_V1_1925756},
- [5] = {1940577, 0x10, 0x11, ERRATA_V1_1940577},
- [6] = {1966096, 0x10, 0x11, ERRATA_V1_1966096},
- [7] = {2108267, 0x00, 0x12, ERRATA_V1_2108267},
- [8] = {2139242, 0x00, 0x11, ERRATA_V1_2139242},
- [9] = {2216392, 0x10, 0x11, ERRATA_V1_2216392},
- [10] = {2294912, 0x00, 0x12, ERRATA_V1_2294912},
- [11] = {2348377, 0x00, 0x11, ERRATA_V1_2348377},
- [12] = {2372203, 0x00, 0x11, ERRATA_V1_2372203},
- [13] = {2701953, 0x00, 0x11, ERRATA_V1_2701953, \
- ERRATA_NON_ARM_INTERCONNECT},
- [14] = {2743093, 0x00, 0x12, ERRATA_V1_2743093},
- [15] = {2743233, 0x00, 0x12, ERRATA_V1_2743233},
- [16] = {2779461, 0x00, 0x12, ERRATA_V1_2779461},
- [17 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [0] = {2701953, 0x00, 0x11},
+ [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_V1_H_INC */
@@ -315,26 +65,8 @@
{
.cpu_partnumber = CORTEX_A710_MIDR,
.cpu_errata_list = {
- [0] = {1987031, 0x00, 0x20, ERRATA_A710_1987031},
- [1] = {2008768, 0x00, 0x20, ERRATA_A710_2008768},
- [2] = {2017096, 0x00, 0x20, ERRATA_A710_2017096},
- [3] = {2055002, 0x10, 0x20, ERRATA_A710_2055002},
- [4] = {2058056, 0x00, 0x21, ERRATA_A710_2058056},
- [5] = {2081180, 0x00, 0x20, ERRATA_A710_2081180},
- [6] = {2083908, 0x20, 0x20, ERRATA_A710_2083908},
- [7] = {2136059, 0x00, 0x20, ERRATA_A710_2136059},
- [8] = {2147715, 0x20, 0x20, ERRATA_A710_2147715},
- [9] = {2216384, 0x00, 0x20, ERRATA_A710_2216384},
- [10] = {2267065, 0x00, 0x20, ERRATA_A710_2267065},
- [11] = {2282622, 0x00, 0x21, ERRATA_A710_2282622},
- [12] = {2291219, 0x00, 0x20, ERRATA_A710_2291219},
- [13] = {2371105, 0x00, 0x20, ERRATA_A710_2371105},
- [14] = {2701952, 0x00, 0x21, ERRATA_A710_2701952, \
- ERRATA_NON_ARM_INTERCONNECT},
- [15] = {2742423, 0x00, 0x21, ERRATA_A710_2742423},
- [16] = {2768515, 0x00, 0x21, ERRATA_A710_2768515},
- [17] = {2778471, 0x00, 0x21, ERRATA_A710_2778471},
- [18 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [0] = {2701952, 0x00, 0x21},
+ [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_A710_H_INC */
@@ -343,28 +75,8 @@
{
.cpu_partnumber = NEOVERSE_N2_MIDR,
.cpu_errata_list = {
- [0] = {2002655, 0x00, 0x00, ERRATA_N2_2002655},
- [1] = {2009478, 0x00, 0x00, ERRATA_N2_2009478},
- [2] = {2025414, 0x00, 0x00, ERRATA_N2_2025414},
- [3] = {2067956, 0x00, 0x00, ERRATA_N2_2067956},
- [4] = {2138953, 0x00, 0x03, ERRATA_N2_2138953},
- [5] = {2138956, 0x00, 0x00, ERRATA_N2_2138956},
- [6] = {2138958, 0x00, 0x00, ERRATA_N2_2138958},
- [7] = {2189731, 0x00, 0x00, ERRATA_N2_2189731},
- [8] = {2242400, 0x00, 0x00, ERRATA_N2_2242400},
- [9] = {2242415, 0x00, 0x00, ERRATA_N2_2242415},
- [10] = {2280757, 0x00, 0x00, ERRATA_N2_2280757},
- [11] = {2326639, 0x00, 0x00, ERRATA_N2_2326639},
- [12] = {2340933, 0x00, 0x00, ERRATA_N2_2340933},
- [13] = {2346952, 0x00, 0x02, ERRATA_N2_2346952},
- [14] = {2376738, 0x00, 0x00, ERRATA_N2_2376738},
- [15] = {2388450, 0x00, 0x00, ERRATA_N2_2388450},
- [16] = {2728475, 0x00, 0x02, ERRATA_N2_2728475, \
- ERRATA_NON_ARM_INTERCONNECT},
- [17] = {2743014, 0x00, 0x02, ERRATA_N2_2743014},
- [18] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
- [19] = {2779511, 0x00, 0x02, ERRATA_N2_2779511},
- [20 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [0] = {2728475, 0x00, 0x02},
+ [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_N2_H_INC */
@@ -373,188 +85,129 @@
{
.cpu_partnumber = CORTEX_X2_MIDR,
.cpu_errata_list = {
- [0] = {2002765, 0x00, 0x20, ERRATA_X2_2002765},
- [1] = {2017096, 0x00, 0x20, ERRATA_X2_2017096},
- [2] = {2058056, 0x00, 0x21, ERRATA_X2_2058056},
- [3] = {2081180, 0x00, 0x20, ERRATA_X2_2081180},
- [4] = {2083908, 0x20, 0x20, ERRATA_X2_2083908},
- [5] = {2147715, 0x20, 0x20, ERRATA_X2_2147715},
- [6] = {2216384, 0x00, 0x20, ERRATA_X2_2216384},
- [7] = {2282622, 0x00, 0x21, ERRATA_X2_2282622},
- [8] = {2371105, 0x00, 0x20, ERRATA_X2_2371105},
- [9] = {2701952, 0x00, 0x21, ERRATA_X2_2701952, \
- ERRATA_NON_ARM_INTERCONNECT},
- [10] = {2742423, 0x00, 0x21, ERRATA_X2_2742423},
- [11] = {2768515, 0x00, 0x21, ERRATA_X2_2768515},
- [12] = {2778471, 0x00, 0x21, ERRATA_X2_2778471},
- [13 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [0] = {2701952, 0x00, 0x21},
+ [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_X2_H_INC */
-#if CORTEX_A510_H_INC
-{
- .cpu_partnumber = CORTEX_A510_MIDR,
- .cpu_errata_list = {
- [0] = {1922240, 0x00, 0x00, ERRATA_A510_1922240},
- [1] = {2041909, 0x02, 0x02, ERRATA_A510_2041909},
- [2] = {2042739, 0x00, 0x02, ERRATA_A510_2042739},
- [3] = {2080326, 0x02, 0x02, ERRATA_A510_2080326},
- [4] = {2172148, 0x00, 0x10, ERRATA_A510_2172148},
- [5] = {2218950, 0x00, 0x10, ERRATA_A510_2218950},
- [6] = {2250311, 0x00, 0x10, ERRATA_A510_2250311},
- [7] = {2288014, 0x00, 0x10, ERRATA_A510_2288014},
- [8] = {2347730, 0x00, 0x11, ERRATA_A510_2347730},
- [9] = {2371937, 0x00, 0x11, ERRATA_A510_2371937},
- [10] = {2666669, 0x00, 0x11, ERRATA_A510_2666669},
- [11] = {2684597, 0x00, 0x12, ERRATA_A510_2684597},
- [12 ... ERRATA_LIST_END] = UNDEF_ERRATA,
- }
-},
-#endif /* CORTEX_A510_H_INC */
-
#if NEOVERSE_V2_H_INC
{
.cpu_partnumber = NEOVERSE_V2_MIDR,
.cpu_errata_list = {
- [0] = {2331132, 0x00, 0x02, ERRATA_V2_2331132},
- [1] = {2618597, 0x00, 0x01, ERRATA_V2_2618597},
- [2] = {2662553, 0x00, 0x01, ERRATA_V2_2662553},
- [3] = {2719103, 0x00, 0x01, ERRATA_V2_2719103, \
- ERRATA_NON_ARM_INTERCONNECT},
- [4] = {2719105, 0x00, 0x01, ERRATA_V2_2719105},
- [5] = {2743011, 0x00, 0x01, ERRATA_V2_2743011},
- [6] = {2779510, 0x00, 0x01, ERRATA_V2_2779510},
- [7] = {2801372, 0x00, 0x01, ERRATA_V2_2801372},
- [8 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [0] = {2719103, 0x00, 0x01},
+ [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_V2_H_INC */
-#if CORTEX_A715_H_INC
-{
- .cpu_partnumber = CORTEX_A715_MIDR,
- .cpu_errata_list = {
- [0] = {2561034, 0x10, 0x10, ERRATA_A715_2561034},
- [1] = {2701951, 0x00, 0x11, ERRATA_A715_2701951, \
- ERRATA_NON_ARM_INTERCONNECT},
- [2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
- }
-},
-#endif /* CORTEX_A715_H_INC */
-
#if CORTEX_X3_H_INC
{
.cpu_partnumber = CORTEX_X3_MIDR,
.cpu_errata_list = {
- [0] = {2070301, 0x00, 0x12, ERRATA_X3_2070301},
- [1] = {2266875, 0x00, 0x10, ERRATA_X3_2266875},
- [2] = {2302506, 0x00, 0x11, ERRATA_X3_2302506},
- [3] = {2313909, 0x00, 0x10, ERRATA_X3_2313909},
- [4] = {2615812, 0x00, 0x11, ERRATA_X3_2615812},
- [5] = {2641945, 0x00, 0x10, ERRATA_X3_2641945},
- [6] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
- [7] = {2743088, 0x00, 0x11, ERRATA_X3_2743088},
- [8] = {2779509, 0x00, 0x11, ERRATA_X3_2779509},
- [9 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [0] = {2701951, 0x00, 0x11},
+ [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* CORTEX_X3_H_INC */
-#if CORTEX_A520_H_INC
+#if CORTEX_X4_H_INC
{
- .cpu_partnumber = CORTEX_A520_MIDR,
+ .cpu_partnumber = CORTEX_X4_MIDR,
.cpu_errata_list = {
- [0] = {2630792, 0x00, 0x01, ERRATA_A520_2630792},
- [1] = {2858100, 0x00, 0x01, ERRATA_A520_2858100},
- [2 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [0] = {2701112, 0x00, 0x00},
+ [1 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
-#endif /* CORTEX_A520_H_INC */
+#endif /* CORTEX_X4_H_INC */
};
-/*
- * Function to do binary search and check for the specific errata ID
- * in the array of structures specific to the cpu identified.
- */
-int32_t binary_search(struct em_cpu_list *ptr, uint32_t erratum_id, uint8_t rxpx_val)
+#if ERRATA_NON_ARM_INTERCONNECT
+
+/* Check if the errata is enabled for non-arm interconnect */
+static int32_t non_arm_interconnect_errata(uint32_t errata_id, long rev_var)
{
- int low_index = 0U, mid_index = 0U;
-
- int high_index = MAX_ERRATA_ENTRIES - 1;
-
- assert(ptr != NULL);
-
- /*
- * Pointer to the errata list of the cpu that matches
- * extracted partnumber in the cpu list
- */
- struct em_cpu *erratum_ptr = NULL;
-
- while (low_index <= high_index) {
- mid_index = (low_index + high_index) / 2;
-
- erratum_ptr = &ptr->cpu_errata_list[mid_index];
- assert(erratum_ptr != NULL);
-
- if (erratum_id < erratum_ptr->em_errata_id) {
- high_index = mid_index - 1;
- } else if (erratum_id > erratum_ptr->em_errata_id) {
- low_index = mid_index + 1;
- } else if (erratum_id == erratum_ptr->em_errata_id) {
- if (RXPX_RANGE(rxpx_val, erratum_ptr->em_rxpx_lo, \
- erratum_ptr->em_rxpx_hi)) {
- if ((erratum_ptr->errata_enabled) && \
- (!(erratum_ptr->non_arm_interconnect))) {
- return EM_HIGHER_EL_MITIGATION;
- }
- return EM_AFFECTED;
- }
- return EM_NOT_AFFECTED;
- }
- }
- /* no matching errata ID */
- return EM_UNKNOWN_ERRATUM;
-}
-
-/* Function to check if the errata exists for the specific CPU and rxpx */
-int32_t verify_errata_implemented(uint32_t errata_id, uint32_t forward_flag)
-{
- /*
- * Read MIDR value and extract the revision, variant and partnumber
- */
- static uint32_t midr_val, cpu_partnum;
- static uint8_t cpu_rxpx_val;
int32_t ret_val = EM_UNKNOWN_ERRATUM;
/* Determine the number of cpu listed in the cpu list */
uint8_t size_cpulist = ARRAY_SIZE(cpu_list);
/* Read the midr reg to extract cpu, revision and variant info */
- midr_val = read_midr();
+ uint32_t midr_val = read_midr();
- /* Extract revision and variant from the MIDR register */
- cpu_rxpx_val = cpu_get_rev_var();
-
- /* Extract the cpu partnumber and check if the cpu is in the cpu list */
- cpu_partnum = EXTRACT_PARTNUM(midr_val);
-
- for (uint8_t i = 0; i < size_cpulist; i++) {
+ for (uint8_t i = 0U; i < size_cpulist; i++) {
cpu_ptr = &cpu_list[i];
- uint16_t partnum_extracted = EXTRACT_PARTNUM(cpu_ptr->cpu_partnumber);
+ /*
+ * If the cpu partnumber in the cpu list, matches the midr
+ * part number, check to see if the errata ID matches
+ */
+ if (EXTRACT_PARTNUM(midr_val) == EXTRACT_PARTNUM(cpu_ptr->cpu_partnumber)) {
- if (partnum_extracted == cpu_partnum) {
- /*
- * If the midr value is in the cpu list, binary search
- * for the errata ID and specific revision in the list.
- */
- ret_val = binary_search(cpu_ptr, errata_id, cpu_rxpx_val);
+ struct em_cpu *ptr = NULL;
+
+ for (int j = 0; j < MAX_PLAT_CPU_ERRATA_ENTRIES; j++) {
+ ptr = &cpu_ptr->cpu_errata_list[j];
+ assert(ptr != NULL);
+ if (errata_id == ptr->em_errata_id) {
+ if (RXPX_RANGE(rev_var, ptr->em_rxpx_lo, ptr->em_rxpx_hi)) {
+ ret_val = EM_AFFECTED;
+ break;
+ }
+ ret_val = EM_NOT_AFFECTED;
+ break;
+ }
+ }
break;
}
}
return ret_val;
}
+#endif
+
+/* Function to check if the errata exists for the specific CPU and rxpx */
+int32_t verify_errata_implemented(uint32_t errata_id, uint32_t forward_flag)
+{
+ int32_t ret_val;
+ struct cpu_ops *cpu_ops;
+ struct erratum_entry *entry, *end;
+ long rev_var;
+
+ ret_val = EM_UNKNOWN_ERRATUM;
+ rev_var = cpu_get_rev_var();
+
+#if ERRATA_NON_ARM_INTERCONNECT
+ ret_val = non_arm_interconnect_errata(errata_id, rev_var);
+ if (ret_val != EM_UNKNOWN_ERRATUM) {
+ return ret_val;
+ }
+#endif
+
+ cpu_ops = get_cpu_ops_ptr();
+ assert(cpu_ops != NULL);
+
+ entry = cpu_ops->errata_list_start;
+ assert(entry != NULL);
+
+ end = cpu_ops->errata_list_end;
+ assert(end != NULL);
+
+ end--; /* point to the last erratum entry of the queried cpu */
+
+ while ((entry <= end) && (ret_val == EM_UNKNOWN_ERRATUM)) {
+ if (entry->id == errata_id) {
+ if (entry->check_func(rev_var)) {
+ if (entry->chosen)
+ return EM_HIGHER_EL_MITIGATION;
+ else
+ return EM_AFFECTED;
+ }
+ return EM_NOT_AFFECTED;
+ }
+ entry += 1;
+ }
+ return ret_val;
+}
/* Predicate indicating that a function id is part of EM_ABI */
bool is_errata_fid(uint32_t smc_fid)
diff --git a/tools/conventional-changelog-tf-a/package.json b/tools/conventional-changelog-tf-a/package.json
index d1793f7..a5ff8b0 100644
--- a/tools/conventional-changelog-tf-a/package.json
+++ b/tools/conventional-changelog-tf-a/package.json
@@ -1,6 +1,6 @@
{
"name": "conventional-changelog-tf-a",
- "version": "2.8.16",
+ "version": "2.8.18",
"license": "BSD-3-Clause",
"private": true,
"main": "index.js",