| commit | 2973054d9b4ba4fbcad7e04303ce8e0838b2f2b3 | [log] [tgz] |
|---|---|---|
| author | Sieu Mun Tang <sieu.mun.tang@intel.com> | Mon Oct 16 00:15:38 2023 +0800 |
| committer | Jit Loon Lim <jit.loon.lim@intel.com> | Fri Nov 03 21:18:51 2023 +0800 |
| tree | e30c53e4025a3da784ef4d3f9f1c52341bdb0745 | |
| parent | 93823fb6ec63a2d92cc2ca55fb3a8dbb5f9e8467 [diff] |
fix(intel): update HPS bridges for Agilex5 SoC FPGA This patch is used to update reset manager support for Agilex5 Soc FPGA. 1. Update HPS bridges support for socfpga_bridges_disable a. SOC2FPGA b. LWSOC2FPGA c. F2SDRAM d. F2SOC Change-Id: Ia539ff289e83303ae3b4d78b9ac1d50c9f9558da Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>