fix(cpus): add erratum 2701951 to Cortex-X3's list
Erratum ID 2701951 is an erratum that could affect platforms that
do not use an Arm interconnect IP. This was originally added to the list
of Cortex-A715 in the errata ABI files.
Fixed this by adding it to the Cortex-X3 list.
SDEN documentation:
https://developer.arm.com/documentation/2055130/latest
Change-Id: I6ffaf4360a4a2d0a23c253a2326c178e010c8e45
Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 1f27b4c..9aaa078 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -799,6 +799,11 @@
CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU.
It is fixed in r1p1.
+- ``ERRATA_X3_2701951``: This applies erratum 2701951 workaround to Cortex-X3
+ CPU and affects system configurations that do not use an ARM interconnect
+ IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed
+ in r1p2.
+
- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to
Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
r1p1. It is fixed in r1p2.
@@ -884,10 +889,6 @@
Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
It is fixed in r1p1.
-- ``ERRATA_A715_2701951``: This applies erratum 2701951 workaround to Cortex-A715
- CPU and affects system configurations that do not use an ARM interconnect
- IP. This needs to be applied to revisions r0p0, r1p0 and r1p1. It is fixed
- in r1p2.
DSU Errata Workarounds
----------------------