plat/qemu: move gicv2 codes to separate file
This file moves gicv2 codes to a new separate files, target is to add
gicv3 support later.
Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org>
Reviewed-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Tested-by: Radoslaw Biernacki <radoslaw.biernacki@linaro.org>
Change-Id: I30eb1fda5ea5c2b35d79360c52f46601cbca1bcc
diff --git a/plat/qemu/qemu_bl31_setup.c b/plat/qemu/qemu_bl31_setup.c
index 7453b89..4d36b03 100644
--- a/plat/qemu/qemu_bl31_setup.c
+++ b/plat/qemu/qemu_bl31_setup.c
@@ -1,16 +1,12 @@
/*
- * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
-#include <platform_def.h>
-
#include <common/bl_common.h>
-#include <drivers/arm/gic_common.h>
-#include <drivers/arm/gicv2.h>
#include <plat/common/platform.h>
#include "qemu_private.h"
@@ -73,49 +69,9 @@
BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
}
-/******************************************************************************
- * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
- * interrupts.
- *****************************************************************************/
-#define PLATFORM_G1S_PROPS(grp) \
- INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_EDGE), \
- INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_EDGE), \
- INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_EDGE), \
- INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_EDGE), \
- INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_EDGE), \
- INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_EDGE), \
- INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_EDGE), \
- INTR_PROP_DESC(QEMU_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
- grp, GIC_INTR_CFG_EDGE)
-
-#define PLATFORM_G0_PROPS(grp)
-
-static const interrupt_prop_t qemu_interrupt_props[] = {
- PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
- PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
-};
-
-static const struct gicv2_driver_data plat_gicv2_driver_data = {
- .gicd_base = GICD_BASE,
- .gicc_base = GICC_BASE,
- .interrupt_props = qemu_interrupt_props,
- .interrupt_props_num = ARRAY_SIZE(qemu_interrupt_props),
-};
-
void bl31_platform_setup(void)
{
- /* Initialize the gic cpu and distributor interfaces */
- gicv2_driver_init(&plat_gicv2_driver_data);
- gicv2_distif_init();
- gicv2_pcpu_distif_init();
- gicv2_cpuif_enable();
+ plat_qemu_gic_init();
}
unsigned int plat_get_syscnt_freq2(void)