fix(cpus): workaround for Cortex-A715 erratum 2420947
Cortex-A715 erratum 2420947 is a cat B erratum that applies only
to revision r1p0 and is fixed in r1p1. The workaround is to set
bit[33] of CPUACTLR2_EL1. This will prevent store and store-release
to merge inside the write buffer, and it is not expected to have
much performance impacts.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN2148827/latest
Change-Id: I01a71b878cd958e742ff8357f8cdfbfc5625de47
Signed-off-by: Bipin Ravi <biprav01@u203721.austin.arm.com>
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 9aaa078..416f9ee 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -881,6 +881,10 @@
For Cortex-A715, the following errata build flags are defined :
+- ``ERRATA_A715_2420947``: This applies errata 2420947 workaround to
+ Cortex-A715 CPU. This needs to be enabled only for revision r1p0.
+ It is fixed in r1p1.
+
- ``ERRATA_A715_2429384``: This applies errata 2429384 workaround to
Cortex-A715 CPU. This needs to be enabled for revision r1p0. There is no
workaround for revision r0p0. It is fixed in r1p1.