fix(cpus): workaround for Cortex-A715 erratum 3699560
Cortex-A715 erratum 3699560 that applies to all revisions <= r1p3
and is still Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2148827/latest/
Change-Id: I183aa921b4b6f715d64eb6b70809de2566017d31
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index 7c4db46..08f8786 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -11,6 +11,7 @@
#include <cortex_a75.h>
#include <cortex_a520.h>
#include <cortex_a710.h>
+#include <cortex_a715.h>
#include <cortex_x4.h>
#include <lib/cpus/cpu_ops.h>
#include <lib/cpus/errata.h>
@@ -52,6 +53,13 @@
break;
#endif /* ERRATA_A710_3701772 */
+#if ERRATA_A715_3699560
+ case EXTRACT_PARTNUM(CORTEX_A715_MIDR):
+ if (check_erratum_cortex_a715_3699560(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_A715_3699560 */
+
default:
break;
}