fix(cpus): workaround for Cortex-X925 erratum 2963999
Cortex-X925 erratum 2963999 that applies to r0p0 and is fixed in
r0p1.
In EL3, reads of MPIDR_EL1 and MIDR_EL1 might incorrectly virtualize
which register to return when reading the value of
MPIDR_EL1/VMPIDR_EL2 and MIDR_EL1/VPIDR_EL2, respectively.
The workaround is to do an ISB prior to an MRS read to either
MPIDR_EL1 and MIDR_EL1.
SDEN documentation:
https://developer.arm.com/documentation/109180/latest/
Change-Id: I447fd359ea32e1d274e1245886e1de57d14f082c
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 208d7cf..a871c59 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -897,6 +897,9 @@
For Cortex-X925, the following errata build flags are defined :
+- ``ERRATA_X925_2963999``: This applies errata 2963999 workaround to Cortex-X925
+ CPU. This needs to be enabled for revision r0p0. It is fixed in r0p1.
+
- ``ERRATA_X925_3701747``: This applies errata 3701747 workaround to Cortex-X925
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is still open.