feat(drtm): add platform functions for DRTM
Added platform hooks to retrieve DRTM features and
address map.
Additionally, implemented these hooks for the FVP platform.
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I5621cc9807ffff8139ae8876250147f7b2c76759
diff --git a/include/services/drtm_svc.h b/include/services/drtm_svc.h
index 6845ace..890cdbb 100644
--- a/include/services/drtm_svc.h
+++ b/include/services/drtm_svc.h
@@ -66,6 +66,158 @@
#define ARM_DRTM_FUNC_ID U(0x0)
#define ARM_DRTM_FEAT_ID U(0x1)
+/*
+ * Definitions for DRTM features as per DRTM beta0 section 3.3,
+ * Table 6 DRTM_FEATURES
+ */
+#define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT U(33)
+#define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK ULL(0xF)
+#define ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_DEFAULT ULL(0x1)
+
+#define ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT U(32)
+#define ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK ULL(0x1)
+#define ARM_DRTM_TPM_FEATURES_TPM_HASH_NOT_SUPPORTED ULL(0x0)
+#define ARM_DRTM_TPM_FEATURES_TPM_HASH_SUPPORTED ULL(0x1)
+
+#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT U(0)
+#define ARM_DRTM_TPM_FEATURES_FW_HASH_MASK ULL(0xFFFFFFFF)
+#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA256 ULL(0xB)
+#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA384 ULL(0xC)
+#define ARM_DRTM_TPM_FEATURES_FW_HASH_SHA512 ULL(0xD)
+
+#define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT U(32)
+#define ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK ULL(0xFFFFFFFF)
+
+#define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT U(0)
+#define ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK ULL(0xFFFFFFFF)
+
+#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT U(8)
+#define ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK ULL(0xF)
+
+#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT U(0)
+#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK ULL(0xFF)
+#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_COMPLETE ULL(0x1)
+#define ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_REGION ULL(0x2)
+
+#define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT U(0)
+#define ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK ULL(0xFF)
+
+#define ARM_DRTM_TPM_FEATURES_SET_PCR_SCHEMA(reg, val) \
+ do { \
+ reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK \
+ << ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT)) | (((val) & \
+ ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_MASK) << \
+ ARM_DRTM_TPM_FEATURES_PCR_SCHEMA_SHIFT)); \
+ } while (false)
+
+#define ARM_DRTM_TPM_FEATURES_SET_TPM_HASH(reg, val) \
+ do { \
+ reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK \
+ << ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT)) | (((val) & \
+ ARM_DRTM_TPM_FEATURES_TPM_HASH_MASK) << \
+ ARM_DRTM_TPM_FEATURES_TPM_HASH_SHIFT)); \
+ } while (false)
+
+#define ARM_DRTM_TPM_FEATURES_SET_FW_HASH(reg, val) \
+ do { \
+ reg = (((reg) & ~(ARM_DRTM_TPM_FEATURES_FW_HASH_MASK \
+ << ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT)) | (((val) & \
+ ARM_DRTM_TPM_FEATURES_FW_HASH_MASK) << \
+ ARM_DRTM_TPM_FEATURES_FW_HASH_SHIFT)); \
+ } while (false)
+
+#define ARM_DRTM_MIN_MEM_REQ_SET_DCE_SIZE(reg, val) \
+ do { \
+ reg = (((reg) & ~(ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK \
+ << ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT)) | (((val) & \
+ ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_MASK) << \
+ ARM_DRTM_MIN_MEM_REQ_DCE_SIZE_SHIFT)); \
+ } while (false)
+
+#define ARM_DRTM_MIN_MEM_REQ_SET_MIN_DLME_DATA_SIZE(reg, val) \
+ do { \
+ reg = (((reg) & \
+ ~(ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK << \
+ ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT)) | \
+ (((val) & ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_MASK) \
+ << ARM_DRTM_MIN_MEM_REQ_MIN_DLME_DATA_SIZE_SHIFT)); \
+ } while (false)
+
+#define ARM_DRTM_DMA_PROT_FEATURES_SET_MAX_REGIONS(reg, val) \
+ do { \
+ reg = (((reg) & \
+ ~(ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK << \
+ ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT)) | \
+ (((val) & ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_MASK) \
+ << ARM_DRTM_DMA_PROT_FEATURES_MAX_REGIONS_SHIFT)); \
+ } while (false)
+
+#define ARM_DRTM_DMA_PROT_FEATURES_SET_DMA_SUPPORT(reg, val) \
+ do { \
+ reg = (((reg) & \
+ ~(ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK << \
+ ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT)) | \
+ (((val) & ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_MASK) \
+ << ARM_DRTM_DMA_PROT_FEATURES_DMA_SUPPORT_SHIFT)); \
+ } while (false)
+
+#define ARM_DRTM_TCB_HASH_FEATURES_SET_MAX_NUM_HASHES(reg, val) \
+ do { \
+ reg = (((reg) & \
+ ~(ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK << \
+ ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT)) | \
+ (((val) & \
+ ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_MASK) << \
+ ARM_DRTM_TCB_HASH_FEATURES_MAX_NUM_HASHES_SHIFT)); \
+ } while (false)
+
+/* Definitions for DRTM address map */
+#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT U(55)
+#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK ULL(0x3)
+#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_NC ULL(0)
+#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WC ULL(1)
+#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WT ULL(2)
+#define ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_WB ULL(3)
+
+#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT U(52)
+#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK ULL(0x7)
+#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NORMAL ULL(0)
+#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NCAR ULL(1)
+#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_DEVICE ULL(2)
+#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_NV ULL(3)
+#define ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_RSVD ULL(4)
+
+#define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT U(0)
+#define ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK ULL(0xFFFFFFFFFFFFF)
+
+#define ARM_DRTM_REGION_SIZE_TYPE_SET_CACHEABILITY(reg, val) \
+ do { \
+ reg = (((reg) & \
+ ~(ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK << \
+ ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT)) | \
+ (((val) & \
+ ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_MASK) << \
+ ARM_DRTM_REGION_SIZE_TYPE_CACHEABILITY_SHIFT)); \
+ } while (false)
+
+#define ARM_DRTM_REGION_SIZE_TYPE_SET_REGION_TYPE(reg, val) \
+ do { \
+ reg = (((reg) & \
+ ~(ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK << \
+ ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT)) | \
+ (((val) & ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_MASK) \
+ << ARM_DRTM_REGION_SIZE_TYPE_REGION_TYPE_SHIFT)); \
+ } while (false)
+
+#define ARM_DRTM_REGION_SIZE_TYPE_SET_4K_PAGE_NUM(reg, val) \
+ do { \
+ reg = (((reg) & \
+ ~(ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK << \
+ ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT)) | \
+ (((val) & ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_MASK) \
+ << ARM_DRTM_REGION_SIZE_TYPE_4K_PAGE_NUM_SHIFT)); \
+ } while (false)
+
/* Initialization routine for the DRTM service */
int drtm_setup(void);