Merge changes from topic "hm/handoff-aarch32" into integration
* changes:
feat(fvp): support AArch32 booting with handoff
feat(arm): support AArch32 booting with handoff
diff --git a/bl32/tsp/tsp_common.c b/bl32/tsp/tsp_common.c
index 3a6c9d9..6095549 100644
--- a/bl32/tsp/tsp_common.c
+++ b/bl32/tsp/tsp_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -104,7 +104,7 @@
tsp_stats[linear_id].eret_count++;
INFO("TSP: cpu 0x%lx SYSTEM_OFF request\n", read_mpidr());
- INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(),
+ INFO("TSP: cpu 0x%lx: %u smcs, %u erets requests\n", read_mpidr(),
tsp_stats[linear_id].smc_count,
tsp_stats[linear_id].eret_count);
@@ -132,7 +132,7 @@
tsp_stats[linear_id].eret_count++;
INFO("TSP: cpu 0x%lx SYSTEM_RESET request\n", read_mpidr());
- INFO("TSP: cpu 0x%lx: %d smcs, %d erets requests\n", read_mpidr(),
+ INFO("TSP: cpu 0x%lx: %u smcs, %u erets requests\n", read_mpidr(),
tsp_stats[linear_id].smc_count,
tsp_stats[linear_id].eret_count);
diff --git a/bl32/tsp/tsp_interrupt.c b/bl32/tsp/tsp_interrupt.c
index a847b6c..9d86e3e 100644
--- a/bl32/tsp/tsp_interrupt.c
+++ b/bl32/tsp/tsp_interrupt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -37,8 +37,8 @@
VERBOSE("TSP: cpu 0x%lx sync s-el1 interrupt request from 0x%" PRIx64 "\n",
read_mpidr(), elr_el3);
- VERBOSE("TSP: cpu 0x%lx: %d sync s-el1 interrupt requests,"
- " %d sync s-el1 interrupt returns\n",
+ VERBOSE("TSP: cpu 0x%lx: %u sync s-el1 interrupt requests,"
+ " %u sync s-el1 interrupt returns\n",
read_mpidr(),
tsp_stats[linear_id].sync_sel1_intr_count,
tsp_stats[linear_id].sync_sel1_intr_ret_count);
@@ -54,7 +54,7 @@
uint32_t linear_id = plat_my_core_pos();
tsp_stats[linear_id].preempt_intr_count++;
- VERBOSE("TSP: cpu 0x%lx: %d preempt interrupt requests\n",
+ VERBOSE("TSP: cpu 0x%lx: %u preempt interrupt requests\n",
read_mpidr(), tsp_stats[linear_id].preempt_intr_count);
return TSP_PREEMPTED;
}
@@ -107,9 +107,9 @@
/* Update the statistics and print some messages */
tsp_stats[linear_id].sel1_intr_count++;
- VERBOSE("TSP: cpu 0x%lx handled S-EL1 interrupt %d\n",
+ VERBOSE("TSP: cpu 0x%lx handled S-EL1 interrupt %u\n",
read_mpidr(), id);
- VERBOSE("TSP: cpu 0x%lx: %d S-EL1 requests\n",
+ VERBOSE("TSP: cpu 0x%lx: %u S-EL1 requests\n",
read_mpidr(), tsp_stats[linear_id].sel1_intr_count);
return 0;
}
diff --git a/bl32/tsp/tsp_main.c b/bl32/tsp/tsp_main.c
index 8c6b2ed..1b7116a 100644
--- a/bl32/tsp/tsp_main.c
+++ b/bl32/tsp/tsp_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -47,7 +47,7 @@
tsp_stats[linear_id].eret_count++;
tsp_stats[linear_id].cpu_on_count++;
- INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
+ INFO("TSP: cpu 0x%lx: %u smcs, %u erets %u cpu on requests\n",
read_mpidr(),
tsp_stats[linear_id].smc_count,
tsp_stats[linear_id].eret_count,
@@ -75,7 +75,7 @@
tsp_stats[linear_id].cpu_on_count++;
INFO("TSP: cpu 0x%lx turned on\n", read_mpidr());
- INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
+ INFO("TSP: cpu 0x%lx: %u smcs, %u erets %u cpu on requests\n",
read_mpidr(),
tsp_stats[linear_id].smc_count,
tsp_stats[linear_id].eret_count,
@@ -112,7 +112,7 @@
tsp_stats[linear_id].cpu_off_count++;
INFO("TSP: cpu 0x%lx off request\n", read_mpidr());
- INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n",
+ INFO("TSP: cpu 0x%lx: %u smcs, %u erets %u cpu off requests\n",
read_mpidr(),
tsp_stats[linear_id].smc_count,
tsp_stats[linear_id].eret_count,
@@ -150,7 +150,7 @@
tsp_stats[linear_id].eret_count++;
tsp_stats[linear_id].cpu_suspend_count++;
- INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
+ INFO("TSP: cpu 0x%lx: %u smcs, %u erets %u cpu suspend requests\n",
read_mpidr(),
tsp_stats[linear_id].smc_count,
tsp_stats[linear_id].eret_count,
@@ -184,9 +184,9 @@
tsp_stats[linear_id].eret_count++;
tsp_stats[linear_id].cpu_resume_count++;
- INFO("TSP: cpu 0x%lx resumed. maximum off power level %" PRId64 "\n",
+ INFO("TSP: cpu 0x%lx resumed. maximum off power level %" PRIu64 "\n",
read_mpidr(), max_off_pwrlvl);
- INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu resume requests\n",
+ INFO("TSP: cpu 0x%lx: %u smcs, %u erets %u cpu resume requests\n",
read_mpidr(),
tsp_stats[linear_id].smc_count,
tsp_stats[linear_id].eret_count,
@@ -224,7 +224,7 @@
INFO("TSP: cpu 0x%lx received %s smc 0x%" PRIx64 "\n", read_mpidr(),
((func >> 31) & 1) == 1 ? "fast" : "yielding",
func);
- INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(),
+ INFO("TSP: cpu 0x%lx: %u smcs, %u erets\n", read_mpidr(),
tsp_stats[linear_id].smc_count,
tsp_stats[linear_id].eret_count);
diff --git a/changelog.yaml b/changelog.yaml
index f586471..6e7f179 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -186,21 +186,6 @@
scope: neoverse-rd
subsections:
- - title: SGI-575
- scope: sgi575
-
- - title: RD-E1-Edge
- scope: rde1edge
-
- - title: RD-N1-Edge
- scope: rdn1edge
-
- - title: RD-V1
- scope: rdv1
-
- - title: RD-V1-MC
- scope: rdv1mc
-
- title: RD-N2
scope: rdn2
diff --git a/docs/about/features.rst b/docs/about/features.rst
index 9b7bdf9..f15144a 100644
--- a/docs/about/features.rst
+++ b/docs/about/features.rst
@@ -127,7 +127,6 @@
Additionally the following libraries are marked experimental when included
in a platform:
-- MPU translation library ``lib/xlat_mpu``
- RSE comms driver ``drivers/arm/rse``
Still to come
@@ -151,4 +150,4 @@
--------------
-*Copyright (c) 2019-2023, Arm Limited. All rights reserved.*
+*Copyright (c) 2019-2025, Arm Limited. All rights reserved.*
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 3e33824..9e6f613 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -587,11 +587,8 @@
:|M|: Rohit Mathew <Rohit.Mathew@arm.com>
:|G|: `rohit-arm`_
:|F|: plat/arm/board/neoverse_rd/common
-:|F|: plat/arm/board/neoverse_rd/platform/rdn1edge/
:|F|: plat/arm/board/neoverse_rd/platform/rdn2/
-:|F|: plat/arm/board/neoverse_rd/platform/rdv1/
-:|F|: plat/arm/board/neoverse_rd/platform/rdv1mc/
-:|F|: plat/arm/board/neoverse_rd/platform/sgi575/
+:|F|: plat/arm/board/neoverse_rd/platform/rdv3/
Arm Total Compute platform port
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/docs/components/context-management-library.rst b/docs/components/context-management-library.rst
index 8cb1ace..cef6fba 100644
--- a/docs/components/context-management-library.rst
+++ b/docs/components/context-management-library.rst
@@ -106,7 +106,6 @@
#define FEAT_STATE_DISABLED 0
#define FEAT_STATE_ENABLED 1
#define FEAT_STATE_CHECK 2
- #define FEAT_STATE_CHECK_ASYMMETRIC 3
A pattern is established for feature enablement behavior.
Each feature must support the 3 possible values with rigid semantics.
@@ -120,15 +119,15 @@
- **FEAT_STATE_CHECK** - same as ``FEAT_STATE_ALWAYS`` except that the feature's
existence will be checked at runtime. Default on dynamic platforms (example: FVP).
-- **FEAT_STATE_CHECK_ASYMMETRIC** - same as ``FEAT_STATE_CHECK`` except that the feature's
- existence is asymmetric across cores, which requires the feature existence is checked
- during warmboot path also. Note that only limited number of features can be asymmetric.
-
.. note::
- Only limited number of features can be ``FEAT_STATE_CHECK_ASYMMETRIC`` this is due to
- the fact that Operating systems are designed for SMP systems.
- There are no clear guidelines what kind of mismatch is allowed but following pointers
- can help making a decision
+
+ In general, it is assumed that all cores will support the same set of
+ architectural features (features will be symmetrical). However, there are
+ cases where this is impractical to achieve. Only some features can be
+ mismatched among cores and this is the exception rather than the rule. This
+ is due to the fact that Operating systems are designed for SMP systems. There
+ are no clear guidelines what kind of mismatch is allowed but following
+ pointers can help in making a decision:
- All mandatory features must be symmetric.
- Any feature that impacts the generation of page tables must be symmetric.
@@ -136,8 +135,9 @@
- Features related with profiling, debug and trace could be asymmetric
- Migration of vCPU/tasks between CPUs should not cause an error
- Whenever there is asymmetric feature support is added for a feature TF-A need to add
- feature specific code in context management code.
+ TF-A caters for mismatched features, however, this is not regularly tested
+ for all features and may not work as expected, even without considering OS
+ support.
.. note::
``FEAT_RAS`` is an exception here, as it impacts the execution of EL3 and
@@ -345,9 +345,9 @@
|Context Init WarmBoot|
-The primary CPU initializes the Non-Secure context for the secondary CPU while
-restoring re-entry information for the Non-Secure world.
-It initialises via ``cm_init_context_by_index(target_idx, ep )``.
+The primary CPU writes the entrypoint for the secondary CPU. When the secondary
+wakes up it initialises its own context via ``cm_init_my_context( ep )`` using
+the provided entrypoint.
``psci_warmboot_entrypoint()`` is the warm boot entrypoint procedure.
During the warm bootup process, secondary CPUs have their secure context
diff --git a/docs/components/xlat-tables-lib-v2-design.rst b/docs/components/xlat-tables-lib-v2-design.rst
index cac32f5..c7fd5a2 100644
--- a/docs/components/xlat-tables-lib-v2-design.rst
+++ b/docs/components/xlat-tables-lib-v2-design.rst
@@ -10,7 +10,7 @@
More specifically, some use cases that this library aims to support are:
#. Statically allocate translation tables and populate them (at run-time) based
- upon a description of the memory layout. The memory layout is typically
+ on a description of the memory layout. The memory layout is typically
provided by the platform port as a list of memory regions;
#. Support for generating translation tables pertaining to a different
@@ -26,28 +26,22 @@
#. Support for changing memory attributes of memory regions at run-time.
-About version 1, version 2 and MPU libraries
---------------------------------------------
+About version 1 and version 2
+-----------------------------
This document focuses on version 2 of the library, whose sources are available
in the ``lib/xlat_tables_v2`` directory. Version 1 of the library can still be
found in ``lib/xlat_tables`` directory but it is less flexible and doesn't
-support dynamic mapping. ``lib/xlat_mpu``, which configures Arm's MPU
-equivalently, is also addressed here. The ``lib/xlat_mpu`` is experimental,
-meaning that its API may change. It currently strives for consistency and
-code-reuse with xlat_tables_v2. Future versions may be more MPU-specific (e.g.,
-removing all mentions of virtual addresses). Although potential bug fixes will
-be applied to all versions of the xlat_* libs, future feature enhancements will
-focus on version 2 and might not be back-ported to version 1 and MPU versions.
-Therefore, it is recommended to use version 2, especially for new platform
-ports (unless the platform uses an MPU).
+support dynamic mapping. Although potential bug fixes will be applied to both
+versions, future features enhancements will focus on version 2 and might not be
+back-ported to version 1. Therefore, it is recommended to use version 2,
+especially for new platform ports.
-However, please note that version 2 and the MPU version are still in active
-development and is not considered stable yet. Hence, compatibility breaks might
-be introduced.
+However, please note that version 2 is still in active development and is not
+considered stable yet. Hence, compatibility breaks might be introduced.
From this point onwards, this document will implicitly refer to version 2 of the
-library, unless stated otherwise.
+library.
Design concepts and interfaces
@@ -108,16 +102,6 @@
library will choose the mapping granularity for this region as it sees fit (more
details can be found in `The memory mapping algorithm`_ section below).
-The MPU library also uses ``struct mmap_region`` to specify translations, but
-the MPU's translations are limited to specification of valid addresses and
-access permissions. If the requested virtual and physical addresses mismatch
-the system will panic. Being register-based for deterministic memory-reference
-timing, the MPU hardware does not involve memory-resident translation tables.
-
-Currently, the MPU library is also limited to MPU translation at EL2 with no
-MMU translation at other ELs. These limitations, however, are expected to be
-overcome in future library versions.
-
Translation Context
~~~~~~~~~~~~~~~~~~~
@@ -231,8 +215,7 @@
The ``MAP_REGION()`` and ``MAP_REGION_FLAT()`` macros do not allow specifying a
mapping granularity, which leaves the library implementation free to choose
it. However, in cases where a specific granularity is required, the
-``MAP_REGION2()`` macro might be used instead. Using ``MAP_REGION_FLAT()`` only
-to define regions for the MPU library is strongly recommended.
+``MAP_REGION2()`` macro might be used instead.
As explained earlier in this document, when the dynamic mapping feature is
disabled, there is no notion of dynamic regions. Conceptually, there are only
@@ -391,9 +374,6 @@
refer to the comments in the source code of the core module for more details
about the sorting algorithm in use.
-This mapping algorithm does not apply to the MPU library, since the MPU hardware
-directly maps regions by "base" and "limit" (bottom and top) addresses.
-
TLB maintenance operations
~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -410,11 +390,6 @@
is deferred to the ``enable_mmu*()`` family of functions, just before the MMU is
turned on.
-Regarding enabling and disabling memory management, for the MPU library, to
-reduce confusion, calls to enable or disable the MPU use ``mpu`` in their names
-in place of ``mmu``. For example, the ``enable_mmu_el2()`` call is changed to
-``enable_mpu_el2()``.
-
TLB invalidation is not required when adding dynamic regions either. Dynamic
regions are not allowed to overlap existing memory region. Therefore, if the
dynamic mapping request is deemed legitimate, it automatically concerns memory
@@ -437,6 +412,6 @@
--------------
-*Copyright (c) 2017-2021, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.*
.. |Alignment Example| image:: ../resources/diagrams/xlat_align.png
diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst
index cf8cbc7..1306ecb 100644
--- a/docs/design/firmware-design.rst
+++ b/docs/design/firmware-design.rst
@@ -2599,6 +2599,9 @@
section section can be reclaimed for any data which is accessed after cold
boot initialization and it is upto the platform to make the decision.
+Please note that this will disable inlining for any functions with the __init
+attribute.
+
.. _firmware_design_pmf:
Performance Measurement Framework
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index a043991..da7a2c3 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -27,7 +27,7 @@
Program Min supported version
======================== =====================
Arm Compiler 6.23
-Arm GNU Compiler 13.3
+Arm GNU Compiler 14.2
Clang/LLVM 18.1.8
Device Tree Compiler 1.6.1
GNU make 3.81
@@ -51,7 +51,7 @@
AArch64 builds, the respective targets required are ``arm-none-eabi`` and
``aarch64-none-elf``.
-Testing has been performed with version 13.3.Rel1 (gcc 13.3) of the Arm
+Testing has been performed with version 14.2.Rel1 (GCC 14.2) of the Arm
GNU compiler, which can be installed from the `Arm Developer website`_.
In addition, a native compiler is required to build supporting tools.
diff --git a/docs/plat/arm/fvp/fvp-support.rst b/docs/plat/arm/fvp/fvp-support.rst
index 0ce1905..9535005 100644
--- a/docs/plat/arm/fvp/fvp-support.rst
+++ b/docs/plat/arm/fvp/fvp-support.rst
@@ -1,8 +1,16 @@
Fixed Virtual Platform (FVP) Support
------------------------------------
-This section lists the supported Arm |FVP| platforms. Please refer to the FVP
-documentation for a detailed description of the model parameter options.
+An |FVP| provides a complete simulation of an Arm system. This is a generic term
+used for all kinds of vastly different and incompatible systems. One category of
+these systems are the ``FVP_Base`` family of FVPs. These are entirely virtual
+platforms, largely used for early feature development. They offer a large
+degrees of customisation but share a lot of similarities. The ``fvp`` platform
+in TF-A supports these platforms only. Despite the generic name, other FVPs (eg
+FVP_TC4) have their own dedicated TF-A platforms and will not work with this one.
+
+Please refer to each FVP's documentation for a detailed description of the model
+parameter options.
The latest version of the AArch64 build of TF-A has been tested on the following
Arm FVPs without shifted affinities, and that do not support threaded CPU cores
@@ -41,9 +49,6 @@
- ``FVP_Base_Neoverse-N1``
- ``FVP_Base_Neoverse-N2``
- ``FVP_Base_Neoverse-V1``
-- ``FVP_BaseR_AEMv8R``
-- ``FVP_RD_1_AE``
-- ``FVP_TC4``
The latest version of the AArch32 build of TF-A has been tested on the
following Arm FVPs without shifted affinities, and that do not support threaded
@@ -58,9 +63,8 @@
is not compatible with legacy GIC configurations. Therefore this FVP does not
support these legacy GIC configurations.
-The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm
-FVP website`_. The Cortex-A models listed above are also available to download
-from `Arm's website`_.
+The *Foundation* and *Base* FVPs can be downloaded free of charge. See the
+`Arm's website`_ for download options of all FVPs.
.. note::
The build numbers quoted above are those reported by launching the FVP
@@ -94,7 +98,5 @@
*Copyright (c) 2019-2025, Arm Limited. All rights reserved.*
-.. _Arm's website: `FVP models`_
-.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
+.. _Arm's website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
.. _Linaro Release 20.01: http://releases.linaro.org/members/arm/platforms/20.01
-.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index 768a437..d0d6889 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -64,8 +64,6 @@
currently have associated documentation:
- Arm Neoverse N1 System Development Platform (N1SDP)
- - Arm Neoverse Reference Design N1 Edge (RD-N1-Edge) FVP
- - Arm SGI-575
- MediaTek MT8173 SoCs
Deprecated platforms
@@ -80,6 +78,18 @@
| fvp_r | Arm | 2.13 | 2.13 |
| | | | |
+----------------+----------------+--------------------+--------------------+
+| SGI-575 | Arm | 2.13 | 2.13 |
+| | | | |
++----------------+----------------+--------------------+--------------------+
+| RD-N1-Edge | Arm | 2.13 | 2.13 |
+| | | | |
++----------------+----------------+--------------------+--------------------+
+| RD-V1 | Arm | 2.13 | 2.13 |
+| | | | |
++----------------+----------------+--------------------+--------------------+
+| RD-V1-MC | Arm | 2.13 | 2.13 |
+| | | | |
++----------------+----------------+--------------------+--------------------+
--------------
diff --git a/drivers/auth/tbbr/tbbr_cot_bl1_r64.c b/drivers/auth/tbbr/tbbr_cot_bl1_r64.c
deleted file mode 100644
index 236823a..0000000
--- a/drivers/auth/tbbr/tbbr_cot_bl1_r64.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <stddef.h>
-
-#include <mbedtls/version.h>
-
-#include <drivers/auth/auth_mod.h>
-#include <drivers/auth/tbbr_cot_common.h>
-
-#if USE_TBBR_DEFS
-#include <tools_share/tbbr_oid.h>
-#else
-#include <platform_oid.h>
-#endif
-
-#include <platform_def.h>
-
-static unsigned char trusted_world_pk_buf[PK_DER_LEN];
-static unsigned char non_trusted_world_pk_buf[PK_DER_LEN];
-static unsigned char content_pk_buf[PK_DER_LEN];
-static unsigned char nt_fw_config_hash_buf[HASH_DER_LEN];
-
-static auth_param_type_desc_t non_trusted_nv_ctr = AUTH_PARAM_TYPE_DESC(
- AUTH_PARAM_NV_CTR, NON_TRUSTED_FW_NVCOUNTER_OID);
-static auth_param_type_desc_t trusted_world_pk = AUTH_PARAM_TYPE_DESC(
- AUTH_PARAM_PUB_KEY, TRUSTED_WORLD_PK_OID);
-static auth_param_type_desc_t non_trusted_world_pk = AUTH_PARAM_TYPE_DESC(
- AUTH_PARAM_PUB_KEY, NON_TRUSTED_WORLD_PK_OID);
-static auth_param_type_desc_t nt_fw_content_pk = AUTH_PARAM_TYPE_DESC(
- AUTH_PARAM_PUB_KEY, NON_TRUSTED_FW_CONTENT_CERT_PK_OID);
-static auth_param_type_desc_t nt_world_bl_hash = AUTH_PARAM_TYPE_DESC(
- AUTH_PARAM_HASH, NON_TRUSTED_WORLD_BOOTLOADER_HASH_OID);
-static auth_param_type_desc_t nt_fw_config_hash = AUTH_PARAM_TYPE_DESC(
- AUTH_PARAM_HASH, NON_TRUSTED_FW_CONFIG_HASH_OID);
-/*
- * Trusted key certificate
- */
-static const auth_img_desc_t trusted_key_cert = {
- .img_id = TRUSTED_KEY_CERT_ID,
- .img_type = IMG_CERT,
- .parent = NULL,
- .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
- [0] = {
- .type = AUTH_METHOD_SIG,
- .param.sig = {
- .pk = &subject_pk,
- .sig = &sig,
- .alg = &sig_alg,
- .data = &raw_data
- }
- },
- [1] = {
- .type = AUTH_METHOD_NV_CTR,
- .param.nv_ctr = {
- .cert_nv_ctr = &trusted_nv_ctr,
- .plat_nv_ctr = &trusted_nv_ctr
- }
- }
- },
- .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
- [0] = {
- .type_desc = &trusted_world_pk,
- .data = {
- .ptr = (void *)trusted_world_pk_buf,
- .len = (unsigned int)PK_DER_LEN
- }
- },
- [1] = {
- .type_desc = &non_trusted_world_pk,
- .data = {
- .ptr = (void *)non_trusted_world_pk_buf,
- .len = (unsigned int)PK_DER_LEN
- }
- }
- }
-};
-/*
- * Non-Trusted Firmware
- */
-static const auth_img_desc_t non_trusted_fw_key_cert = {
- .img_id = NON_TRUSTED_FW_KEY_CERT_ID,
- .img_type = IMG_CERT,
- .parent = &trusted_key_cert,
- .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
- [0] = {
- .type = AUTH_METHOD_SIG,
- .param.sig = {
- .pk = &non_trusted_world_pk,
- .sig = &sig,
- .alg = &sig_alg,
- .data = &raw_data
- }
- },
- [1] = {
- .type = AUTH_METHOD_NV_CTR,
- .param.nv_ctr = {
- .cert_nv_ctr = &non_trusted_nv_ctr,
- .plat_nv_ctr = &non_trusted_nv_ctr
- }
- }
- },
- .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
- [0] = {
- .type_desc = &nt_fw_content_pk,
- .data = {
- .ptr = (void *)content_pk_buf,
- .len = (unsigned int)PK_DER_LEN
- }
- }
- }
-};
-static const auth_img_desc_t non_trusted_fw_content_cert = {
- .img_id = NON_TRUSTED_FW_CONTENT_CERT_ID,
- .img_type = IMG_CERT,
- .parent = &non_trusted_fw_key_cert,
- .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
- [0] = {
- .type = AUTH_METHOD_SIG,
- .param.sig = {
- .pk = &nt_fw_content_pk,
- .sig = &sig,
- .alg = &sig_alg,
- .data = &raw_data
- }
- },
- [1] = {
- .type = AUTH_METHOD_NV_CTR,
- .param.nv_ctr = {
- .cert_nv_ctr = &non_trusted_nv_ctr,
- .plat_nv_ctr = &non_trusted_nv_ctr
- }
- }
- },
- .authenticated_data = (const auth_param_desc_t[COT_MAX_VERIFIED_PARAMS]) {
- [0] = {
- .type_desc = &nt_world_bl_hash,
- .data = {
- .ptr = (void *)nt_world_bl_hash_buf,
- .len = (unsigned int)HASH_DER_LEN
- }
- },
- [1] = {
- .type_desc = &nt_fw_config_hash,
- .data = {
- .ptr = (void *)nt_fw_config_hash_buf,
- .len = (unsigned int)HASH_DER_LEN
- }
- }
- }
-};
-static const auth_img_desc_t bl33_image = {
- .img_id = BL33_IMAGE_ID,
- .img_type = IMG_RAW,
- .parent = &non_trusted_fw_content_cert,
- .img_auth_methods = (const auth_method_desc_t[AUTH_METHOD_NUM]) {
- [0] = {
- .type = AUTH_METHOD_HASH,
- .param.hash = {
- .data = &raw_data,
- .hash = &nt_world_bl_hash
- }
- }
- }
-};
-
-static const auth_img_desc_t * const cot_desc[] = {
- [TRUSTED_KEY_CERT_ID] = &trusted_key_cert,
- [NON_TRUSTED_FW_KEY_CERT_ID] = &non_trusted_fw_key_cert,
- [NON_TRUSTED_FW_CONTENT_CERT_ID] = &non_trusted_fw_content_cert,
- [BL33_IMAGE_ID] = &bl33_image,
-};
-
-/* Register the CoT in the authentication module */
-REGISTER_COT(cot_desc);
diff --git a/drivers/measured_boot/event_log/event_print.c b/drivers/measured_boot/event_log/event_print.c
index e2ba174..1390427 100644
--- a/drivers/measured_boot/event_log/event_print.c
+++ b/drivers/measured_boot/event_log/event_print.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,7 +18,7 @@
* @param[in/out] log_addr Pointer to Event Log
* @param[in/out] log_size Pointer to Event Log size
*/
-static void id_event_print(uint8_t **log_addr, size_t *log_size)
+static void event_log_print_id_event(uint8_t **log_addr, size_t *log_size)
{
unsigned int i;
uint8_t info_size, *info_size_ptr;
@@ -148,7 +148,7 @@
* @param[in/out] log_addr Pointer to Event Log
* @param[in/out] log_size Pointer to Event Log size
*/
-static void event2_print(uint8_t **log_addr, size_t *log_size)
+static void event_log_print_pcr_event2(uint8_t **log_addr, size_t *log_size)
{
uint32_t event_size, count;
size_t sha_size, digests_size = 0U;
@@ -250,16 +250,16 @@
* @param[in] log_addr Pointer to Event Log
* @param[in] log_size Event Log size
*/
-void dump_event_log(uint8_t *log_addr, size_t log_size)
+void event_log_dump(uint8_t *log_addr, size_t log_size)
{
#if LOG_LEVEL >= EVENT_LOG_LEVEL
assert(log_addr != NULL);
/* Print TCG_EfiSpecIDEvent */
- id_event_print(&log_addr, &log_size);
+ event_log_print_id_event(&log_addr, &log_size);
while (log_size != 0U) {
- event2_print(&log_addr, &log_size);
+ event_log_print_pcr_event2(&log_addr, &log_size);
}
#endif
}
diff --git a/drivers/partition/partition.c b/drivers/partition/partition.c
index 387469c..564d29d 100644
--- a/drivers/partition/partition.c
+++ b/drivers/partition/partition.c
@@ -75,11 +75,6 @@
memcpy(&tmp, mbr_sector + MBR_PRIMARY_ENTRY_OFFSET, sizeof(tmp));
- if (tmp.first_lba != 1) {
- VERBOSE("MBR header may have an invalid first LBA\n");
- return -EINVAL;
- }
-
if ((tmp.sector_nums == 0) || (tmp.sector_nums == UINT32_MAX)) {
VERBOSE("MBR header entry has an invalid number of sectors\n");
return -EINVAL;
@@ -421,6 +416,11 @@
goto out;
}
if (mbr_entry.type == PARTITION_TYPE_GPT) {
+ if (mbr_entry.first_lba != 1U) {
+ VERBOSE("MBR header may have an invalid first LBA\n");
+ return -EINVAL;
+ }
+
result = load_primary_gpt(image_handle, mbr_entry.first_lba);
if (result != 0) {
io_close(image_handle);
diff --git a/drivers/ti/ipc/mailbox.c b/drivers/ti/ipc/mailbox.c
new file mode 100644
index 0000000..65458a5
--- /dev/null
+++ b/drivers/ti/ipc/mailbox.c
@@ -0,0 +1,145 @@
+/*
+ * Texas Instruments Mailbox Driver
+ *
+ * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <errno.h>
+#include <stdlib.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/utils.h>
+#include <lib/utils_def.h>
+#include <ti_sci_transport.h>
+
+#include <platform_def.h>
+
+/*
+ * TI_MAILBOX_RX/TX_BASE and the MAILBOX_MAX_MESSAGE_SIZE values are expected
+ * to come from platform specific header file ie. platform_def.h
+ */
+
+#define TI_MAILBOX_SYSC UL(0x10)
+#define TI_MAILBOX_MSG UL(0x40)
+#define TI_MAILBOX_FIFO_STATUS UL(0x80)
+#define TI_MAILBOX_MSG_STATUS UL(0xc0)
+
+/*
+ * Function to poll for mailbox rx messages
+ * IRQ model is currently not in scope of this driver
+ */
+static int8_t ti_mailbox_poll_rx_status(void)
+{
+ uint32_t num_messages_pending = 0U;
+ uint32_t retry_count = 100U;
+
+ /*
+ * Keep polling till we get a message for 100 times
+ * with intervals of 10 milliseconds.
+ */
+ while (num_messages_pending == 0U) {
+ num_messages_pending = mmio_read_32(TI_MAILBOX_RX_BASE + TI_MAILBOX_MSG_STATUS);
+ if (retry_count-- == 0U) {
+ return -ETIMEDOUT;
+ }
+ mdelay(10);
+ }
+ return 0;
+}
+
+int ti_sci_transport_clear_rx_thread(enum ti_sci_transport_chan_id id)
+{
+ /* MSG_STATUS tells us how many pending messages */
+ uint32_t try_count = mmio_read_32(TI_MAILBOX_RX_BASE + TI_MAILBOX_MSG_STATUS);
+
+ /* Run the loop till the status register is cleared */
+ while (mmio_read_32(TI_MAILBOX_RX_BASE + TI_MAILBOX_MSG_STATUS) != 0U) {
+ WARN("Clearing message from mailbox FIFO\n");
+ /* The act of reading the mailbox msg itself clears it */
+ mmio_read_32(TI_MAILBOX_RX_BASE + TI_MAILBOX_MSG);
+ /*
+ * The try_count is kept independent of the value of the status register
+ * because if at any point a new mailbox message arrives while this loop
+ * is in progress, we would want to know that message arrived and not clear
+ * it. We would rather print the error than clear the message thus indicating
+ * that the system is probably in a bad/async state.
+ */
+ if (!(try_count--)) {
+ ERROR("Could not clear all messages from mailbox FIFO\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+int ti_sci_transport_send(enum ti_sci_transport_chan_id id, const struct ti_sci_msg *msg)
+{
+ uint32_t num_bytes;
+ void *dst_ptr = (void *)MAILBOX_TX_START_REGION;
+
+ assert(msg != NULL);
+
+ num_bytes = msg->len;
+
+ /*
+ * Only a simple check because even if there's 1 pending message
+ * we will be in a bad state if we try to send another message
+ * due to the absence of any interrupt or buffer mgmt model.
+ */
+ if (mmio_read_32(TI_MAILBOX_TX_BASE + TI_MAILBOX_FIFO_STATUS)) {
+ ERROR("Mailbox FIFO has pending messages!\n");
+ return -EINVAL;
+ }
+
+ if (num_bytes > MAILBOX_MAX_MESSAGE_SIZE) {
+ ERROR("message length %lu > max msg size\n", msg->len);
+ return -EINVAL;
+ }
+
+ /*
+ * Move the buffer contents into the SRAM to be accessed by TIFS
+ */
+ memmove(dst_ptr, msg->buf, num_bytes);
+
+ mmio_write_32(TI_MAILBOX_TX_BASE + TI_MAILBOX_MSG, (uint64_t)(void *)dst_ptr);
+
+ return 0;
+}
+
+int ti_sci_transport_recv(enum ti_sci_transport_chan_id id, struct ti_sci_msg *msg)
+{
+ uint32_t num_bytes;
+ uint64_t rcv_addr;
+
+ assert(msg != NULL);
+
+ num_bytes = msg->len;
+
+ if (ti_mailbox_poll_rx_status() == -ETIMEDOUT) {
+ ERROR("Timeout waiting for receive\n");
+ return -ETIMEDOUT;
+ }
+
+ rcv_addr = mmio_read_32(TI_MAILBOX_RX_BASE + TI_MAILBOX_MSG);
+
+ if (rcv_addr != MAILBOX_RX_START_REGION) {
+ ERROR("message address %lu is not valid\n", rcv_addr);
+ return -EINVAL;
+ }
+
+ if (num_bytes > MAILBOX_MAX_MESSAGE_SIZE) {
+ ERROR("message length %lu > max msg size\n", msg->len);
+ return -EINVAL;
+ }
+
+ memmove(msg->buf, (uint8_t *)(rcv_addr), num_bytes);
+
+ return 0;
+}
diff --git a/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c b/drivers/ti/ipc/sec_proxy.c
similarity index 83%
rename from plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c
rename to drivers/ti/ipc/sec_proxy.c
index fb27336..55396f6 100644
--- a/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.c
+++ b/drivers/ti/ipc/sec_proxy.c
@@ -2,7 +2,7 @@
* Texas Instruments K3 Secure Proxy Driver
* Based on Linux and U-Boot implementation
*
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2018-2025 Texas Instruments Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,7 +18,7 @@
#include <lib/utils.h>
#include <lib/utils_def.h>
-#include "sec_proxy.h"
+#include <ti_sci_transport.h>
/* SEC PROXY RT THREAD STATUS */
#define RT_THREAD_STATUS (0x0)
@@ -97,32 +97,12 @@
.data_end_offset = 0x3C,
},
.threads = {
-#if !K3_SEC_PROXY_LITE
- SP_THREAD(SP_NOTIFY),
- SP_THREAD(SP_RESPONSE),
- SP_THREAD(SP_HIGH_PRIORITY),
- SP_THREAD(SP_LOW_PRIORITY),
- SP_THREAD(SP_NOTIFY_RESP),
-#else
- SP_THREAD(SP_RESPONSE),
- SP_THREAD(SP_HIGH_PRIORITY),
-#endif /* K3_SEC_PROXY_LITE */
+ SP_THREAD(RX_SECURE_TRANSPORT_CHANNEL_ID),
+ SP_THREAD(TX_SECURE_TRANSPORT_CHANNEL_ID),
},
};
/**
- * struct sec_msg_hdr - Message header for secure messages and responses
- * @checksum: CRC of message for integrity checking
- */
-union sec_msg_hdr {
- struct {
- uint16_t checksum;
- uint16_t reserved;
- } __packed;
- uint32_t data;
-};
-
-/**
* k3_sec_proxy_verify_thread() - Verify thread status before
* sending/receiving data
* @spt: Pointer to Secure Proxy thread description
@@ -170,13 +150,13 @@
}
/**
- * k3_sec_proxy_clear_rx_thread() - Clear Secure Proxy thread
+ * ti_sci_transport_clear_rx_thread() - Clear Secure Proxy thread
*
* @id: Channel Identifier
*
* Return: 0 if all goes well, else appropriate error message
*/
-int k3_sec_proxy_clear_rx_thread(enum k3_sec_proxy_chan_id id)
+int ti_sci_transport_clear_rx_thread(enum ti_sci_transport_chan_id id)
{
struct k3_sec_proxy_thread *spt = &spm.threads[id];
@@ -208,16 +188,15 @@
}
/**
- * k3_sec_proxy_send() - Send data over a Secure Proxy thread
+ * ti_sci_transport_send() - Send data over a Secure Proxy thread
* @id: Channel Identifier
- * @msg: Pointer to k3_sec_proxy_msg
+ * @msg: Pointer to ti_sci_msg
*
* Return: 0 if all goes well, else appropriate error message
*/
-int k3_sec_proxy_send(enum k3_sec_proxy_chan_id id, const struct k3_sec_proxy_msg *msg)
+int ti_sci_transport_send(enum ti_sci_transport_chan_id id, const struct ti_sci_msg *msg)
{
struct k3_sec_proxy_thread *spt = &spm.threads[id];
- union sec_msg_hdr secure_header;
int num_words, trail_bytes, i, ret;
uintptr_t data_reg;
@@ -228,19 +207,13 @@
}
/* Check the message size */
- if (msg->len + sizeof(secure_header) > spm.desc.max_msg_size) {
+ if (msg->len > spm.desc.max_msg_size) {
ERROR("Thread %s message length %lu > max msg size\n",
spt->name, msg->len);
return -EINVAL;
}
- /* TODO: Calculate checksum */
- secure_header.checksum = 0;
-
- /* Send the secure header */
data_reg = spm.desc.data_start_offset;
- mmio_write_32(spt->data + data_reg, secure_header.data);
- data_reg += sizeof(uint32_t);
/* Send whole words */
num_words = msg->len / sizeof(uint32_t);
@@ -281,16 +254,15 @@
}
/**
- * k3_sec_proxy_recv() - Receive data from a Secure Proxy thread
+ * ti_sci_transport_recv() - Receive data from a Secure Proxy thread
* @id: Channel Identifier
- * @msg: Pointer to k3_sec_proxy_msg
+ * @msg: Pointer to ti_sci_msg
*
* Return: 0 if all goes well, else appropriate error message
*/
-int k3_sec_proxy_recv(enum k3_sec_proxy_chan_id id, struct k3_sec_proxy_msg *msg)
+int ti_sci_transport_recv(enum ti_sci_transport_chan_id id, struct ti_sci_msg *msg)
{
struct k3_sec_proxy_thread *spt = &spm.threads[id];
- union sec_msg_hdr secure_header;
uintptr_t data_reg;
int num_words, trail_bytes, i, ret;
@@ -300,10 +272,7 @@
return ret;
}
- /* Read secure header */
data_reg = spm.desc.data_start_offset;
- secure_header.data = mmio_read_32(spt->data + data_reg);
- data_reg += sizeof(uint32_t);
/* Read whole words */
num_words = msg->len / sizeof(uint32_t);
@@ -332,9 +301,6 @@
if (data_reg <= spm.desc.data_end_offset)
mmio_read_32(spt->data + spm.desc.data_end_offset);
- /* TODO: Verify checksum */
- (void)secure_header.checksum;
-
VERBOSE("Message successfully received from thread %s\n", spt->name);
return 0;
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c b/drivers/ti/ti_sci/ti_sci.c
similarity index 98%
rename from plat/ti/k3/common/drivers/ti_sci/ti_sci.c
rename to drivers/ti/ti_sci/ti_sci.c
index 5c6ba6b..f0813e5 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
+++ b/drivers/ti/ti_sci/ti_sci.c
@@ -2,7 +2,7 @@
* Texas Instruments System Control Interface Driver
* Based on Linux and U-Boot implementation
*
- * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,7 +16,7 @@
#include <lib/bakery_lock.h>
#include <common/debug.h>
-#include <sec_proxy.h>
+#include <ti_sci_transport.h>
#include "ti_sci_protocol.h"
#include "ti_sci.h"
@@ -34,8 +34,8 @@
* @rx_message: Receive message
*/
struct ti_sci_xfer {
- struct k3_sec_proxy_msg tx_message;
- struct k3_sec_proxy_msg rx_message;
+ struct ti_sci_msg tx_message;
+ struct ti_sci_msg rx_message;
};
/**
@@ -69,6 +69,9 @@
return -ERANGE;
hdr = (struct ti_sci_msg_hdr *)tx_buf;
+
+ /* TODO: Calculate checksum */
+ hdr->sec_hdr.checksum = 0;
hdr->seq = ++message_sequence;
hdr->type = msg_type;
hdr->host = TI_SCI_HOST_ID;
@@ -95,8 +98,8 @@
*
* Return: 0 if all goes well, else appropriate error message
*/
-static int ti_sci_get_response(struct k3_sec_proxy_msg *msg,
- enum k3_sec_proxy_chan_id chan)
+static int ti_sci_get_response(struct ti_sci_msg *msg,
+ enum ti_sci_transport_chan_id chan)
{
struct ti_sci_msg_hdr *hdr;
unsigned int retry = 5;
@@ -104,7 +107,7 @@
for (; retry > 0; retry--) {
/* Receive the response */
- ret = k3_sec_proxy_recv(chan, msg);
+ ret = ti_sci_transport_recv(chan, msg);
if (ret) {
ERROR("Message receive failed (%d)\n", ret);
return ret;
@@ -133,6 +136,9 @@
if (!(hdr->flags & TI_SCI_FLAG_RESP_GENERIC_ACK))
return -ENODEV;
+ /* TODO: Verify checksum */
+ (void)hdr->sec_hdr.checksum;
+
return 0;
}
@@ -145,21 +151,21 @@
*/
static int ti_sci_do_xfer(struct ti_sci_xfer *xfer)
{
- struct k3_sec_proxy_msg *tx_msg = &xfer->tx_message;
- struct k3_sec_proxy_msg *rx_msg = &xfer->rx_message;
+ struct ti_sci_msg *tx_msg = &xfer->tx_message;
+ struct ti_sci_msg *rx_msg = &xfer->rx_message;
int ret;
bakery_lock_get(&ti_sci_xfer_lock);
/* Clear any spurious messages in receive queue */
- ret = k3_sec_proxy_clear_rx_thread(SP_RESPONSE);
+ ret = ti_sci_transport_clear_rx_thread(RX_SECURE_TRANSPORT_CHANNEL_ID);
if (ret) {
ERROR("Could not clear response queue (%d)\n", ret);
goto unlock;
}
/* Send the message */
- ret = k3_sec_proxy_send(SP_HIGH_PRIORITY, tx_msg);
+ ret = ti_sci_transport_send(TX_SECURE_TRANSPORT_CHANNEL_ID, tx_msg);
if (ret) {
ERROR("Message sending failed (%d)\n", ret);
goto unlock;
@@ -167,7 +173,7 @@
/* Get the response if requested */
if (rx_msg->len != 0U) {
- ret = ti_sci_get_response(rx_msg, SP_RESPONSE);
+ ret = ti_sci_get_response(rx_msg, RX_SECURE_TRANSPORT_CHANNEL_ID);
if (ret != 0U) {
ERROR("Failed to get response (%d)\n", ret);
goto unlock;
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.h b/drivers/ti/ti_sci/ti_sci.h
similarity index 99%
rename from plat/ti/k3/common/drivers/ti_sci/ti_sci.h
rename to drivers/ti/ti_sci/ti_sci.h
index 06d1f8d..1f19632 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.h
+++ b/drivers/ti/ti_sci/ti_sci.h
@@ -2,7 +2,7 @@
* Texas Instruments System Control Interface API
* Based on Linux and U-Boot implementation
*
- * Copyright (C) 2018-2024 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/
*
* SPDX-License-Identifier: BSD-3-Clause
*/
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h b/drivers/ti/ti_sci/ti_sci_protocol.h
similarity index 98%
rename from plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
rename to drivers/ti/ti_sci/ti_sci_protocol.h
index cc71eac..bdd2462 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
+++ b/drivers/ti/ti_sci/ti_sci_protocol.h
@@ -5,7 +5,7 @@
* The system works in a message response protocol
* See: http://processors.wiki.ti.com/index.php/TISCI for details
*
- * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2018-2025 Texas Instruments Incorporated - https://www.ti.com/
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -54,6 +54,17 @@
#define TISCI_MSG_WAIT_PROC_BOOT_STATUS 0xc401
/**
+ * struct ti_sci_secure_msg_hdr - Header that prefixes all TISCI messages sent
+ * via secure transport.
+ * @checksum: crc16 checksum for the entire message
+ * @reserved: Reserved for future use.
+ */
+struct ti_sci_secure_msg_hdr {
+ uint16_t checksum;
+ uint16_t reserved;
+} __packed;
+
+/**
* struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
* @type: Type of messages: One of TI_SCI_MSG* values
* @host: Host of the message
@@ -61,6 +72,7 @@
* @flags: Flag for the message
*/
struct ti_sci_msg_hdr {
+ struct ti_sci_secure_msg_hdr sec_hdr;
uint16_t type;
uint8_t host;
uint8_t seq;
diff --git a/drivers/ti/ti_sci/ti_sci_transport.h b/drivers/ti/ti_sci/ti_sci_transport.h
new file mode 100644
index 0000000..13d0fb5
--- /dev/null
+++ b/drivers/ti/ti_sci/ti_sci_transport.h
@@ -0,0 +1,74 @@
+/*
+ * Texas Instruments SCI Transport Protocol Header
+ *
+ * Copyright (C) 2018-2025 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TI_SCI_TRANSPORT_H
+#define TI_SCI_TRANSPORT_H
+
+#include <stdint.h>
+
+/**
+ * enum ti_sci_transport_chan_id - Secure Proxy thread IDs
+ *
+ * These are the available IDs used in ti_sci_transport_{send,recv}()
+ */
+enum ti_sci_transport_chan_id {
+#if !K3_SEC_PROXY_LITE
+ RX_SECURE_TRANSPORT_CHANNEL_ID = 1,
+ TX_SECURE_TRANSPORT_CHANNEL_ID,
+#else
+ RX_SECURE_TRANSPORT_CHANNEL_ID = 8,
+ /*
+ * Note: TISCI documentation indicates "low priority", but in reality
+ * with a single thread, there is no low or high priority.. This usage
+ * is more appropriate for TF-A since we can reduce the churn as a
+ * result.
+ */
+ TX_SECURE_TRANSPORT_CHANNEL_ID,
+#endif /* K3_SEC_PROXY_LITE */
+};
+
+/**
+ * struct ti_sci_msg - Secure proxy message structure
+ * @len: Length of data in the Buffer
+ * @buf: Buffer pointer
+ *
+ * This is the structure for data used in ti_sci_transport_{send,recv}()
+ */
+struct ti_sci_msg {
+ size_t len;
+ uint8_t *buf;
+};
+
+/**
+ * ti_sci_transport_clear_rx_thread() - Clear a receive Secure Proxy thread
+ * @id: Channel Identifier
+ * @msg: Pointer to ti_sci_msg
+ *
+ * Return: 0 if all goes well, else appropriate error message
+ */
+int ti_sci_transport_clear_rx_thread(enum ti_sci_transport_chan_id id);
+
+/**
+ * ti_sci_transport_send() - Send data over mailbox/ Secure Proxy thread
+ * @id: Channel Identifier
+ * @msg: Pointer to ti_sci_msg
+ *
+ * Return: 0 if all goes well, else appropriate error message
+ */
+int ti_sci_transport_send(enum ti_sci_transport_chan_id id, const struct ti_sci_msg *msg);
+
+/**
+ * ti_sci_transport_recv() - Receive data from a Secure Proxy thread/ mailbox
+ * @id: Channel Identifier
+ * @msg: Pointer to ti_sci_msg
+ *
+ * Return: 0 if all goes well, else appropriate error message
+ */
+int ti_sci_transport_recv(enum ti_sci_transport_chan_id id, struct ti_sci_msg *msg);
+
+#endif /* TI_SCI_TRANSPORT_H */
diff --git a/fdts/stm32mp157c-lxa-tac-fw-config.dts b/fdts/stm32mp157c-lxa-tac-fw-config.dts
new file mode 100644
index 0000000..9ee09e9
--- /dev/null
+++ b/fdts/stm32mp157c-lxa-tac-fw-config.dts
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (c) 2021, STMicroelectronics - All Rights Reserved
+ */
+
+#define DDR_SIZE 0x20000000 /* 512MB */
+#include "stm32mp15-fw-config.dtsi"
diff --git a/fdts/stm32mp157c-lxa-tac.dts b/fdts/stm32mp157c-lxa-tac.dts
new file mode 100644
index 0000000..a9e894c
--- /dev/null
+++ b/fdts/stm32mp157c-lxa-tac.dts
@@ -0,0 +1,160 @@
+/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
+/*
+ * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2021 Rouven Czerwinski, Pengutronix
+ */
+
+/dts-v1/;
+
+#include "stm32mp157.dtsi"
+#include "stm32mp15xc.dtsi"
+#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
+#include "stm32mp15xx-osd32.dtsi"
+#include "stm32mp15xxac-pinctrl.dtsi"
+
+/ {
+ model = "Linux Automation Test Automation Controller (TAC)";
+ compatible = "lxa,stm32mp157c-tac", "oct,stm32mp15xx-osd32", "st,stm32mp157";
+
+ aliases {
+ mmc1 = &sdmmc2;
+ serial0 = &uart4;
+ };
+
+
+ chosen {
+ stdout-path = &uart4;
+ };
+
+ led-controller-0 {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "tac:green:user1";
+ gpios = <&gpiof 10 1>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ reg_3v3: regulator_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&v3v3>;
+ };
+};
+
+&pinctrl {
+ tac_sdmmc2_d47_pins_b: tac-sdmmc2-d47-1 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+};
+
+/* VCO = 624 MHz => P = 208, Q = 48, R = 104 */
+&pll3 {
+ st,pll = <&pll3_cfg2>;
+
+ pll3_cfg2: pll3-cfg2 {
+ st,pll_vco = <&pll3_vco_624Mhz>;
+ st,pll_div_pqr = <2 12 5>;
+ };
+};
+
+/* VCO = 750.0 MHz => P = 125, Q = 75, R = 62.5 */
+&pll4 {
+ st,pll = <&pll4_cfg2>;
+
+ pll4_cfg2: pll4-cfg2 {
+ st,pll_vco = <&pll4_vco_750Mhz>;
+ st,pll_div_pqr = <5 9 11>;
+ };
+};
+
+&rcc {
+ /* change parent clocks */
+ st,clksrc = <
+ CLK_MPU_PLL1P
+ CLK_AXI_PLL2P
+ CLK_MCU_PLL3P
+ CLK_RTC_LSE
+ CLK_MCO1_DISABLED
+ CLK_MCO2_DISABLED
+ CLK_CKPER_HSE
+ CLK_FMC_ACLK
+ CLK_QSPI_ACLK
+ CLK_ETH_PLL4P
+ CLK_SDMMC12_PLL3R
+ CLK_DSI_DSIPLL
+ CLK_STGEN_HSE
+ CLK_USBPHY_HSE
+ CLK_SPI2S1_PLL3Q
+ CLK_SPI2S23_PLL3Q
+ CLK_SPI45_HSI
+ CLK_SPI6_HSI
+ CLK_I2C46_HSI
+ CLK_SDMMC3_DISABLED
+ CLK_USBO_USBPHY
+ CLK_ADC_CKPER
+ CLK_CEC_DISABLED
+ CLK_I2C12_HSI
+ CLK_I2C35_HSI
+ CLK_UART1_HSI
+ CLK_UART24_HSI
+ CLK_UART35_HSI
+ CLK_UART6_HSI
+ CLK_UART78_HSI
+ CLK_SPDIF_DISABLED
+ CLK_FDCAN_PLL3Q
+ CLK_SAI1_DISABLED
+ CLK_SAI2_DISABLED
+ CLK_SAI3_DISABLED
+ CLK_SAI4_DISABLED
+ CLK_RNG1_LSI
+ CLK_RNG2_LSI
+ CLK_LPTIM1_PCLK1
+ CLK_LPTIM23_PCLK3
+ CLK_LPTIM45_LSE
+ >;
+
+ st,pll_vco {
+ pll3_vco_624Mhz: pll3-vco-624Mhz {
+ src = <CLK_PLL3_HSE>;
+ divmn = <1 51>;
+ };
+
+ pll4_vco_750Mhz: pll4-vco-750Mhz {
+ src = <CLK_PLL4_HSE>;
+ divmn = <3 124>;
+ };
+ };
+};
+
+&sdmmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &tac_sdmmc2_d47_pins_b>;
+ bus-width = <8>;
+ mmc-ddr-3_3v;
+ no-1-8-v;
+ no-sd;
+ no-sdio;
+ non-removable;
+ st,neg-edge;
+ vmmc-supply = <®_3v3>;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
diff --git a/include/common/feat_detect.h b/include/common/feat_detect.h
index b85e1ce..18e6c42 100644
--- a/include/common/feat_detect.h
+++ b/include/common/feat_detect.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,6 +14,5 @@
#define FEAT_STATE_DISABLED 0
#define FEAT_STATE_ALWAYS 1
#define FEAT_STATE_CHECK 2
-#define FEAT_STATE_CHECK_ASYMMETRIC 3
#endif /* FEAT_DETECT_H */
diff --git a/include/drivers/measured_boot/event_log/event_log.h b/include/drivers/measured_boot/event_log/event_log.h
index b44526a..18abadf 100644
--- a/include/drivers/measured_boot/event_log/event_log.h
+++ b/include/drivers/measured_boot/event_log/event_log.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -69,7 +69,7 @@
void event_log_init(uint8_t *event_log_start, uint8_t *event_log_finish);
void event_log_write_specid_event(void);
void event_log_write_header(void);
-void dump_event_log(uint8_t *log_addr, size_t log_size);
+void event_log_dump(uint8_t *log_addr, size_t log_size);
int event_log_measure(uintptr_t data_base, uint32_t data_size,
unsigned char hash_data[CRYPTO_MD_MAX_SIZE]);
void event_log_record(const uint8_t *hash, uint32_t event_type,
diff --git a/include/lib/cpus/errata.h b/include/lib/cpus/errata.h
index 8e28d46..1f5f5ea 100644
--- a/include/lib/cpus/errata.h
+++ b/include/lib/cpus/errata.h
@@ -67,7 +67,6 @@
}
#endif
-
bool check_if_trbe_disable_affected_core(void);
int check_wa_cve_2024_7881(void);
bool errata_ich_vmcr_el2_applies(void);
diff --git a/include/lib/el3_runtime/context_mgmt.h b/include/lib/el3_runtime/context_mgmt.h
index a48ed96..72a8ea2 100644
--- a/include/lib/el3_runtime/context_mgmt.h
+++ b/include/lib/el3_runtime/context_mgmt.h
@@ -34,17 +34,11 @@
void cm_prepare_el3_exit(uint32_t security_state);
void cm_prepare_el3_exit_ns(void);
-#if !IMAGE_BL1
-void cm_init_context_by_index(unsigned int cpu_idx,
- const struct entry_point_info *ep);
-#endif /* !IMAGE_BL1 */
-
#ifdef __aarch64__
#if IMAGE_BL31
void cm_manage_extensions_el3(unsigned int my_idx);
void manage_extensions_nonsecure_per_world(void);
void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx);
-void cm_handle_asymmetric_features(void);
#endif
#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
@@ -97,7 +91,6 @@
void cm_set_next_context(void *context);
static inline void cm_manage_extensions_el3(unsigned int cpu_idx) {}
static inline void manage_extensions_nonsecure_per_world(void) {}
-static inline void cm_handle_asymmetric_features(void) {}
#endif /* __aarch64__ */
#endif /* CONTEXT_MGMT_H */
diff --git a/include/lib/el3_runtime/cpu_data.h b/include/lib/el3_runtime/cpu_data.h
index e417f45..3dc156a 100644
--- a/include/lib/el3_runtime/cpu_data.h
+++ b/include/lib/el3_runtime/cpu_data.h
@@ -23,10 +23,10 @@
/* Size of cpu_context array */
#define CPU_DATA_CONTEXT_NUM 3
/* Offset of cpu_ops_ptr, size 8 bytes */
-#define CPU_DATA_CPU_OPS_PTR 0x18
+#define CPU_DATA_CPU_OPS_PTR 0x20
#else /* ENABLE_RME */
#define CPU_DATA_CONTEXT_NUM 2
-#define CPU_DATA_CPU_OPS_PTR 0x10
+#define CPU_DATA_CPU_OPS_PTR 0x18
#endif /* ENABLE_RME */
#if ENABLE_PAUTH
@@ -47,8 +47,9 @@
#if CRASH_REPORTING
#error "Crash reporting is not supported in AArch32"
#endif
-#define CPU_DATA_CPU_OPS_PTR 0x0
-#define CPU_DATA_CRASH_BUF_OFFSET (0x4 + PSCI_CPU_DATA_SIZE)
+#define WARMBOOT_EP_INFO 0x0
+#define CPU_DATA_CPU_OPS_PTR 0x4
+#define CPU_DATA_CRASH_BUF_OFFSET (CPU_DATA_CPU_OPS_PTR + PSCI_CPU_DATA_SIZE)
#endif /* __aarch64__ */
@@ -79,7 +80,12 @@
#if ENABLE_RUNTIME_INSTRUMENTATION
/* Temporary space to store PMF timestamps from assembly code */
#define CPU_DATA_PMF_TS_COUNT 1
+#if __aarch64__
#define CPU_DATA_PMF_TS0_OFFSET CPU_DATA_EHF_DATA_BUF_END
+#else
+/* alignment */
+#define CPU_DATA_PMF_TS0_OFFSET (CPU_DATA_EHF_DATA_BUF_END + 8)
+#endif
#define CPU_DATA_PMF_TS0_IDX 0
#endif
@@ -131,6 +137,7 @@
#ifdef __aarch64__
void *cpu_context[CPU_DATA_CONTEXT_NUM];
#endif /* __aarch64__ */
+ entry_point_info_t *warmboot_ep_info;
uintptr_t cpu_ops_ptr;
struct psci_cpu_data psci_svc_cpu_data;
#if ENABLE_PAUTH
diff --git a/include/lib/libc/cdefs.h b/include/lib/libc/cdefs.h
index 97b7824..5febe9d 100644
--- a/include/lib/libc/cdefs.h
+++ b/include/lib/libc/cdefs.h
@@ -16,12 +16,19 @@
#define __aligned(x) __attribute__((__aligned__(x)))
#define __section(x) __attribute__((__section__(x)))
#define __fallthrough __attribute__((__fallthrough__))
+#define __noinline __attribute__((__noinline__))
#if RECLAIM_INIT_CODE
/*
* Add each function to a section that is unique so the functions can still
- * be garbage collected
+ * be garbage collected.
+ *
+ * NOTICE: for this to work, these functions will NOT be inlined.
+ * TODO: the noinline attribute can be removed if RECLAIM_INIT_CODE is made
+ * platform agnostic and called after bl31_main(). Then, top-level functions
+ * (those that can't be inlined like bl31_main()) can be annotated with __init
+ * and noinline can be removed.
*/
-#define __init __section(".text.init." __FILE__ "." __XSTRING(__LINE__))
+#define __init __section(".text.init." __FILE__ "." __XSTRING(__LINE__)) __noinline
#else
#define __init
#endif
diff --git a/include/lib/libc/string.h b/include/lib/libc/string.h
index bba9816..098fded 100644
--- a/include/lib/libc/string.h
+++ b/include/lib/libc/string.h
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
- * Portions copyright (c) 2018-2020, Arm Limited and Contributors.
+ * Portions copyright (c) 2018-2025, Arm Limited and Contributors.
* Portions copyright (c) 2023, Intel Corporation. All rights reserved.
* All rights reserved.
*/
@@ -14,19 +14,26 @@
#include <stddef.h>
-void *memcpy(void *dst, const void *src, size_t len);
+/*
+ * When conditions are right, the compiler may have a baked-in call that can be
+ * inlined and that will be much more optimal than our generic implementation.
+ * When it doesn't, it will emit a call to the original function for which we
+ * provide an implementation.
+ */
+#define memcpy __builtin_memcpy
+#define memset __builtin_memset
+#define memcmp __builtin_memcmp
+#define memchr __builtin_memchr
+#define strcmp __builtin_strcmp
+#define strncmp __builtin_strncmp
+#define strchr __builtin_strchr
+#define strlen __builtin_strlen
+#define strrchr __builtin_strrchr
+
int memcpy_s(void *dst, size_t dsize, void *src, size_t ssize);
void *memmove(void *dst, const void *src, size_t len);
-int memcmp(const void *s1, const void *s2, size_t len);
-int strcmp(const char *s1, const char *s2);
-int strncmp(const char *s1, const char *s2, size_t n);
-void *memchr(const void *src, int c, size_t len);
void *memrchr(const void *src, int c, size_t len);
-char *strchr(const char *s, int c);
-void *memset(void *dst, int val, size_t count);
-size_t strlen(const char *s);
size_t strnlen(const char *s, size_t maxlen);
-char *strrchr(const char *p, int ch);
size_t strlcpy(char * dst, const char * src, size_t dsize);
size_t strlcat(char * dst, const char * src, size_t dsize);
char *strtok_r(char *s, const char *delim, char **last);
diff --git a/include/lib/libc/string_private.h b/include/lib/libc/string_private.h
new file mode 100644
index 0000000..da85fae
--- /dev/null
+++ b/include/lib/libc/string_private.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STRING_PRIVATE_H
+#define STRING_PRIVATE_H
+
+/* Do not include outside of the libc. Use string.h instead. */
+
+#include <stddef.h>
+
+int memcmp(const void *s1, const void *s2, size_t len);
+int strcmp(const char *s1, const char *s2);
+int strncmp(const char *s1, const char *s2, size_t n);
+void *memchr(const void *src, int c, size_t len);
+char *strchr(const char *s, int c);
+void *memset(void *dst, int val, size_t count);
+size_t strlen(const char *s);
+char *strrchr(const char *p, int ch);
+
+#endif /* STRING_PRIVATE_H */
diff --git a/include/lib/xlat_mpu/xlat_mpu.h b/include/lib/xlat_mpu/xlat_mpu.h
deleted file mode 100644
index 3a470ad..0000000
--- a/include/lib/xlat_mpu/xlat_mpu.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef XLAT_MPU_H
-#define XLAT_MPU_H
-
-#ifndef __ASSEMBLER__
-
-#include <lib/cassert.h>
-
-#define XLAT_TABLES_LIB_V2 1
-
-void enable_mpu_el2(unsigned int flags);
-void enable_mpu_direct_el2(unsigned int flags);
-
-/*
- * Function to wipe clean and disable all MPU regions. This function expects
- * that the MPU has already been turned off, and caching concerns addressed,
- * but it nevertheless also explicitly turns off the MPU.
- */
-void clear_all_mpu_regions(void);
-
-#endif /* __ASSEMBLER__ */
-#endif /* XLAT_MPU_H */
diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h
index faccf31..e10770c 100644
--- a/include/plat/common/platform.h
+++ b/include/plat/common/platform.h
@@ -465,13 +465,6 @@
void plat_flush_next_bl_params(void);
/*
- * The below function enable Trusted Firmware components like SPDs which
- * haven't migrated to the new platform API to compile on platforms which
- * have the compatibility layer disabled.
- */
-unsigned int platform_core_pos_helper(unsigned long mpidr);
-
-/*
* Optional function to get SOC version
*/
int32_t plat_get_soc_version(void);
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c
index 132888c..00d9c01 100644
--- a/lib/el3_runtime/aarch32/context_mgmt.c
+++ b/lib/el3_runtime/aarch32/context_mgmt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -155,21 +155,6 @@
#endif /* IMAGE_BL32 */
}
-#if !IMAGE_BL1
-/*******************************************************************************
- * The following function initializes the cpu_context for a CPU specified by
- * its `cpu_idx` for first use, and sets the initial entrypoint state as
- * specified by the entry_point_info structure.
- ******************************************************************************/
-void cm_init_context_by_index(unsigned int cpu_idx,
- const entry_point_info_t *ep)
-{
- cpu_context_t *ctx;
- ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
- cm_setup_context(ctx, ep);
-}
-#endif /* !IMAGE_BL1 */
-
/*******************************************************************************
* The following function initializes the cpu_context for the current CPU
* for first use, and sets the initial entrypoint state as specified by the
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 021d538..2d1b063 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -484,13 +484,6 @@
#endif /* CTX_INCLUDE_PAUTH_REGS */
/*
- * SCR_EL3.TCR2EN: Enable access to TCR2_ELx for AArch64 if present.
- */
- if (is_feat_tcr2_supported() && (GET_RW(ep->spsr) == MODE_RW_64)) {
- scr_el3 |= SCR_TCR2EN_BIT;
- }
-
- /*
* SCR_EL3.PIEN: Enable permission indirection and overlay
* registers for AArch64 if present.
*/
@@ -591,6 +584,10 @@
trf_enable(ctx);
}
+ if (is_feat_tcr2_supported()) {
+ tcr2_enable(ctx);
+ }
+
pmuv3_enable(ctx);
#endif /* IMAGE_BL31 */
@@ -839,8 +836,10 @@
spe_enable(ctx);
}
- if (is_feat_trbe_supported()) {
- trbe_enable(ctx);
+ if (!check_if_trbe_disable_affected_core()) {
+ if (is_feat_trbe_supported()) {
+ trbe_enable(ctx);
+ }
}
if (is_feat_brbe_supported()) {
@@ -955,21 +954,6 @@
#endif /* IMAGE_BL31 */
}
-#if !IMAGE_BL1
-/*******************************************************************************
- * The following function initializes the cpu_context for a CPU specified by
- * its `cpu_idx` for first use, and sets the initial entrypoint state as
- * specified by the entry_point_info structure.
- ******************************************************************************/
-void cm_init_context_by_index(unsigned int cpu_idx,
- const entry_point_info_t *ep)
-{
- cpu_context_t *ctx;
- ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
- cm_setup_context(ctx, ep);
-}
-#endif /* !IMAGE_BL1 */
-
/*******************************************************************************
* The following function initializes the cpu_context for the current CPU
* for first use, and sets the initial entrypoint state as specified by the
@@ -1647,52 +1631,6 @@
}
#endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
-#if IMAGE_BL31
-/*********************************************************************************
-* This function allows Architecture features asymmetry among cores.
-* TF-A assumes that all the cores in the platform has architecture feature parity
-* and hence the context is setup on different core (e.g. primary sets up the
-* context for secondary cores).This assumption may not be true for systems where
-* cores are not conforming to same Arch version or there is CPU Erratum which
-* requires certain feature to be be disabled only on a given core.
-*
-* This function is called on secondary cores to override any disparity in context
-* setup by primary, this would be called during warmboot path.
-*********************************************************************************/
-void cm_handle_asymmetric_features(void)
-{
- cpu_context_t *ctx __maybe_unused = cm_get_context(NON_SECURE);
-
- assert(ctx != NULL);
-
-#if ENABLE_SPE_FOR_NS == FEAT_STATE_CHECK_ASYMMETRIC
- if (is_feat_spe_supported()) {
- spe_enable(ctx);
- } else {
- spe_disable(ctx);
- }
-#endif
-
- if (check_if_trbe_disable_affected_core()) {
- if (is_feat_trbe_supported()) {
- trbe_disable(ctx);
- }
- }
-
-#if ENABLE_FEAT_TCR2 == FEAT_STATE_CHECK_ASYMMETRIC
- el3_state_t *el3_state = get_el3state_ctx(ctx);
- u_register_t spsr = read_ctx_reg(el3_state, CTX_SPSR_EL3);
-
- if (is_feat_tcr2_supported() && (GET_RW(spsr) == MODE_RW_64)) {
- tcr2_enable(ctx);
- } else {
- tcr2_disable(ctx);
- }
-#endif
-
-}
-#endif
-
/*******************************************************************************
* This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS
* is enabled, it restores EL1 and EL2 sysreg contexts instead of directly
@@ -1701,18 +1639,6 @@
******************************************************************************/
void cm_prepare_el3_exit_ns(void)
{
-#if IMAGE_BL31
- /*
- * Check and handle Architecture feature asymmetry among cores.
- *
- * In warmboot path secondary cores context is initialized on core which
- * did CPU_ON SMC call, if there is feature asymmetry in these cores handle
- * it in this function call.
- * For Symmetric cores this is an empty function.
- */
- cm_handle_asymmetric_features();
-#endif
-
#if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
#if ENABLE_ASSERTIONS
cpu_context_t *ctx = cm_get_context(NON_SECURE);
diff --git a/lib/libc/memchr.c b/lib/libc/memchr.c
index 66d7ba1..e009a5f 100644
--- a/lib/libc/memchr.c
+++ b/lib/libc/memchr.c
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stddef.h>
-#include <string.h>
+#include <string_private.h>
void *memchr(const void *src, int c, size_t len)
{
diff --git a/lib/libc/memcmp.c b/lib/libc/memcmp.c
index db2701b..1458208 100644
--- a/lib/libc/memcmp.c
+++ b/lib/libc/memcmp.c
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stddef.h>
-#include <string.h>
+#include <string_private.h>
int memcmp(const void *s1, const void *s2, size_t len)
{
diff --git a/lib/libc/memcpy.c b/lib/libc/memcpy.c
index af9ed45..ca31de5 100644
--- a/lib/libc/memcpy.c
+++ b/lib/libc/memcpy.c
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2013-2019, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stddef.h>
-#include <string.h>
+#include <string_private.h>
void *memcpy(void *dst, const void *src, size_t len)
{
diff --git a/lib/libc/memcpy_s.c b/lib/libc/memcpy_s.c
index 26953bf..ee87637 100644
--- a/lib/libc/memcpy_s.c
+++ b/lib/libc/memcpy_s.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2023, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -53,12 +53,7 @@
}
}
- /*
- * Start copy process when there is no error
- */
- while (ssize--) {
- d[ssize] = s[ssize];
- }
+ (void)memcpy(dst, src, ssize);
return 0;
}
diff --git a/lib/libc/memset.c b/lib/libc/memset.c
index c5bac8d..2513221 100644
--- a/lib/libc/memset.c
+++ b/lib/libc/memset.c
@@ -1,11 +1,11 @@
/*
- * Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stddef.h>
-#include <string.h>
+#include <string_private.h>
#include <stdint.h>
void *memset(void *dst, int val, size_t count)
diff --git a/lib/libc/strchr.c b/lib/libc/strchr.c
index 1cd03ca..b3bebe4 100644
--- a/lib/libc/strchr.c
+++ b/lib/libc/strchr.c
@@ -30,12 +30,12 @@
*/
/*
- * Portions copyright (c) 2018, Arm Limited and Contributors.
+ * Portions copyright (c) 2018-2025, Arm Limited and Contributors.
* All rights reserved.
*/
#include <stddef.h>
-#include <string.h>
+#include <string_private.h>
char *
strchr(const char *p, int ch)
diff --git a/lib/libc/strcmp.c b/lib/libc/strcmp.c
index 290db4c..5afd0e9 100644
--- a/lib/libc/strcmp.c
+++ b/lib/libc/strcmp.c
@@ -33,11 +33,11 @@
*/
/*
- * Portions copyright (c) 2018, Arm Limited and Contributors.
+ * Portions copyright (c) 2018-2025, Arm Limited and Contributors.
* All rights reserved.
*/
-#include <string.h>
+#include <string_private.h>
/*
* Compare strings.
diff --git a/lib/libc/strlen.c b/lib/libc/strlen.c
index e4b79d9..cc1d1df 100644
--- a/lib/libc/strlen.c
+++ b/lib/libc/strlen.c
@@ -1,10 +1,10 @@
/*
- * Copyright (c) 2018, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <string.h>
+#include <string_private.h>
size_t strlen(const char *s)
{
diff --git a/lib/libc/strncmp.c b/lib/libc/strncmp.c
index f0bbadc..828e0c5 100644
--- a/lib/libc/strncmp.c
+++ b/lib/libc/strncmp.c
@@ -30,11 +30,11 @@
*/
/*
- * Portions copyright (c) 2018, Arm Limited and Contributors.
+ * Portions copyright (c) 2018-2025, Arm Limited and Contributors.
* All rights reserved.
*/
-#include <string.h>
+#include <string_private.h>
int
strncmp(const char *s1, const char *s2, size_t n)
diff --git a/lib/libc/strrchr.c b/lib/libc/strrchr.c
index cd435ff..98f76c6 100644
--- a/lib/libc/strrchr.c
+++ b/lib/libc/strrchr.c
@@ -30,7 +30,7 @@
*/
#include <stddef.h>
-#include <string.h>
+#include <string_private.h>
char *
strrchr(const char *p, int ch)
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 17ecab8..1c634e3 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -1032,6 +1032,13 @@
}
/*
+ * Caches and (importantly) coherency are on so we can rely on seeing
+ * whatever the primary gave us without explicit cache maintenance
+ */
+ entry_point_info_t *ep = get_cpu_data(warmboot_ep_info);
+ cm_init_my_context(ep);
+
+ /*
* Generic management: Now we just need to retrieve the
* information that we had stashed away during the cpu_on
* call to set this cpu on its way.
diff --git a/lib/psci/psci_main.c b/lib/psci/psci_main.c
index 34de10f..f126f49 100644
--- a/lib/psci/psci_main.c
+++ b/lib/psci/psci_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,15 +28,17 @@
{
int rc;
- entry_point_info_t ep;
+ entry_point_info_t *ep;
+ unsigned int target_idx = (unsigned int)plat_core_pos_by_mpidr(target_cpu);
/* Validate the target CPU */
if (!is_valid_mpidr(target_cpu)) {
return PSCI_E_INVALID_PARAMS;
}
- /* Validate the entry point and get the entry_point_info */
- rc = psci_validate_entry_point(&ep, entrypoint, context_id);
+ ep = get_cpu_data_by_index(target_idx, warmboot_ep_info);
+ /* Validate the lower EL entry point and put it in the entry_point_info */
+ rc = psci_validate_entry_point(ep, entrypoint, context_id);
if (rc != PSCI_E_SUCCESS) {
return rc;
}
@@ -45,7 +47,7 @@
* To turn this cpu on, specify which power
* levels need to be turned on
*/
- return psci_cpu_on_start(target_cpu, &ep);
+ return psci_cpu_on_start(target_cpu, ep);
}
unsigned int psci_version(void)
@@ -59,7 +61,6 @@
{
int rc;
unsigned int target_pwrlvl, is_power_down_state;
- entry_point_info_t ep;
psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
plat_local_state_t cpu_pd_state;
unsigned int cpu_idx = plat_my_core_pos();
@@ -173,7 +174,9 @@
* point and program entry information.
*/
if (is_power_down_state != 0U) {
- rc = psci_validate_entry_point(&ep, entrypoint, context_id);
+ entry_point_info_t *ep = get_cpu_data_by_index(cpu_idx, warmboot_ep_info);
+
+ rc = psci_validate_entry_point(ep, entrypoint, context_id);
if (rc != PSCI_E_SUCCESS) {
return rc;
}
@@ -186,7 +189,6 @@
* arrival of an interrupt
*/
rc = psci_cpu_suspend_start(cpu_idx,
- &ep,
target_pwrlvl,
&state_info,
is_power_down_state);
@@ -199,8 +201,8 @@
{
int rc;
psci_power_state_t state_info;
- entry_point_info_t ep;
unsigned int cpu_idx = plat_my_core_pos();
+ entry_point_info_t *ep = get_cpu_data_by_index(cpu_idx, warmboot_ep_info);
/* Check if the current CPU is the last ON CPU in the system */
if (!psci_is_last_on_cpu(cpu_idx)) {
@@ -208,7 +210,7 @@
}
/* Validate the entry point and get the entry_point_info */
- rc = psci_validate_entry_point(&ep, entrypoint, context_id);
+ rc = psci_validate_entry_point(ep, entrypoint, context_id);
if (rc != PSCI_E_SUCCESS) {
return rc;
}
@@ -235,7 +237,6 @@
* arrival of an interrupt
*/
rc = psci_cpu_suspend_start(cpu_idx,
- &ep,
PLAT_MAX_PWR_LVL,
&state_info,
PSTATE_TYPE_POWERDOWN);
@@ -305,7 +306,7 @@
int psci_migrate(u_register_t target_cpu)
{
int rc;
- u_register_t resident_cpu_mpidr;
+ u_register_t resident_cpu_mpidr = 0;
/* Validate the target cpu */
if (!is_valid_mpidr(target_cpu))
@@ -347,7 +348,7 @@
u_register_t psci_migrate_info_up_cpu(void)
{
- u_register_t resident_cpu_mpidr;
+ u_register_t resident_cpu_mpidr = 0;
int rc;
/*
diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c
index 3eacb9c..1bbea7a 100644
--- a/lib/psci/psci_on.c
+++ b/lib/psci/psci_on.c
@@ -141,10 +141,7 @@
rc = psci_plat_pm_ops->pwr_domain_on(target_cpu);
assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL));
- if (rc == PSCI_E_SUCCESS) {
- /* Store the re-entry information for the non-secure world. */
- cm_init_context_by_index(target_idx, ep);
- } else {
+ if (rc != PSCI_E_SUCCESS) {
/* Restore the state on error. */
psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF);
flush_cpu_data_by_index(target_idx,
diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h
index 49b19c9..f3f5a5c 100644
--- a/lib/psci/psci_private.h
+++ b/lib/psci/psci_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -344,7 +344,6 @@
/* Private exported functions from psci_suspend.c */
int psci_cpu_suspend_start(unsigned int idx,
- const entry_point_info_t *ep,
unsigned int end_pwrlvl,
psci_power_state_t *state_info,
unsigned int is_power_down_state);
diff --git a/lib/psci/psci_setup.c b/lib/psci/psci_setup.c
index 3604549..e1b0ae8 100644
--- a/lib/psci/psci_setup.c
+++ b/lib/psci/psci_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -30,6 +30,7 @@
* of relying on platform defined constants.
******************************************************************************/
static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT];
+static entry_point_info_t warmboot_ep_info[PLATFORM_CORE_COUNT];
/******************************************************************************
* Define the psci capability variable.
@@ -114,6 +115,13 @@
}
}
+static void __init populate_cpu_data(void)
+{
+ for (unsigned int idx = 0; idx < psci_plat_core_count; idx++) {
+ set_cpu_data_by_index(idx, warmboot_ep_info, &warmboot_ep_info[idx]);
+ }
+}
+
/*******************************************************************************
* Core routine to populate the power domain tree. The tree descriptor passed by
* the platform is populated breadth-first and the first entry in the map
@@ -218,6 +226,9 @@
/* Update the CPU limits for each node in psci_non_cpu_pd_nodes */
psci_update_pwrlvl_limits();
+ /* Initialise the warmboot entrypoints */
+ populate_cpu_data();
+
/* Populate the mpidr field of cpu node for this CPU */
psci_cpu_pd_nodes[cpu_idx].mpidr =
read_mpidr() & MPIDR_AFFINITY_MASK;
diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c
index f690e49..39d4482 100644
--- a/lib/psci/psci_suspend.c
+++ b/lib/psci/psci_suspend.c
@@ -45,7 +45,6 @@
static void psci_suspend_to_pwrdown_start(unsigned int idx,
unsigned int end_pwrlvl,
unsigned int max_off_lvl,
- const entry_point_info_t *ep,
const psci_power_state_t *state_info)
{
PUBLISH_EVENT_ARG(psci_suspend_pwrdown_start, &idx);
@@ -85,12 +84,6 @@
if (psci_plat_pm_ops->pwr_domain_suspend_pwrdown_early != NULL)
psci_plat_pm_ops->pwr_domain_suspend_pwrdown_early(state_info);
#endif
-
- /*
- * Store the re-entry information for the non-secure world.
- */
- cm_init_my_context(ep);
-
/*
* Arch. management. Initiate power down sequence.
*/
@@ -116,7 +109,6 @@
* not possible to undo any of the actions taken beyond that point.
******************************************************************************/
int psci_cpu_suspend_start(unsigned int idx,
- const entry_point_info_t *ep,
unsigned int end_pwrlvl,
psci_power_state_t *state_info,
unsigned int is_power_down_state)
@@ -124,10 +116,6 @@
int rc = PSCI_E_SUCCESS;
unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
unsigned int max_off_lvl = 0;
-#if FEAT_PABANDON
- cpu_context_t *ctx = cm_get_context(NON_SECURE);
- cpu_context_t old_ctx;
-#endif
/*
* This function must only be called on platforms where the
@@ -205,26 +193,9 @@
#if !CTX_INCLUDE_EL2_REGS
cm_el1_sysregs_context_save(NON_SECURE);
#endif
- /*
- * when the core wakes it expects its context to already be in
- * place so we must overwrite it before powerdown. But if
- * powerdown never happens we want the old context. Save it in
- * case we wake up. EL2/El1 will not be touched by PSCI so don't
- * copy */
- memcpy(&ctx->gpregs_ctx, &old_ctx.gpregs_ctx, sizeof(gp_regs_t));
- memcpy(&ctx->el3state_ctx, &old_ctx.el3state_ctx, sizeof(el3_state_t));
-#if DYNAMIC_WORKAROUND_CVE_2018_3639
- memcpy(&ctx->cve_2018_3639_ctx, &old_ctx.cve_2018_3639_ctx, sizeof(cve_2018_3639_t));
-#endif
-#if ERRATA_SPECULATIVE_AT
- memcpy(&ctx->errata_speculative_at_ctx, &old_ctx.errata_speculative_at_ctx, sizeof(errata_speculative_at_t));
-#endif
-#if CTX_INCLUDE_PAUTH_REGS
- memcpy(&ctx->pauth_ctx, &old_ctx.pauth_ctx, sizeof(pauth_t));
-#endif
#endif
max_off_lvl = psci_find_max_off_lvl(state_info);
- psci_suspend_to_pwrdown_start(idx, end_pwrlvl, end_pwrlvl, ep, state_info);
+ psci_suspend_to_pwrdown_start(idx, end_pwrlvl, end_pwrlvl, state_info);
}
/*
@@ -301,18 +272,6 @@
#if FEAT_PABANDON
psci_cpu_suspend_to_powerdown_finish(idx, max_off_lvl, state_info);
- /* we overwrote context ourselves, put it back */
- memcpy(&ctx->gpregs_ctx, &old_ctx.gpregs_ctx, sizeof(gp_regs_t));
- memcpy(&ctx->el3state_ctx, &old_ctx.el3state_ctx, sizeof(el3_state_t));
-#if DYNAMIC_WORKAROUND_CVE_2018_3639
- memcpy(&ctx->cve_2018_3639_ctx, &old_ctx.cve_2018_3639_ctx, sizeof(cve_2018_3639_t));
-#endif
-#if ERRATA_SPECULATIVE_AT
- memcpy(&ctx->errata_speculative_at_ctx, &old_ctx.errata_speculative_at_ctx, sizeof(errata_speculative_at_t));
-#endif
-#if CTX_INCLUDE_PAUTH_REGS
- memcpy(&ctx->pauth_ctx, &old_ctx.pauth_ctx, sizeof(pauth_t));
-#endif
#if !CTX_INCLUDE_EL2_REGS
cm_el1_sysregs_context_restore(NON_SECURE);
#endif
diff --git a/lib/xlat_mpu/aarch64/enable_mpu.S b/lib/xlat_mpu/aarch64/enable_mpu.S
deleted file mode 100644
index 0dda979..0000000
--- a/lib/xlat_mpu/aarch64/enable_mpu.S
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <asm_macros.S>
-#include <assert_macros.S>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-#include <platform_def.h>
-
- .global enable_mpu_direct_el2
-
- /* void enable_mmu_direct_el2(unsigned int flags) */
-func enable_mpu_direct_el2
-#if ENABLE_ASSERTIONS
- mrs x1, sctlr_el2
- tst x1, #SCTLR_M_BIT
- ASM_ASSERT(eq)
-#endif
- mov x7, x0
- adrp x0, mmu_cfg_params
- add x0, x0, :lo12:mmu_cfg_params
-
- /* (MAIRs are already set up) */
-
- /* TCR */
- ldr x2, [x0, #(MMU_CFG_TCR << 3)]
- msr tcr_el2, x2
-
- /*
- * Ensure all translation table writes have drained into memory, the TLB
- * invalidation is complete, and translation register writes are
- * committed before enabling the MMU
- */
- dsb ish
- isb
-
- /* Set and clear required fields of SCTLR */
- mrs x4, sctlr_el2
- mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT
- orr x4, x4, x5
-
- /* Additionally, amend SCTLR fields based on flags */
- bic x5, x4, #SCTLR_C_BIT
- tst x7, #DISABLE_DCACHE
- csel x4, x5, x4, ne
-
- msr sctlr_el2, x4
- isb
-
- ret
-endfunc enable_mpu_direct_el2
diff --git a/lib/xlat_mpu/aarch64/xlat_mpu_arch.c b/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
deleted file mode 100644
index b462de0..0000000
--- a/lib/xlat_mpu/aarch64/xlat_mpu_arch.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2021-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <stdbool.h>
-#include <stdint.h>
-
-#include "../xlat_mpu_private.h"
-#include <arch.h>
-#include <arch_features.h>
-#include <lib/cassert.h>
-#include <lib/utils_def.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-
-#include <fvp_r_arch_helpers.h>
-
-#warning "xlat_mpu library is currently experimental and its API may change in future."
-
-#if ENABLE_ASSERTIONS
-/*
- * Return minimum virtual address space size supported by the architecture
- */
-uintptr_t xlat_get_min_virt_addr_space_size(void)
-{
- uintptr_t ret;
-
- if (is_feat_ttst_present()) {
- ret = MIN_VIRT_ADDR_SPACE_SIZE_TTST;
- } else {
- ret = MIN_VIRT_ADDR_SPACE_SIZE;
- }
- return ret;
-}
-#endif /* ENABLE_ASSERTIONS*/
-
-bool is_mpu_enabled_ctx(const xlat_ctx_t *ctx)
-{
- if (ctx->xlat_regime == EL1_EL0_REGIME) {
- assert(xlat_arch_current_el() >= 1U);
- return (read_sctlr_el1() & SCTLR_M_BIT) != 0U;
- } else {
- assert(xlat_arch_current_el() >= 2U);
- return (read_sctlr_el2() & SCTLR_M_BIT) != 0U;
- }
-}
-
-bool is_dcache_enabled(void)
-{
- unsigned int el = get_current_el();
-
- if (el == 1U) {
- return (read_sctlr_el1() & SCTLR_C_BIT) != 0U;
- } else { /* must be EL2 */
- return (read_sctlr_el2() & SCTLR_C_BIT) != 0U;
- }
-}
-
-unsigned int xlat_arch_current_el(void)
-{
- unsigned int el = (unsigned int)GET_EL(read_CurrentEl());
-
- assert(el > 0U);
-
- return el;
-}
-
diff --git a/lib/xlat_mpu/ro_xlat_mpu.mk b/lib/xlat_mpu/ro_xlat_mpu.mk
deleted file mode 100644
index d3af3bd..0000000
--- a/lib/xlat_mpu/ro_xlat_mpu.mk
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Copyright (c) 2021, Arm Limited. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-ifeq (${USE_DEBUGFS}, 1)
- $(error "Debugfs requires functionality from the dynamic translation \
- library and is incompatible with ALLOW_RO_XLAT_TABLES.")
-endif
-
-ifeq (${ARCH},aarch32)
- $(error "The xlat_mpu library does not currently support AArch32.")
-endif
diff --git a/lib/xlat_mpu/xlat_mpu.mk b/lib/xlat_mpu/xlat_mpu.mk
deleted file mode 100644
index 31bef04..0000000
--- a/lib/xlat_mpu/xlat_mpu.mk
+++ /dev/null
@@ -1,19 +0,0 @@
-#
-# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-XLAT_MPU_LIB_V1_SRCS := $(addprefix lib/xlat_mpu/, \
- ${ARCH}/enable_mpu.S \
- ${ARCH}/xlat_mpu_arch.c \
- xlat_mpu_context.c \
- xlat_mpu_core.c \
- xlat_mpu_utils.c)
-
-XLAT_MPU_LIB_V1 := 1
-$(eval $(call add_define,XLAT_MPU_LIB_V1))
-
-ifeq (${ALLOW_XLAT_MPU}, 1)
- include lib/xlat_mpu_v2/ro_xlat_mpu.mk
-endif
diff --git a/lib/xlat_mpu/xlat_mpu_context.c b/lib/xlat_mpu/xlat_mpu_context.c
deleted file mode 100644
index 783f21d..0000000
--- a/lib/xlat_mpu/xlat_mpu_context.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <common/debug.h>
-
-#include "lib/xlat_mpu/xlat_mpu.h"
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-#include "xlat_mpu_private.h"
-
-#include <fvp_r_arch_helpers.h>
-#include <platform_def.h>
-
-#warning "xlat_mpu library is currently experimental and its API may change in future."
-
-
-/*
- * MMU configuration register values for the active translation context. Used
- * from the MMU assembly helpers.
- */
-uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
-
-/*
- * Allocate and initialise the default translation context for the BL image
- * currently executing.
- */
-REGISTER_XLAT_CONTEXT(tf, MAX_MMAP_REGIONS, MAX_XLAT_TABLES,
- PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE);
-
-void mmap_add(const mmap_region_t *mm)
-{
- mmap_add_ctx(&tf_xlat_ctx, mm);
-}
-
-void __init init_xlat_tables(void)
-{
- assert(tf_xlat_ctx.xlat_regime == EL_REGIME_INVALID);
-
- unsigned int current_el = xlat_arch_current_el();
-
- if (current_el == 1U) {
- tf_xlat_ctx.xlat_regime = EL1_EL0_REGIME;
- } else {
- assert(current_el == 2U);
- tf_xlat_ctx.xlat_regime = EL2_REGIME;
- }
- /* Note: If EL3 is supported in future v8-R64, add EL3 assignment */
- init_xlat_tables_ctx(&tf_xlat_ctx);
-}
-
-int xlat_get_mem_attributes(uintptr_t base_va, uint32_t *attr)
-{
- return xlat_get_mem_attributes_ctx(&tf_xlat_ctx, base_va, attr);
-}
-
-void enable_mpu_el2(unsigned int flags)
-{
- /* EL2 is strictly MPU on v8-R64, so no need for setup_mpu_cfg() */
- enable_mpu_direct_el2(flags);
-}
diff --git a/lib/xlat_mpu/xlat_mpu_core.c b/lib/xlat_mpu/xlat_mpu_core.c
deleted file mode 100644
index 33f381d..0000000
--- a/lib/xlat_mpu/xlat_mpu_core.c
+++ /dev/null
@@ -1,408 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <string.h>
-
-#include <arch_features.h>
-#include <common/debug.h>
-#include <lib/utils_def.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-#include "xlat_mpu_private.h"
-
-#include <fvp_r_arch_helpers.h>
-#include <platform_def.h>
-
-#warning "xlat_mpu library is currently experimental and its API may change in future."
-
-
-/* Helper function that cleans the data cache only if it is enabled. */
-static inline __attribute__((unused))
- void xlat_clean_dcache_range(uintptr_t addr, size_t size)
-{
- if (is_dcache_enabled()) {
- clean_dcache_range(addr, size);
- }
-}
-
-
-
-/* Calculate region-attributes byte for PRBAR part of MPU-region descriptor: */
-uint64_t prbar_attr_value(uint32_t attr)
-{
- uint64_t retValue = UL(0);
- uint64_t extract; /* temp var holding bit extracted from attr */
-
- /* Extract and stuff SH: */
- extract = (uint64_t) ((attr >> MT_SHAREABILITY_SHIFT)
- & MT_SHAREABILITY_MASK);
- retValue |= (extract << PRBAR_SH_SHIFT);
-
- /* Extract and stuff AP: */
- extract = (uint64_t) ((attr >> MT_PERM_SHIFT) & MT_PERM_MASK);
- if (extract == 0U) {
- retValue |= (UL(2) << PRBAR_AP_SHIFT);
- } else /* extract == 1 */ {
- retValue |= (UL(0) << PRBAR_AP_SHIFT);
- }
-
- /* Extract and stuff XN: */
- extract = (uint64_t) ((attr >> MT_EXECUTE_SHIFT) & MT_EXECUTE_MASK);
- retValue |= (extract << PRBAR_XN_SHIFT);
- /* However, also don't execute in peripheral space: */
- extract = (uint64_t) ((attr >> MT_TYPE_SHIFT) & MT_TYPE_MASK);
- if (extract == 0U) {
- retValue |= (UL(1) << PRBAR_XN_SHIFT);
- }
- return retValue;
-}
-
-/* Calculate region-attributes byte for PRLAR part of MPU-region descriptor: */
-uint64_t prlar_attr_value(uint32_t attr)
-{
- uint64_t retValue = UL(0);
- uint64_t extract; /* temp var holding bit extracted from attr */
-
- /* Extract and stuff AttrIndx: */
- extract = (uint64_t) ((attr >> MT_TYPE_SHIFT)
- & MT_TYPE_MASK);
- switch (extract) {
- case UL(0):
- retValue |= (UL(1) << PRLAR_ATTR_SHIFT);
- break;
- case UL(2):
- /* 0, so OR in nothing */
- break;
- case UL(3):
- retValue |= (UL(2) << PRLAR_ATTR_SHIFT);
- break;
- default:
- retValue |= (extract << PRLAR_ATTR_SHIFT);
- break;
- }
-
- /* Stuff EN: */
- retValue |= (UL(1) << PRLAR_EN_SHIFT);
-
- /* Force NS to 0 (Secure); v8-R64 only supports Secure: */
- extract = ~(1U << PRLAR_NS_SHIFT);
- retValue &= extract;
-
- return retValue;
-}
-
-/*
- * Function that writes an MPU "translation" into the MPU registers. If not
- * possible (e.g., if no more MPU regions available) boot is aborted.
- */
-static void mpu_map_region(mmap_region_t *mm)
-{
- uint64_t prenr_el2_value = 0UL;
- uint64_t prbar_attrs = 0UL;
- uint64_t prlar_attrs = 0UL;
- int region_to_use = 0;
-
- /* If all MPU regions in use, then abort boot: */
- prenr_el2_value = read_prenr_el2();
- assert(prenr_el2_value != 0xffffffff);
-
- /* Find and select first-available MPU region (PRENR has an enable bit
- * for each MPU region, 1 for in-use or 0 for unused):
- */
- for (region_to_use = 0; region_to_use < N_MPU_REGIONS;
- region_to_use++) {
- if (((prenr_el2_value >> region_to_use) & 1) == 0) {
- break;
- }
- }
- write_prselr_el2((uint64_t) (region_to_use));
- isb();
-
- /* Set base and limit addresses: */
- write_prbar_el2(mm->base_pa & PRBAR_PRLAR_ADDR_MASK);
- write_prlar_el2((mm->base_pa + mm->size - 1UL)
- & PRBAR_PRLAR_ADDR_MASK);
- dsbsy();
- isb();
-
- /* Set attributes: */
- prbar_attrs = prbar_attr_value(mm->attr);
- write_prbar_el2(read_prbar_el2() | prbar_attrs);
- prlar_attrs = prlar_attr_value(mm->attr);
- write_prlar_el2(read_prlar_el2() | prlar_attrs);
- dsbsy();
- isb();
-
- /* Mark this MPU region as used: */
- prenr_el2_value |= (1 << region_to_use);
- write_prenr_el2(prenr_el2_value);
- isb();
-}
-
-/*
- * Function that verifies that a region can be mapped.
- * Returns:
- * 0: Success, the mapping is allowed.
- * EINVAL: Invalid values were used as arguments.
- * ERANGE: The memory limits were surpassed.
- * ENOMEM: There is not enough memory in the mmap array.
- * EPERM: Region overlaps another one in an invalid way.
- */
-static int mmap_add_region_check(const xlat_ctx_t *ctx, const mmap_region_t *mm)
-{
- unsigned long long base_pa = mm->base_pa;
- uintptr_t base_va = mm->base_va;
- size_t size = mm->size;
-
- unsigned long long end_pa = base_pa + size - 1U;
- uintptr_t end_va = base_va + size - 1U;
-
- if (base_pa != base_va) {
- return -EINVAL; /* MPU does not perform address translation */
- }
- if ((base_pa % 64ULL) != 0ULL) {
- return -EINVAL; /* MPU requires 64-byte alignment */
- }
- /* Check for overflows */
- if ((base_pa > end_pa) || (base_va > end_va)) {
- return -ERANGE;
- }
- if (end_pa > ctx->pa_max_address) {
- return -ERANGE;
- }
- /* Check that there is space in the ctx->mmap array */
- if (ctx->mmap[ctx->mmap_num - 1].size != 0U) {
- return -ENOMEM;
- }
- /* Check for PAs and VAs overlaps with all other regions */
- for (const mmap_region_t *mm_cursor = ctx->mmap;
- mm_cursor->size != 0U; ++mm_cursor) {
-
- uintptr_t mm_cursor_end_va =
- mm_cursor->base_va + mm_cursor->size - 1U;
-
- /*
- * Check if one of the regions is completely inside the other
- * one.
- */
- bool fully_overlapped_va =
- ((base_va >= mm_cursor->base_va) &&
- (end_va <= mm_cursor_end_va)) ||
- ((mm_cursor->base_va >= base_va) &&
- (mm_cursor_end_va <= end_va));
-
- /*
- * Full VA overlaps are only allowed if both regions are
- * identity mapped (zero offset) or have the same VA to PA
- * offset. Also, make sure that it's not the exact same area.
- * This can only be done with static regions.
- */
- if (fully_overlapped_va) {
-
-#if PLAT_XLAT_TABLES_DYNAMIC
- if (((mm->attr & MT_DYNAMIC) != 0U) ||
- ((mm_cursor->attr & MT_DYNAMIC) != 0U)) {
- return -EPERM;
- }
-#endif /* PLAT_XLAT_TABLES_DYNAMIC */
- if ((mm_cursor->base_va - mm_cursor->base_pa)
- != (base_va - base_pa)) {
- return -EPERM;
- }
- if ((base_va == mm_cursor->base_va) &&
- (size == mm_cursor->size)) {
- return -EPERM;
- }
- } else {
- /*
- * If the regions do not have fully overlapping VAs,
- * then they must have fully separated VAs and PAs.
- * Partial overlaps are not allowed
- */
-
- unsigned long long mm_cursor_end_pa =
- mm_cursor->base_pa + mm_cursor->size - 1U;
-
- bool separated_pa = (end_pa < mm_cursor->base_pa) ||
- (base_pa > mm_cursor_end_pa);
- bool separated_va = (end_va < mm_cursor->base_va) ||
- (base_va > mm_cursor_end_va);
-
- if (!separated_va || !separated_pa) {
- return -EPERM;
- }
- }
- }
-
- return 0;
-}
-
-void mmap_add_region_ctx(xlat_ctx_t *ctx, const mmap_region_t *mm)
-{
- mmap_region_t *mm_cursor = ctx->mmap, *mm_destination;
- const mmap_region_t *mm_end = ctx->mmap + ctx->mmap_num;
- const mmap_region_t *mm_last;
- unsigned long long end_pa = mm->base_pa + mm->size - 1U;
- uintptr_t end_va = mm->base_va + mm->size - 1U;
- int ret;
-
- /* Ignore empty regions */
- if (mm->size == 0U) {
- return;
- }
-
- /* Static regions must be added before initializing the xlat tables. */
- assert(!ctx->initialized);
-
- ret = mmap_add_region_check(ctx, mm);
- if (ret != 0) {
- ERROR("mmap_add_region_check() failed. error %d\n", ret);
- assert(false);
- return;
- }
-
- /*
- * Find the last entry marker in the mmap
- */
- mm_last = ctx->mmap;
- while ((mm_last->size != 0U) && (mm_last < mm_end)) {
- ++mm_last;
- }
-
- /*
- * Check if we have enough space in the memory mapping table.
- * This shouldn't happen as we have checked in mmap_add_region_check
- * that there is free space.
- */
- assert(mm_last->size == 0U);
-
- /* Make room for new region by moving other regions up by one place */
- mm_destination = mm_cursor + 1;
- (void)memmove(mm_destination, mm_cursor,
- (uintptr_t)mm_last - (uintptr_t)mm_cursor);
-
- /*
- * Check we haven't lost the empty sentinel from the end of the array.
- * This shouldn't happen as we have checked in mmap_add_region_check
- * that there is free space.
- */
- assert(mm_end->size == 0U);
-
- *mm_cursor = *mm;
-
- if (end_pa > ctx->max_pa) {
- ctx->max_pa = end_pa;
- }
- if (end_va > ctx->max_va) {
- ctx->max_va = end_va;
- }
-}
-
-void mmap_add_ctx(xlat_ctx_t *ctx, const mmap_region_t *mm)
-{
- const mmap_region_t *mm_cursor = mm;
-
- while (mm_cursor->granularity != 0U) {
- mmap_add_region_ctx(ctx, mm_cursor);
- mm_cursor++;
- }
-}
-
-void __init init_xlat_tables_ctx(xlat_ctx_t *ctx)
-{
- uint64_t mair = UL(0);
-
- assert(ctx != NULL);
- assert(!ctx->initialized);
- assert((ctx->xlat_regime == EL2_REGIME) ||
- (ctx->xlat_regime == EL1_EL0_REGIME));
- /* Note: Add EL3_REGIME if EL3 is supported in future v8-R64 cores. */
- assert(!is_mpu_enabled_ctx(ctx));
-
- mmap_region_t *mm = ctx->mmap;
-
- assert(ctx->va_max_address >=
- (xlat_get_min_virt_addr_space_size() - 1U));
- assert(ctx->va_max_address <= (MAX_VIRT_ADDR_SPACE_SIZE - 1U));
- assert(IS_POWER_OF_TWO(ctx->va_max_address + 1U));
-
- xlat_mmap_print(mm);
-
- /* All tables must be zeroed before mapping any region. */
-
- for (unsigned int i = 0U; i < ctx->base_table_entries; i++)
- ctx->base_table[i] = INVALID_DESC;
-
- /* Also mark all MPU regions as invalid in the MPU hardware itself: */
- write_prenr_el2(0);
- /* Sufficient for current, max-32-region implementations. */
- dsbsy();
- isb();
- while (mm->size != 0U) {
- if (read_prenr_el2() == ALL_MPU_EL2_REGIONS_USED) {
- ERROR("Not enough MPU regions to map region:\n"
- " VA:0x%lx PA:0x%llx size:0x%zx attr:0x%x\n",
- mm->base_va, mm->base_pa, mm->size, mm->attr);
- panic();
- } else {
-#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
- xlat_clean_dcache_range((uintptr_t)mm->base_va,
- mm->size);
-#endif
- mpu_map_region(mm);
- }
- mm++;
- }
-
- ctx->initialized = true;
-
- xlat_tables_print(ctx);
-
- /* Set attributes in the right indices of the MAIR */
- mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);
- mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,
- ATTR_IWBWA_OWBWA_NTR_INDEX);
- mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE,
- ATTR_NON_CACHEABLE_INDEX);
- write_mair_el2(mair);
- dsbsy();
- isb();
-}
-
-/*
- * Function to wipe clean and disable all MPU regions. This function expects
- * that the MPU has already been turned off, and caching concerns addressed,
- * but it nevertheless also explicitly turns off the MPU.
- */
-void clear_all_mpu_regions(void)
-{
- uint64_t sctlr_el2_value = 0UL;
- uint64_t region_n = 0UL;
-
- /*
- * MPU should already be disabled, but explicitly disable it
- * nevertheless:
- */
- sctlr_el2_value = read_sctlr_el2() & ~(1UL);
- write_sctlr_el2(sctlr_el2_value);
-
- /* Disable all regions: */
- write_prenr_el2(0UL);
-
- /* Sequence through all regions, zeroing them out and turning off: */
- for (region_n = 0UL; region_n < N_MPU_REGIONS; region_n++) {
- write_prselr_el2(region_n);
- isb();
- write_prbar_el2((uint64_t) 0);
- write_prlar_el2((uint64_t) 0);
- dsbsy();
- isb();
- }
-}
diff --git a/lib/xlat_mpu/xlat_mpu_private.h b/lib/xlat_mpu/xlat_mpu_private.h
deleted file mode 100644
index 5b0697d..0000000
--- a/lib/xlat_mpu/xlat_mpu_private.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef XLAT_MPU_PRIVATE_H
-#define XLAT_MPU_PRIVATE_H
-
-#include <stdbool.h>
-
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-
-#include <platform_def.h>
-
-#if PLAT_XLAT_TABLES_DYNAMIC
-/*
- * Private shifts and masks to access fields of an mmap attribute
- */
-/* Dynamic or static */
-#define MT_DYN_SHIFT U(31)
-
-/*
- * Memory mapping private attributes
- *
- * Private attributes not exposed in the public header.
- */
-
-#endif /* PLAT_XLAT_TABLES_DYNAMIC */
-
-/* Calculate region-attributes byte for PRBAR part of MPU-region descriptor: */
-uint64_t prbar_attr_value(uint32_t attr);
-/* Calculate region-attributes byte for PRLAR part of MPU-region descriptor: */
-uint64_t prlar_attr_value(uint32_t attr);
-/* Calculates the attr value for a given PRBAR and PRLAR entry value: */
-uint32_t region_attr(uint64_t prbar_attr, uint64_t prlar_attr);
-
-#define PRBAR_PRLAR_ADDR_MASK UL(0xffffffffffc0)
- /* mask for PRBAR & PRLAR MPU-region field */
-/* MPU region attribute bit fields: */
-#define PRBAR_SH_SHIFT UL(4)
-#define PRBAR_SH_MASK UL(0x3)
-#define PRBAR_AP_SHIFT UL(2)
-#define PRBAR_AP_MASK UL(0x3)
-#define PRBAR_XN_SHIFT UL(1)
-#define PRBAR_XN_MASK UL(0x3)
-#define PRLAR_NS_SHIFT UL(4)
-#define PRLAR_NS_MASK UL(0x3)
-#define PRBAR_ATTR_SHIFT UL(0)
-#define PRBAR_ATTR_MASK UL(0x3f)
-#define PRLAR_ATTR_SHIFT UL(1)
-#define PRLAR_ATTR_MASK UL(0x7)
-#define PRLAR_EN_SHIFT UL(0)
-#define PRLAR_EN_MASK UL(0x1)
-/* Aspects of the source attributes not defined elsewhere: */
-#define MT_PERM_MASK UL(0x1)
-#define MT_SEC_MASK UL(0x1)
-#define MT_EXECUTE_MASK UL(0x3)
-#define MT_TYPE_SHIFT UL(0)
-
-#define MPUIR_EL2 S3_4_C0_C0_4
-#define PRBAR_EL2 S3_4_C6_C8_0
-#define PRLAR_EL2 S3_4_C6_C8_1
-#define PRSELR_EL2 S3_4_C6_C2_1
-#define PRENR_EL2 S3_4_C6_C1_1
-
-/* v8-R64 MPU registers */
-DEFINE_RENAME_SYSREG_RW_FUNCS(mpuir_el2, MPUIR_EL2)
-DEFINE_RENAME_SYSREG_RW_FUNCS(prenr_el2, PRENR_EL2)
-DEFINE_RENAME_SYSREG_RW_FUNCS(prselr_el2, PRSELR_EL2)
-DEFINE_RENAME_SYSREG_RW_FUNCS(prbar_el2, PRBAR_EL2)
-DEFINE_RENAME_SYSREG_RW_FUNCS(prlar_el2, PRLAR_EL2)
-
-extern uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
-
-/*
- * Return the execute-never mask that will prevent instruction fetch at the
- * given translation regime.
- */
-uint64_t xlat_arch_regime_get_xn_desc(int xlat_regime);
-
-/* Print VA, PA, size and attributes of all regions in the mmap array. */
-void xlat_mmap_print(const mmap_region_t *mmap);
-
-/*
- * Print the current state of the translation tables by reading them from
- * memory.
- */
-void xlat_tables_print(xlat_ctx_t *ctx);
-
-/*
- * Returns a block/page table descriptor for the given level and attributes.
- */
-uint64_t xlat_desc(const xlat_ctx_t *ctx, uint32_t attr,
- unsigned long long addr_pa, unsigned int level);
-
-/*
- * Architecture-specific initialization code.
- */
-
-/* Returns the current Exception Level. The returned EL must be 1 or higher. */
-unsigned int xlat_arch_current_el(void);
-
-/*
- * Returns true if the MMU of the translation regime managed by the given
- * xlat_ctx_t is enabled, false otherwise.
- */
-bool is_mpu_enabled_ctx(const xlat_ctx_t *ctx);
-
-/*
- * Returns minimum virtual address space size supported by the architecture
- */
-uintptr_t xlat_get_min_virt_addr_space_size(void);
-
-#endif /* XLAT_MPU_PRIVATE_H */
diff --git a/lib/xlat_mpu/xlat_mpu_utils.c b/lib/xlat_mpu/xlat_mpu_utils.c
deleted file mode 100644
index dc5f956..0000000
--- a/lib/xlat_mpu/xlat_mpu_utils.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <stdio.h>
-
-#include <common/debug.h>
-#include <lib/utils_def.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-#include "xlat_mpu_private.h"
-
-#include <fvp_r_arch_helpers.h>
-#include <platform_def.h>
-
-#warning "xlat_mpu library is currently experimental and its API may change in future."
-
-
-void xlat_mmap_print(__unused const mmap_region_t *mmap)
-{
- /* Empty */
-}
-
-#if LOG_LEVEL < LOG_LEVEL_VERBOSE
-
-void xlat_tables_print(__unused xlat_ctx_t *ctx)
-{
- /* Empty */
-}
-
-#else /* if LOG_LEVEL >= LOG_LEVEL_VERBOSE */
-
-static void xlat_tables_print_internal(__unused xlat_ctx_t *ctx)
-{
- int region_to_use = 0;
- uintptr_t region_base;
- size_t region_size;
- uint64_t prenr_el2_value = 0U;
-
- /*
- * Keep track of how many invalid descriptors are counted in a row.
- * Whenever multiple invalid descriptors are found, only the first one
- * is printed, and a line is added to inform about how many descriptors
- * have been omitted.
- */
-
- /*
- * TODO: Remove this WARN() and comment when these API calls are more
- * completely implemented and tested!
- */
- WARN("%s in this early version of xlat_mpu library may not produce reliable results!",
- __func__);
-
- /*
- * Sequence through all regions and print those in-use (PRENR has an
- * enable bit for each MPU region, 1 for in-use or 0 for unused):
- */
- prenr_el2_value = read_prenr_el2();
- for (region_to_use = 0; region_to_use < N_MPU_REGIONS;
- region_to_use++) {
- if (((prenr_el2_value >> region_to_use) & 1U) == 0U) {
- continue;
- }
- region_base = read_prbar_el2() & PRBAR_PRLAR_ADDR_MASK;
- region_size = read_prlar_el2() & PRBAR_PRLAR_ADDR_MASK;
- printf("Address: 0x%llx, size: 0x%llx ",
- (long long) region_base,
- (long long) region_size);
- }
-}
-
-void xlat_tables_print(__unused xlat_ctx_t *ctx)
-{
- xlat_tables_print_internal(ctx);
-}
-
-#endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */
diff --git a/plat/amd/versal2/plat_psci_pm.c b/plat/amd/versal2/plat_psci_pm.c
index 50614d5..3cc6b95 100644
--- a/plat/amd/versal2/plat_psci_pm.c
+++ b/plat/amd/versal2/plat_psci_pm.c
@@ -110,7 +110,7 @@
* Send the system reset request to the firmware if power down request
* is not received from firmware.
*/
- if (pwrdwn_req_received == true) {
+ if (pwrdwn_req_received == false) {
/*
* TODO: shutdown scope for this reset needs be revised once
* we have a clearer understanding of the overall reset scoping
diff --git a/plat/amd/versal2/pm_service/pm_svc_main.c b/plat/amd/versal2/pm_service/pm_svc_main.c
index 88848e2..10d2ed2 100644
--- a/plat/amd/versal2/pm_service/pm_svc_main.c
+++ b/plat/amd/versal2/pm_service/pm_svc_main.c
@@ -133,7 +133,7 @@
/* Check status register for each IPI except PMC */
for (i = IPI_ID_APU; i <= IPI_ID_5; i++) {
- ipi_status = (uint32_t)ipi_mb_enquire_status(IPI_ID_APU, i);
+ ipi_status = ipi_mb_enquire_status(IPI_ID_APU, i);
/* If any agent other than PMC has generated IPI FIQ then send SGI to mbox driver */
if ((ipi_status & (uint32_t)IPI_MB_STATUS_RECV_PENDING) > (uint32_t) 0) {
@@ -143,8 +143,8 @@
}
/* If PMC has not generated interrupt then end ISR */
- ipi_status = (uint32_t)ipi_mb_enquire_status(IPI_ID_APU, IPI_ID_PMC);
- if ((ipi_status & (uint32_t) IPI_MB_STATUS_RECV_PENDING) == (uint32_t) 0) {
+ ipi_status = ipi_mb_enquire_status(IPI_ID_APU, IPI_ID_PMC);
+ if ((ipi_status & IPI_MB_STATUS_RECV_PENDING) == (uint32_t)0) {
plat_ic_end_of_interrupt(id);
goto end;
}
diff --git a/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c b/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
index e0b7750..fb7f48e 100644
--- a/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
+++ b/plat/arm/board/fvp/fconf/fconf_hw_config_getter.c
@@ -84,8 +84,12 @@
/* Find the offset of the node containing "arm,psci-1.0" compatible property */
node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,psci-1.0");
if (node < 0) {
- ERROR("FCONF: Unable to locate node with arm,psci-1.0 compatible property\n");
- return node;
+ /* Fall back to 0.2 */
+ node = fdt_node_offset_by_compatible(hw_config_dtb, -1, "arm,psci-0.2");
+ if (node < 0) {
+ ERROR("FCONF: Unable to locate node with arm,psci compatible property\n");
+ return node;
+ }
}
err = fdt_read_uint32(hw_config_dtb, node, "max-pwr-lvl", &max_pwr_lvl);
diff --git a/plat/arm/board/fvp/fvp_bl2_measured_boot.c b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
index 8bf7dad..28aef92 100644
--- a/plat/arm/board/fvp/fvp_bl2_measured_boot.c
+++ b/plat/arm/board/fvp/fvp_bl2_measured_boot.c
@@ -218,5 +218,5 @@
}
#endif /* defined(SPD_tspd) || defined(SPD_spmd) */
- dump_event_log((uint8_t *)event_log_base, event_log_cur_size);
+ event_log_dump((uint8_t *)event_log_base, event_log_cur_size);
}
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index 777729e..c8439e9 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -156,7 +156,7 @@
*/
#if TRUSTED_BOARD_BOOT
#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA
-# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
+# define PLAT_ARM_MAX_BL2_SIZE (UL(0x20000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
#elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA
# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION)
#else
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
deleted file mode 100644
index 74835f6..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the CSS specific memory and interrupt map
- * definitions for the first generation platforms based on the A75, N1 and V1
- * CPUs. There are minor differences in the memory map of these platforms and
- * those differences are not in the scope of this file.
- */
-
-#ifndef NRD_CSS_DEF1_H
-#define NRD_CSS_DEF1_H
-
-/*******************************************************************************
- * CSS memory map related defines
- ******************************************************************************/
-
-/* On-Chip ROM */
-#define NRD_CSS_TRUSTED_ROM_BASE UL(0x00000000)
-#define NRD_CSS_TRUSTED_ROM_SIZE UL(0x00080000) /* 512KB */
-
-/* On-Chip RAM */
-#define NRD_CSS_TRUSTED_SRAM_SIZE UL(0x00080000) /* 512KB */
-#define NRD_CSS_NONTRUSTED_SRAM_BASE UL(0x06000000)
-#define NRD_CSS_NONTRUSTED_SRAM_SIZE UL(0x00080000) /* 512KB */
-
-/* PL011 UART */
-#define NRD_CSS_SEC_UART_BASE UL(0x2A410000)
-#define NRD_CSS_UART_SIZE UL(0x10000)
-
-/* CSS peripherals */
-#define NRD_CSS_PERIPH_BASE UL(0x20000000)
-#define NRD_CSS_PERIPH_SIZE UL(0x40000000)
-
-/* Secure Watchdog */
-#define NRD_CSS_WDOG_BASE UL(0x2A480000)
-
-/* DRAM2 */
-#define NRD_CSS_DRAM2_BASE ULL(0x8080000000)
-#define NRD_CSS_DRAM2_SIZE ULL(0x180000000)
-
-#endif /* NRD_CSS_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
deleted file mode 100644
index 70a7d49..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the CSS firmware specific definitions for
- * the first generation platforms based on the A75, N1 and V1 CPUs.
- */
-
-#ifndef NRD1_CSS_FW_DEF1_H
-#define NRD1_CSS_FW_DEF1_H
-
-#include <nrd_css_def1.h>
-
-/*******************************************************************************
- * BL sizes
- ******************************************************************************/
-
-#define NRD_CSS_BL1_RW_SIZE UL(64 * 1024) /* 64KB */
-
-#if TRUSTED_BOARD_BOOT
-# define NRD_CSS_BL2_SIZE UL(0x28000)
-#else
-# define NRD_CSS_BL2_SIZE UL(0x14000)
-#endif
-
-/*
- * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
- * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2
- * and BL1-RW.
- */
-#define NRD_CSS_BL31_SIZE UL(116 * 1024) /* 116 KB */
-
-/*******************************************************************************
- * Console config
- ******************************************************************************/
-
-#define NRD_CSS_UART_CLK_IN_HZ UL(7372800)
-
-/*******************************************************************************
- * Watchdog config
- ******************************************************************************/
-
-#define NRD_CSS_WDOG_TIMEOUT UL(100)
-
-/*******************************************************************************
- * Platform ID
- ******************************************************************************/
-
-/* Platform ID address */
-#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
-#ifndef __ASSEMBLER__
-/* SSC_VERSION related accessors */
-/* Returns the part number of the platform */
-#define GET_NRD_PART_NUM \
- GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION))
-/* Returns the configuration number of the platform */
-#define GET_NRD_CONFIG_NUM \
- GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
-#endif /* __ASSEMBLER__ */
-
-/*******************************************************************************
- * MMU mappings
- ******************************************************************************/
-
-#define NRD_CSS_PERIPH_MMAP(n) \
- MAP_REGION_FLAT( \
- NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
- NRD_CSS_PERIPH_BASE, \
- NRD_CSS_PERIPH_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define NRD_CSS_SHARED_RAM_MMAP(n) \
- MAP_REGION_FLAT( \
- NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
- ARM_SHARED_RAM_BASE, \
- ARM_SHARED_RAM_SIZE, \
- MT_NON_CACHEABLE | MT_RW | MT_SECURE)
-
-#if SPM_MM
-/*
- * Stand-alone MM logs would be routed via secure UART. Define page table
- * entry for secure UART which would be common to all platforms.
- */
-#define NRD_CSS_SECURE_UART_MMAP \
- MAP_REGION_FLAT( \
- NRD_CSS_SEC_UART_BASE, \
- NRD_CSS_UART_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
-#endif
-
-#endif /* NRD_CSS_FW_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
deleted file mode 100644
index bca095c..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the platform port definitions for the
- * first generation platforms based on the A75, N1 and V1 CPUs.
- */
-
-#ifndef NRD_PLAT_ARM_DEF1_H
-#define NRD_PLAT_ARM_DEF1_H
-
-#ifndef __ASSEMBLER__
-#include <lib/mmio.h>
-#endif /* __ASSEMBLER__ */
-
-#include <lib/utils_def.h>
-#include <lib/xlat_tables/xlat_tables_defs.h>
-#include <plat/arm/board/common/v2m_def.h>
-#include <plat/arm/common/arm_def.h>
-#include <plat/arm/common/arm_spm_def.h>
-#include <plat/arm/css/common/css_def.h>
-#include <plat/arm/soc/common/soc_css_def.h>
-#include <plat/common/common_def.h>
-#include <nrd_css_fw_def1.h>
-#include <nrd_ros_fw_def1.h>
-
-/*******************************************************************************
- * Core count
- ******************************************************************************/
-
-#define PLATFORM_CORE_COUNT (NRD_CHIP_COUNT * \
- PLAT_ARM_CLUSTER_COUNT * \
- NRD_MAX_CPUS_PER_CLUSTER * \
- NRD_MAX_PE_PER_CPU)
-
-/*******************************************************************************
- * PA/VA config
- ******************************************************************************/
-
-#ifdef __aarch64__
-#define PLAT_PHY_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
- NRD_CHIP_COUNT)
-#define PLAT_VIRT_ADDR_SPACE_SIZE NRD_REMOTE_CHIP_MEM_OFFSET( \
- NRD_CHIP_COUNT)
-#else
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
-#endif
-
-/*******************************************************************************
- * XLAT definitions
- ******************************************************************************/
-
-#if defined(IMAGE_BL31)
-# if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
-# define PLAT_ARM_MMAP_ENTRIES (10 + ((NRD_CHIP_COUNT - 1) * 3))
-# define MAX_XLAT_TABLES (11 + ((NRD_CHIP_COUNT - 1) * 3))
-# define PLAT_SP_IMAGE_MMAP_REGIONS U(12)
-# define PLAT_SP_IMAGE_MAX_XLAT_TABLES U(14)
-# else
-# define PLAT_ARM_MMAP_ENTRIES (5 + ((NRD_CHIP_COUNT - 1) * 3))
-# define MAX_XLAT_TABLES (6 + ((NRD_CHIP_COUNT - 1) * 3))
-# endif
-#elif defined(IMAGE_BL32)
-# define PLAT_ARM_MMAP_ENTRIES U(8)
-# define MAX_XLAT_TABLES U(5)
-#elif defined(IMAGE_BL2)
-# define PLAT_ARM_MMAP_ENTRIES (11 + (NRD_CHIP_COUNT - 1))
-
-/*
- * MAX_XLAT_TABLES entries need to be doubled because when the address width
- * exceeds 40 bits an additional level of translation is required. In case of
- * multichip platforms peripherals also fall into address space with width
- * > 40 bits.
- */
-# define MAX_XLAT_TABLES (11 + ((NRD_CHIP_COUNT - 1) * 2))
-#elif !USE_ROMLIB
-# define PLAT_ARM_MMAP_ENTRIES U(11)
-# define MAX_XLAT_TABLES U(7)
-#else
-# define PLAT_ARM_MMAP_ENTRIES U(12)
-# define MAX_XLAT_TABLES U(6)
-#endif
-
-/*******************************************************************************
- * Stack size
- ******************************************************************************/
-
-#if defined(IMAGE_BL1)
-# if TRUSTED_BOARD_BOOT
-# define PLATFORM_STACK_SIZE U(0x1000)
-# else
-# define PLATFORM_STACK_SIZE U(0x440)
-# endif
-#elif defined(IMAGE_BL2)
-# if TRUSTED_BOARD_BOOT
-# define PLATFORM_STACK_SIZE U(0x1000)
-# else
-# define PLATFORM_STACK_SIZE U(0x400)
-# endif
-#elif defined(IMAGE_BL2U)
-# define PLATFORM_STACK_SIZE U(0x400)
-#elif defined(IMAGE_BL31)
-# if SPM_MM
-# define PLATFORM_STACK_SIZE U(0x500)
-# else
-# define PLATFORM_STACK_SIZE U(0x400)
-# endif
-#elif defined(IMAGE_BL32)
-# define PLATFORM_STACK_SIZE U(0x440)
-#endif
-
-#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP))
-/*
- * Secure partition stack follows right after the memory region that is shared
- * between EL3 and S-EL0.
- */
-#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
- PLAT_SP_IMAGE_NS_BUF_SIZE)
-#endif /* SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) */
-
-/*******************************************************************************
- * BL sizes
- ******************************************************************************/
-
-#if USE_ROMLIB
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0x1000)
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0xe000)
-#else
-#define PLAT_ARM_MAX_ROMLIB_RW_SIZE U(0)
-#define PLAT_ARM_MAX_ROMLIB_RO_SIZE U(0)
-#endif
-
-#define PLAT_ARM_MAX_BL1_RW_SIZE NRD_CSS_BL1_RW_SIZE
-
-/*
- * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
- * little space for growth. Additional 8KiB space is added per chip in
- * order to accommodate the additional level of translation required for "TZC"
- * peripheral access which lies in >4TB address space.
- *
- */
-#define PLAT_ARM_MAX_BL2_SIZE (NRD_CSS_BL2_SIZE + \
- ((NRD_CHIP_COUNT - 1) * 0x2000))
-
-#define PLAT_ARM_MAX_BL31_SIZE (NRD_CSS_BL31_SIZE + \
- PLAT_ARM_MAX_BL2_SIZE + \
- PLAT_ARM_MAX_BL1_RW_SIZE)
-
-/*******************************************************************************
- * ROM, SRAM and DRAM config
- ******************************************************************************/
-
-#define PLAT_ARM_TRUSTED_SRAM_SIZE NRD_CSS_TRUSTED_SRAM_SIZE
-
-#define PLAT_ARM_TRUSTED_ROM_BASE NRD_CSS_TRUSTED_ROM_BASE
-#define PLAT_ARM_TRUSTED_ROM_SIZE NRD_CSS_TRUSTED_ROM_SIZE
-
-#define PLAT_ARM_NSRAM_BASE NRD_CSS_NONTRUSTED_SRAM_BASE
-#define PLAT_ARM_NSRAM_SIZE NRD_CSS_NONTRUSTED_SRAM_SIZE
-
-#define PLAT_ARM_DRAM2_BASE NRD_CSS_DRAM2_BASE
-#define PLAT_ARM_DRAM2_SIZE NRD_CSS_DRAM2_SIZE
-
-/*******************************************************************************
- * Console config
- ******************************************************************************/
-
-#define PLAT_ARM_BOOT_UART_BASE NRD_CSS_SEC_UART_BASE
-#define PLAT_ARM_BOOT_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
-
-#define PLAT_ARM_RUN_UART_BASE NRD_CSS_SEC_UART_BASE
-#define PLAT_ARM_RUN_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
-
-#define PLAT_ARM_CRASH_UART_BASE NRD_CSS_SEC_UART_BASE
-#define PLAT_ARM_CRASH_UART_CLK_IN_HZ NRD_CSS_UART_CLK_IN_HZ
-
-/*******************************************************************************
- * Timer config
- ******************************************************************************/
-
-#define PLAT_ARM_NSTIMER_FRAME_ID (0)
-
-/*******************************************************************************
- * Power config
- ******************************************************************************/
-
-#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
-#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
-
-/*******************************************************************************
- * Flash config
- ******************************************************************************/
-
-#define PLAT_ARM_FLASH_IMAGE_BASE V2M_FLASH0_BASE
-#define PLAT_ARM_FLASH_IMAGE_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
-#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
- V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
-/* IO storage framework */
-#define MAX_IO_DEVICES U(3)
-#define MAX_IO_HANDLES U(4)
-
-/*******************************************************************************
- * SCMI config
- ******************************************************************************/
-
-/* Number of SCMI channels on the platform */
-#define PLAT_ARM_SCMI_CHANNEL_COUNT NRD_CHIP_COUNT
-
-/*******************************************************************************
- * SDS config
- ******************************************************************************/
-
-/* Index of SDS region used in the communication with SCP */
-#define SDS_SCP_AP_REGION_ID U(0)
-/* SDS ID for unusable CPU MPID list structure */
-#define SDS_ISOLATED_CPU_LIST_ID U(128)
-
-/*******************************************************************************
- * GIC/EHF config
- ******************************************************************************/
-
-#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
-#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
-#define PLAT_SP_PRI U(0x10)
-
-/*******************************************************************************
- * Platform type identification macro
- ******************************************************************************/
-
-/* Platform ID related accessors */
-#define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0f)
-#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x0)
-#define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02)
-
-#ifndef __ASSEMBLER__
-#define BOARD_CSS_GET_PLAT_TYPE(addr) \
- ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
- >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
-#endif /* __ASSEMBLER__ */
-
-/* Platform ID address */
-#define BOARD_CSS_PLAT_ID_REG_ADDR NRD_ROS_PLATFORM_BASE + \
- UL(0x00fe00e0)
-
-#endif /* NRD_PLAT_ARM_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
deleted file mode 100644
index b86ab21..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_def1.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the RoS specific definitions for the first
- * generation platforms based on the A75, N1 and V1 CPUs. RoS (Rest Of System)
- * is used to refer to the part of the reference design platform that excludes
- * CSS.
- */
-
-#ifndef NRD_ROS_DEF1_H
-#define NRD_ROS_DEF1_H
-
-/*******************************************************************************
- * ROS configs
- ******************************************************************************/
-
-/* RoS Peripherals */
-#define NRD_ROS_PERIPH_BASE UL(0x60000000)
-#define NRD_ROS_PERIPH_SIZE UL(0x20000000)
-
-/* System Reg */
-#define NRD_ROS_SYSTEMREG_BASE UL(0x1C010000)
-#define NRD_ROS_SYSTEMREG_SIZE UL(0x00010000)
-
-/* NOR Flash 2 */
-#define NRD_ROS_NOR2_FLASH_BASE UL(0x10000000)
-#define NRD_ROS_NOR2_FLASH_SIZE UL(0x04000000)
-
-/* RoS Platform */
-#define NRD_ROS_PLATFORM_BASE UL(0x7F000000)
-#define NRD_ROS_PLATFORM_SIZE UL(0x20000000)
-
-#endif /* NRD_ROS_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h
deleted file mode 100644
index c521043..0000000
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- *
- * This file is limited to include the RoS firmware specific definitions for the
- * first generation platforms based on the A75, N1 and V1 CPUs. RoS (Rest Of
- * System) is used to refer to the part of the reference design platform that
- * excludes CSS.
- */
-
-#ifndef NRD_ROS_FW_DEF1_H
-#define NRD_ROS_FW_DEF1_H
-
-#include <nrd_ros_def1.h>
-
-/*******************************************************************************
- * MMU mapping
- ******************************************************************************/
-
-#define NRD_ROS_PERIPH_MMAP(n) \
- MAP_REGION_FLAT( \
- NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
- NRD_ROS_PERIPH_BASE, \
- NRD_ROS_PERIPH_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE)
-
-#define NRD_ROS_SECURE_SYSTEMREG_USER_MMAP \
- MAP_REGION_FLAT( \
- NRD_ROS_SYSTEMREG_BASE, \
- NRD_ROS_SYSTEMREG_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
-
-#define NRD_ROS_SECURE_NOR2_USER_MMAP \
- MAP_REGION_FLAT( \
- NRD_ROS_NOR2_FLASH_BASE, \
- NRD_ROS_NOR2_FLASH_SIZE, \
- MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
-
-#define NRD_MAP_FLASH0_RO \
- MAP_REGION_FLAT( \
- V2M_FLASH0_BASE, \
- V2M_FLASH0_SIZE, \
- MT_DEVICE | MT_RO | MT_SECURE)
-
-/*******************************************************************************
- * TZ config
- ******************************************************************************/
-
-/*
- * Mapping definition of the TrustZone Controller for Arm Neoverse RD platforms
- * where both the DRAM regions are marked for non-secure access. This applies
- * to multi-chip platforms.
- */
-#define NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(n) \
- {NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \
- NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END, \
- ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \
- {NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \
- NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \
- ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
-
-#endif /* NRD_ROS_FW_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_variant.h b/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
index 86d82e2..901cbf1 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,16 +7,6 @@
#ifndef NRD_VARIANT_H
#define NRD_VARIANT_H
-/* SSC_VERSION values for SGI575 */
-#define SGI575_SSC_VER_PART_NUM 0x0783
-
-/* SID Version values for RD-N1E1-Edge */
-#define RD_N1E1_EDGE_SID_VER_PART_NUM 0x0786
-#define RD_E1_EDGE_CONFIG_ID 0x2
-
-/* SID Version values for RD-V1 */
-#define RD_V1_SID_VER_PART_NUM 0x078a
-
/* SID Version values for RD-N2 */
#define RD_N2_SID_VER_PART_NUM 0x07B7
diff --git a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
index bb89c04..3ad586b 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
@@ -24,14 +24,6 @@
nrd_platform_info_t nrd_plat_info;
-static scmi_channel_plat_info_t sgi575_scmi_plat_info = {
- .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
- .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF,
- .db_preserve_mask = 0xfffffffe,
- .db_modify_mask = 0x1,
- .ring_doorbell = &mhu_ring_doorbell,
-};
-
static scmi_channel_plat_info_t plat_rd_scmi_info[] = {
{
.scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE,
@@ -123,9 +115,7 @@
scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id)
{
- if (nrd_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM ||
- nrd_plat_info.platform_id == RD_V1_SID_VER_PART_NUM ||
- nrd_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
+ if (nrd_plat_info.platform_id == RD_N2_SID_VER_PART_NUM ||
nrd_plat_info.platform_id == RD_V2_SID_VER_PART_NUM ||
nrd_plat_info.platform_id == RD_N2_CFG1_SID_VER_PART_NUM ||
nrd_plat_info.platform_id == RD_N2_CFG3_SID_VER_PART_NUM) {
@@ -140,8 +130,6 @@
panic();
}
return &plat3_rd_scmi_info[channel_id];
- } else if (nrd_plat_info.platform_id == SGI575_SSC_VER_PART_NUM) {
- return &sgi575_scmi_plat_info;
} else {
panic();
}
@@ -267,19 +255,5 @@
const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
{
- /*
- * For RD-E1-Edge, only CPU power ON/OFF, PSCI platform callbacks are
- * supported.
- */
- if (((nrd_plat_info.platform_id == RD_N1E1_EDGE_SID_VER_PART_NUM) &&
- (nrd_plat_info.config_id == RD_E1_EDGE_CONFIG_ID))) {
- ops->cpu_standby = NULL;
- ops->system_off = NULL;
- ops->system_reset = NULL;
- ops->get_sys_suspend_power_state = NULL;
- ops->pwr_domain_suspend = NULL;
- ops->pwr_domain_suspend_finish = NULL;
- }
-
return css_scmi_override_pm_ops(ops);
}
diff --git a/plat/arm/board/neoverse_rd/common/nrd_interconnect.c b/plat/arm/board/neoverse_rd/common/nrd_interconnect.c
index 4f9cc85..af8980d 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_interconnect.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_interconnect.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,12 +8,6 @@
#include <common/debug.h>
#include <plat/arm/common/plat_arm.h>
-/*
- * For SGI575 which support FCM (with automatic interconnect enter/exit),
- * we should not do anything in these interface functions.
- * They are used to override the weak functions in cci drivers.
- */
-
/******************************************************************************
* Helper function to initialize ARM interconnect driver.
*****************************************************************************/
diff --git a/plat/arm/board/neoverse_rd/common/nrd_plat1.c b/plat/arm/board/neoverse_rd/common/nrd_plat1.c
deleted file mode 100644
index 32444f4..0000000
--- a/plat/arm/board/neoverse_rd/common/nrd_plat1.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include <platform_def.h>
-
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <drivers/arm/ccn.h>
-#include <drivers/arm/css/sds.h>
-#include <lib/utils_def.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-#include <drivers/arm/sbsa.h>
-
-#if SPM_MM
-#include <services/spm_mm_partition.h>
-#endif
-
-/*
- * Table of regions for different BL stages to map using the MMU.
- * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
- * arm_configure_mmu_elx() will give the available subset of that.
- *
- * Replace or extend the below regions as required
- */
-#if IMAGE_BL1
-const mmap_region_t plat_arm_mmap[] = {
- ARM_MAP_SHARED_RAM,
- NRD_MAP_FLASH0_RO,
- NRD_CSS_PERIPH_MMAP(0),
- NRD_ROS_PERIPH_MMAP(0),
- {0}
-};
-#endif
-#if IMAGE_BL2
-const mmap_region_t plat_arm_mmap[] = {
- ARM_MAP_SHARED_RAM,
- NRD_MAP_FLASH0_RO,
-#ifdef PLAT_ARM_MEM_PROT_ADDR
- ARM_V2M_MAP_MEM_PROTECT,
-#endif
- NRD_CSS_PERIPH_MMAP(0),
- NRD_ROS_PERIPH_MMAP(0),
- ARM_MAP_NS_DRAM1,
-#if NRD_CHIP_COUNT > 1
- NRD_CSS_PERIPH_MMAP(1),
-#endif
-#if NRD_CHIP_COUNT > 2
- NRD_CSS_PERIPH_MMAP(2),
-#endif
-#if NRD_CHIP_COUNT > 3
- NRD_CSS_PERIPH_MMAP(3),
-#endif
-#if ARM_BL31_IN_DRAM
- ARM_MAP_BL31_SEC_DRAM,
-#endif
-#if SPM_MM
- ARM_SP_IMAGE_MMAP,
-#endif
-#if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
- ARM_MAP_BL1_RW,
-#endif
- {0}
-};
-#endif
-#if IMAGE_BL31
-const mmap_region_t plat_arm_mmap[] = {
- ARM_MAP_SHARED_RAM,
- V2M_MAP_IOFPGA,
- NRD_CSS_PERIPH_MMAP(0),
-#ifdef PLAT_ARM_MEM_PROT_ADDR
- ARM_V2M_MAP_MEM_PROTECT,
-#endif
- NRD_ROS_PERIPH_MMAP(0),
-#if SPM_MM
- ARM_SPM_BUF_EL3_MMAP,
-#endif
- {0}
-};
-
-#if SPM_MM && defined(IMAGE_BL31)
-const mmap_region_t plat_arm_secure_partition_mmap[] = {
- NRD_ROS_SECURE_SYSTEMREG_USER_MMAP,
- NRD_ROS_SECURE_NOR2_USER_MMAP,
- NRD_CSS_SECURE_UART_MMAP,
- ARM_SP_IMAGE_MMAP,
- ARM_SP_IMAGE_NS_BUF_MMAP,
- ARM_SP_IMAGE_RW_MMAP,
- ARM_SPM_BUF_EL0_MMAP,
- {0}
-};
-#endif /* SPM_MM && defined(IMAGE_BL31) */
-#endif
-
-ARM_CASSERT_MMAP
-
-#if SPM_MM && defined(IMAGE_BL31)
-/*
- * Boot information passed to a secure partition during initialisation. Linear
- * indices in MP information will be filled at runtime.
- */
-static spm_mm_mp_info_t sp_mp_info[] = {
- [0] = {0x81000000, 0},
- [1] = {0x81000100, 0},
- [2] = {0x81000200, 0},
- [3] = {0x81000300, 0},
- [4] = {0x81010000, 0},
- [5] = {0x81010100, 0},
- [6] = {0x81010200, 0},
- [7] = {0x81010300, 0},
-};
-
-const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
- .h.type = PARAM_SP_IMAGE_BOOT_INFO,
- .h.version = VERSION_1,
- .h.size = sizeof(spm_mm_boot_info_t),
- .h.attr = 0,
- .sp_mem_base = ARM_SP_IMAGE_BASE,
- .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
- .sp_image_base = ARM_SP_IMAGE_BASE,
- .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
- .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
- .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
- .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
- .sp_image_size = ARM_SP_IMAGE_SIZE,
- .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
- .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
- .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
- .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
- .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
- .num_cpus = PLATFORM_CORE_COUNT,
- .mp_info = &sp_mp_info[0],
-};
-
-const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
-{
- return plat_arm_secure_partition_mmap;
-}
-
-const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
- void *cookie)
-{
- return &plat_arm_secure_partition_boot_info;
-}
-#endif /* SPM_MM && defined(IMAGE_BL31) */
-
-#if TRUSTED_BOARD_BOOT
-int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
-{
- assert(heap_addr != NULL);
- assert(heap_size != NULL);
-
- return arm_get_mbedtls_heap(heap_addr, heap_size);
-}
-#endif
-
-void plat_arm_secure_wdt_start(void)
-{
- sbsa_wdog_start(NRD_CSS_WDOG_BASE, NRD_CSS_WDOG_TIMEOUT);
-}
-
-void plat_arm_secure_wdt_stop(void)
-{
- sbsa_wdog_stop(NRD_CSS_WDOG_BASE);
-}
-
-static sds_region_desc_t nrd_sds_regions[] = {
- { .base = PLAT_ARM_SDS_MEM_BASE },
-};
-
-sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count)
-{
- *region_count = ARRAY_SIZE(nrd_sds_regions);
-
- return nrd_sds_regions;
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_fw_config.dts
deleted file mode 100644
index 085a42a..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_fw_config.dts
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/tbbr/tbbr_img_def.h>
-
-/dts-v1/;
-/ {
- dtb-registry {
- compatible = "fconf,dyn_cfg-dtb_registry";
-
- tb_fw-config {
- load-address = <0x0 0x4001300>;
- max-size = <0x200>;
- id = <TB_FW_CONFIG_ID>;
- };
-
- nt_fw-config {
- load-address = <0x0 0xFEF00000>;
- max-size = <0x0100000>;
- id = <NT_FW_CONFIG_ID>;
- };
- };
-};
-
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_nt_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_nt_fw_config.dts
deleted file mode 100644
index 3cef0d1..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_nt_fw_config.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
- /* compatible string */
- compatible = "arm,rd-n1edge";
-
- /*
- * Place holder for system-id node with default values. The
- * value of platform-id and config-id will be set to the
- * correct values during the BL2 stage of boot.
- */
- system-id {
- platform-id = <0x0>;
- config-id = <0x0>;
- multi-chip-mode = <0x0>;
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_tb_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_tb_fw_config.dts
deleted file mode 100644
index 78cd5a8..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/fdts/rdn1edge_tb_fw_config.dts
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
- tb_fw-config {
- compatible = "arm,tb_fw";
-
- /* Disable authentication for development */
- disable_auth = <0x0>;
-
- /*
- * The following two entries are placeholders for Mbed TLS
- * heap information. The default values don't matter since
- * they will be overwritten by BL1.
- * In case of having shared Mbed TLS heap between BL1 and BL2,
- * BL1 will populate these two properties with the respective
- * info about the shared heap. This info will be available for
- * BL2 in order to locate and re-use the heap.
- */
- mbedtls_heap_addr = <0x0 0x0>;
- mbedtls_heap_size = <0x0>;
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
deleted file mode 100644
index 5357c31..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <lib/utils_def.h>
-#include <nrd_css_fw_def1.h>
-#include <nrd_plat_arm_def1.h>
-#include <nrd_ros_fw_def1.h>
-#include <nrd_sdei.h>
-
-/* Remote chip address offset */
-#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
- ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
-
-#define PLAT_ARM_CLUSTER_COUNT U(2)
-#define NRD_MAX_CPUS_PER_CLUSTER U(4)
-#define NRD_MAX_PE_PER_CPU U(1)
-
-#define PLAT_CSS_MHU_BASE UL(0x45400000)
-
-/* Base address of DMC-620 instances */
-#define RDN1EDGE_DMC620_BASE0 UL(0x4e000000)
-#define RDN1EDGE_DMC620_BASE1 UL(0x4e100000)
-
-/* Virtual address used by dynamic mem_protect for chunk_base */
-#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000)
-
-/* Maximum number of address bits used per chip */
-#define NRD_ADDR_BITS_PER_CHIP U(42)
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE UL(0x30000000)
-#define PLAT_ARM_GICR_BASE UL(0x300C0000)
-
-/* GIC SPI range for multichip */
-#define NRD_CHIP0_SPI_MIN U(32)
-#define NRD_CHIP0_SPI_MAX U(991)
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
deleted file mode 100644
index 4892804..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/platform.mk
+++ /dev/null
@@ -1,83 +0,0 @@
-#
-# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# GIC-600 configuration
-GICV3_IMPL_GIC600_MULTICHIP := 1
-
-include plat/arm/board/neoverse_rd/common/nrd-common.mk
-
-RDN1EDGE_BASE = plat/arm/board/neoverse_rd/platform/rdn1edge
-
-PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include/nrd1/ \
- -I${RDN1EDGE_BASE}/include/
-
-NRD_CPU_SOURCES := lib/cpus/aarch64/neoverse_n1.S
-
-PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat1.c
-
-BL1_SOURCES += ${NRD_CPU_SOURCES} \
- ${RDN1EDGE_BASE}/rdn1edge_err.c
-
-BL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_plat.c \
- ${RDN1EDGE_BASE}/rdn1edge_security.c \
- ${RDN1EDGE_BASE}/rdn1edge_err.c \
- drivers/arm/tzc/tzc_dmc620.c \
- lib/utils/mem_region.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
-
-BL31_SOURCES += ${NRD_CPU_SOURCES} \
- ${RDN1EDGE_BASE}/rdn1edge_plat.c \
- ${RDN1EDGE_BASE}/rdn1edge_topology.c \
- drivers/cfi/v2m/v2m_flash.c \
- lib/utils/mem_region.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
-
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
-BL1_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c
-BL2_SOURCES += ${RDN1EDGE_BASE}/rdn1edge_trusted_boot.c
-endif
-
-# Enable dynamic addition of MMAP regions in BL31
-BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
-
-# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_fw_config.dts \
- ${RDN1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts
-FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
-TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
-
-# Add the FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
-# Add the TB_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
-
-FDT_SOURCES += ${RDN1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts
-NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
-
-# Add the NT_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
-
-$(eval $(call CREATE_SEQ,SEQ,2))
-ifneq ($(NRD_CHIP_COUNT),$(filter $(NRD_CHIP_COUNT),$(SEQ)))
- $(error "Chip count for RDN1Edge platform should be one of $(SEQ), currently \
- set to ${NRD_CHIP_COUNT}.")
-endif
-
-ifneq ($(NRD_PLATFORM_VARIANT),0)
- $(error "NRD_PLATFORM_VARIANT for RD-N1-Edge should always be 0, \
- currently set to ${NRD_PLATFORM_VARIANT}.")
-endif
-
-ifneq (${RESET_TO_BL31},0)
- $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
- Please set RESET_TO_BL31 to 0.")
-endif
-
-override CTX_INCLUDE_AARCH32_REGS := 0
-override SPMD_SPM_AT_SEL2 := 0
-
-# Enable the flag since RD-N1-EDGE has a system level cache
-NEOVERSE_Nx_EXTERNAL_LLC := 1
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_err.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_err.c
deleted file mode 100644
index 273e1f4..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_err.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * rdn1edge error handler
- */
-void __dead2 plat_arm_error_handler(int err)
-{
- while (true) {
- wfi();
- }
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
deleted file mode 100644
index 5cbdd5f..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_plat.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <drivers/arm/gic600_multichip.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-
-#include <nrd_plat.h>
-
-#define RT_OWNER 0
-
-#if defined(IMAGE_BL31)
-static const mmap_region_t rdn1edge_dynamic_mmap[] = {
- NRD_CSS_SHARED_RAM_MMAP(1),
- NRD_CSS_PERIPH_MMAP(1),
- NRD_ROS_PERIPH_MMAP(1)
-};
-
-static struct gic600_multichip_data rdn1e1_multichip_data __init = {
- .base_addrs = {
- PLAT_ARM_GICD_BASE
- },
- .rt_owner = RT_OWNER,
- .chip_count = NRD_CHIP_COUNT,
- .chip_addrs = {
- [RT_OWNER] = {
- PLAT_ARM_GICD_BASE >> 16,
- (PLAT_ARM_GICD_BASE
- + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16
- }
- },
- .spi_ids = {
- {PLAT_ARM_GICD_BASE,
- NRD_CHIP0_SPI_MIN,
- NRD_CHIP0_SPI_MAX},
- {0, 0, 0}
- }
-};
-
-static uintptr_t rdn1e1_multichip_gicr_frames[] = {
- PLAT_ARM_GICR_BASE, /* Chip 0's GICR Base */
- PLAT_ARM_GICR_BASE +
- NRD_REMOTE_CHIP_MEM_OFFSET(1), /* Chip 1's GICR BASE */
- UL(0) /* Zero Termination */
-};
-#endif /* IMAGE_BL31 */
-
-unsigned int plat_arm_nrd_get_platform_id(void)
-{
- return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
- & SID_SYSTEM_ID_PART_NUM_MASK;
-}
-
-unsigned int plat_arm_nrd_get_config_id(void)
-{
- return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
-}
-
-unsigned int plat_arm_nrd_get_multi_chip_mode(void)
-{
- return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
- SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
-}
-
-/*
- * IMAGE_BL31 macro is added to build bl31_platform_setup function only for BL31
- * because PLAT_XLAT_TABLES_DYNAMIC macro is set to build only for BL31 and not
- * for other stages.
- */
-#if defined(IMAGE_BL31)
-void bl31_platform_setup(void)
-{
- unsigned int i;
- int ret;
-
- if (plat_arm_nrd_get_multi_chip_mode() == 0 && NRD_CHIP_COUNT > 1) {
- ERROR("Chip Count is set to %d but multi-chip mode not enabled\n",
- NRD_CHIP_COUNT);
- panic();
- } else if (plat_arm_nrd_get_multi_chip_mode() == 1 &&
- NRD_CHIP_COUNT > 1) {
- INFO("Enabling support for multi-chip in RD-N1-Edge\n");
-
- for (i = 0; i < ARRAY_SIZE(rdn1edge_dynamic_mmap); i++) {
- ret = mmap_add_dynamic_region(
- rdn1edge_dynamic_mmap[i].base_pa,
- rdn1edge_dynamic_mmap[i].base_va,
- rdn1edge_dynamic_mmap[i].size,
- rdn1edge_dynamic_mmap[i].attr
- );
- if (ret != 0) {
- ERROR("Failed to add dynamic mmap entry\n");
- panic();
- }
- }
-
- plat_arm_override_gicr_frames(rdn1e1_multichip_gicr_frames);
- gic600_multichip_init(&rdn1e1_multichip_data);
- }
-
- nrd_bl31_common_platform_setup();
-}
-#endif /* IMAGE_BL31 */
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c
deleted file mode 100644
index f3f6238..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_security.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <nrd_dmc620_tzc_regions.h>
-
-uintptr_t rdn1edge_dmc_base[] = {
- RDN1EDGE_DMC620_BASE0,
- RDN1EDGE_DMC620_BASE1
-};
-
-static const tzc_dmc620_driver_data_t rdn1edge_plat_driver_data = {
- .dmc_base = rdn1edge_dmc_base,
- .dmc_count = ARRAY_SIZE(rdn1edge_dmc_base)
-};
-
-static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = {
- NRD_DMC620_TZC_REGIONS_DEF
-};
-
-static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = {
- .plat_drv_data = &rdn1edge_plat_driver_data,
- .plat_acc_addr_data = rdn1edge_acc_addr_data,
- .acc_addr_count = ARRAY_SIZE(rdn1edge_acc_addr_data)
-};
-
-/* Initialize the secure environment */
-void plat_arm_security_setup(void)
-{
- arm_tzc_dmc620_setup(&rdn1edge_plat_config_data);
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c
deleted file mode 100644
index 133eb16..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_topology.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-#include <plat/arm/css/common/css_pm.h>
-
-/******************************************************************************
- * The power domain tree descriptor.
- ******************************************************************************/
-static const unsigned char rdn1edge_pd_tree_desc[] = {
- (PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT),
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
-#if (NRD_CHIP_COUNT > 1)
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER
-#endif
-};
-
-/*******************************************************************************
- * This function returns the topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
- return rdn1edge_pd_tree_desc;
-}
-
-/*******************************************************************************
- * The array mapping platform core position (implemented by plat_my_core_pos())
- * to the SCMI power domain ID implemented by SCP.
- ******************************************************************************/
-const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
-#if (NRD_CHIP_COUNT > 1)
- (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
- (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
- (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
- (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
- (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x4)),
- (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x5)),
- (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x6)),
- (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x7)),
-#endif
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_trusted_boot.c b/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_trusted_boot.c
deleted file mode 100644
index 84622d0..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/rdn1edge_trusted_boot.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * Return the ROTPK hash in the following ASN.1 structure in DER format:
- *
- * AlgorithmIdentifier ::= SEQUENCE {
- * algorithm OBJECT IDENTIFIER,
- * parameters ANY DEFINED BY algorithm OPTIONAL
- * }
- *
- * DigestInfo ::= SEQUENCE {
- * digestAlgorithm AlgorithmIdentifier,
- * digest OCTET STRING
- * }
- */
-int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
- unsigned int *flags)
-{
- return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_fw_config.dts
deleted file mode 100644
index d443443..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_fw_config.dts
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/tbbr/tbbr_img_def.h>
-
-/dts-v1/;
-
-/ {
- dtb-registry {
- compatible = "fconf,dyn_cfg-dtb_registry";
-
- tb_fw-config {
- load-address = <0x0 0x4001300>;
- max-size = <0x200>;
- id = <TB_FW_CONFIG_ID>;
- };
-
- nt_fw-config {
- load-address = <0x0 0xFEF00000>;
- max-size = <0x0100000>;
- id = <NT_FW_CONFIG_ID>;
- };
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_nt_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_nt_fw_config.dts
deleted file mode 100644
index fb08885..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_nt_fw_config.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
- /* compatible string */
- compatible = "arm,rd-v1";
-
- /*
- * Place holder for system-id node with default values. The
- * value of platform-id and config-id will be set to the
- * correct values during the BL2 stage of boot.
- */
- system-id {
- platform-id = <0x0>;
- config-id = <0x0>;
- multi-chip-mode = <0x0>;
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_tb_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_tb_fw_config.dts
deleted file mode 100644
index c370623..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/fdts/rdv1_tb_fw_config.dts
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-
-/ {
- tb_fw-config {
- compatible = "arm,tb_fw";
-
- /* Disable authentication for development */
- disable_auth = <0x0>;
-
- /*
- * The following two entries are placeholders for Mbed TLS
- * heap information. The default values don't matter since
- * they will be overwritten by BL1.
- * In case of having shared Mbed TLS heap between BL1 and BL2,
- * BL1 will populate these two properties with the respective
- * info about the shared heap. This info will be available for
- * BL2 in order to locate and re-use the heap.
- */
- mbedtls_heap_addr = <0x0 0x0>;
- mbedtls_heap_size = <0x0>;
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
deleted file mode 100644
index cd40117..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <lib/utils_def.h>
-#include <nrd_css_fw_def1.h>
-#include <nrd_plat_arm_def1.h>
-#include <nrd_ros_fw_def1.h>
-
-/* Remote chip address offset */
-#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
- ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
-
-#define PLAT_ARM_CLUSTER_COUNT U(16)
-#define NRD_MAX_CPUS_PER_CLUSTER U(1)
-#define NRD_MAX_PE_PER_CPU U(1)
-
-#define PLAT_CSS_MHU_BASE UL(0x45400000)
-#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
-
-/* TZC Related Constants */
-#define PLAT_ARM_TZC_BASE UL(0x21830000)
-#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
-
-#define TZC400_OFFSET UL(0x1000000)
-#define TZC400_COUNT 4
-
-#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
- (n * TZC400_OFFSET))
-
-#define TZC_NSAID_ALL_AP U(0)
-#define TZC_NSAID_PCI U(1)
-#define TZC_NSAID_HDLCD0 U(2)
-#define TZC_NSAID_CLCD U(7)
-#define TZC_NSAID_AP U(9)
-#define TZC_NSAID_VIRTIO U(15)
-
-#define PLAT_ARM_TZC_NS_DEV_ACCESS \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
-
-/* Maximum number of address bits used per chip */
-#define NRD_ADDR_BITS_PER_CHIP U(42)
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE UL(0x30000000)
-#define PLAT_ARM_GICR_BASE UL(0x30140000)
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
deleted file mode 100644
index 241133f..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/platform.mk
+++ /dev/null
@@ -1,78 +0,0 @@
-# Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# RD-V1 platform uses GIC-700 which is based on GICv4.1
-GIC_ENABLE_V4_EXTN := 1
-
-include plat/arm/board/neoverse_rd/common/nrd-common.mk
-
-RDV1_BASE = plat/arm/board/neoverse_rd/platform/rdv1
-
-PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include/nrd1/ \
- -I${RDV1_BASE}/include/
-
-NRD_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S
-
-PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat1.c
-
-BL1_SOURCES += ${NRD_CPU_SOURCES} \
- ${RDV1_BASE}/rdv1_err.c
-
-BL2_SOURCES += ${RDV1_BASE}/rdv1_plat.c \
- ${RDV1_BASE}/rdv1_security.c \
- ${RDV1_BASE}/rdv1_err.c \
- lib/utils/mem_region.c \
- drivers/arm/tzc/tzc400.c \
- plat/arm/common/arm_tzc400.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
-
-BL31_SOURCES += ${NRD_CPU_SOURCES} \
- ${RDV1_BASE}/rdv1_plat.c \
- ${RDV1_BASE}/rdv1_topology.c \
- drivers/cfi/v2m/v2m_flash.c \
- lib/utils/mem_region.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
-
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
-BL1_SOURCES += ${RDV1_BASE}/rdv1_trusted_boot.c
-BL2_SOURCES += ${RDV1_BASE}/rdv1_trusted_boot.c
-endif
-
-# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES += ${RDV1_BASE}/fdts/${PLAT}_fw_config.dts \
- ${RDV1_BASE}/fdts/${PLAT}_tb_fw_config.dts
-FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
-TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
-
-# Add the FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
-# Add the TB_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
-
-FDT_SOURCES += ${RDV1_BASE}/fdts/${PLAT}_nt_fw_config.dts
-NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
-
-# Add the NT_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
-
-override CTX_INCLUDE_AARCH32_REGS := 0
-override ENABLE_FEAT_AMU := 2
-override SPMD_SPM_AT_SEL2 := 0
-
-# FEAT_SVE related flags
-override SVE_VECTOR_LEN := 256
-
-ifneq ($(NRD_PLATFORM_VARIANT),0)
- $(error "NRD_PLATFORM_VARIANT for RD-V1 should always be 0, \
- currently set to ${NRD_PLATFORM_VARIANT}.")
-endif
-
-ifneq (${RESET_TO_BL31},0)
- $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
- Please set RESET_TO_BL31 to 0.")
-endif
-
-# Enable the flag since RD-V1 has a system level cache
-NEOVERSE_Nx_EXTERNAL_LLC := 1
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_err.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_err.c
deleted file mode 100644
index d75f525..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_err.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * rdv1 error handler
- */
-void __dead2 plat_arm_error_handler(int err)
-{
- while (1) {
- wfi();
- }
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_plat.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_plat.c
deleted file mode 100644
index 7cdc19a..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_plat.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/common/platform.h>
-
-#include <nrd_plat.h>
-
-unsigned int plat_arm_nrd_get_platform_id(void)
-{
- return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
- & SID_SYSTEM_ID_PART_NUM_MASK;
-}
-
-unsigned int plat_arm_nrd_get_config_id(void)
-{
- return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
-}
-
-unsigned int plat_arm_nrd_get_multi_chip_mode(void)
-{
- return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
- SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
-}
-
-void bl31_platform_setup(void)
-{
- nrd_bl31_common_platform_setup();
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_security.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_security.c
deleted file mode 100644
index a936a71..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_security.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-#include <platform_def.h>
-
-static const arm_tzc_regions_info_t tzc_regions[] = {
- ARM_TZC_REGIONS_DEF,
- {}
-};
-
-/* Initialize the secure environment */
-void plat_arm_security_setup(void)
-{
- int i;
-
- for (i = 0; i < TZC400_COUNT; i++)
- arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c
deleted file mode 100644
index 20e4266..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_topology.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-#include <plat/arm/css/common/css_pm.h>
-
-/******************************************************************************
- * The power domain tree descriptor.
- ******************************************************************************/
-const unsigned char rd_v1_pd_tree_desc[] = {
- PLAT_ARM_CLUSTER_COUNT,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER
-};
-
-/*******************************************************************************
- * This function returns the topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
- return rd_v1_pd_tree_desc;
-}
-
-/*******************************************************************************
- * The array mapping platform core position (implemented by plat_my_core_pos())
- * to the SCMI power domain ID implemented by SCP.
- ******************************************************************************/
-const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x7)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x8)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x9)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xA)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xB)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xC)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xD)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xE)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF))
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_trusted_boot.c b/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_trusted_boot.c
deleted file mode 100644
index 84622d0..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1/rdv1_trusted_boot.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * Return the ROTPK hash in the following ASN.1 structure in DER format:
- *
- * AlgorithmIdentifier ::= SEQUENCE {
- * algorithm OBJECT IDENTIFIER,
- * parameters ANY DEFINED BY algorithm OPTIONAL
- * }
- *
- * DigestInfo ::= SEQUENCE {
- * digestAlgorithm AlgorithmIdentifier,
- * digest OCTET STRING
- * }
- */
-int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
- unsigned int *flags)
-{
- return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_fw_config.dts
deleted file mode 100644
index d443443..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_fw_config.dts
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/tbbr/tbbr_img_def.h>
-
-/dts-v1/;
-
-/ {
- dtb-registry {
- compatible = "fconf,dyn_cfg-dtb_registry";
-
- tb_fw-config {
- load-address = <0x0 0x4001300>;
- max-size = <0x200>;
- id = <TB_FW_CONFIG_ID>;
- };
-
- nt_fw-config {
- load-address = <0x0 0xFEF00000>;
- max-size = <0x0100000>;
- id = <NT_FW_CONFIG_ID>;
- };
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_nt_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_nt_fw_config.dts
deleted file mode 100644
index 78fa31e..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_nt_fw_config.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
- /* compatible string */
- compatible = "arm,rd-v1-mc";
-
- /*
- * Place holder for system-id node with default values. The
- * value of platform-id and config-id will be set to the
- * correct values during the BL2 stage of boot.
- */
- system-id {
- platform-id = <0x0>;
- config-id = <0x0>;
- multi-chip-mode = <0x0>;
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_tb_fw_config.dts b/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_tb_fw_config.dts
deleted file mode 100644
index c370623..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/fdts/rdv1mc_tb_fw_config.dts
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-
-/ {
- tb_fw-config {
- compatible = "arm,tb_fw";
-
- /* Disable authentication for development */
- disable_auth = <0x0>;
-
- /*
- * The following two entries are placeholders for Mbed TLS
- * heap information. The default values don't matter since
- * they will be overwritten by BL1.
- * In case of having shared Mbed TLS heap between BL1 and BL2,
- * BL1 will populate these two properties with the respective
- * info about the shared heap. This info will be available for
- * BL2 in order to locate and re-use the heap.
- */
- mbedtls_heap_addr = <0x0 0x0>;
- mbedtls_heap_size = <0x0>;
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
deleted file mode 100644
index b4c5c0a..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <lib/utils_def.h>
-#include <nrd_css_fw_def1.h>
-#include <nrd_plat_arm_def1.h>
-#include <nrd_ros_fw_def1.h>
-
-/* Remote chip address offset */
-#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
- ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
-
-#define PLAT_ARM_CLUSTER_COUNT U(4)
-#define NRD_MAX_CPUS_PER_CLUSTER U(1)
-#define NRD_MAX_PE_PER_CPU U(1)
-
-#define PLAT_CSS_MHU_BASE UL(0x45400000)
-#define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE
-
-/* TZC Related Constants */
-#define PLAT_ARM_TZC_BASE UL(0x21830000)
-#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
- (n * TZC400_OFFSET))
-#define TZC400_OFFSET UL(0x1000000)
-#define TZC400_COUNT U(8)
-#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
-
-#define TZC_NSAID_ALL_AP U(0)
-#define TZC_NSAID_PCI U(1)
-#define TZC_NSAID_HDLCD0 U(2)
-#define TZC_NSAID_CLCD U(7)
-#define TZC_NSAID_AP U(9)
-#define TZC_NSAID_VIRTIO U(15)
-
-#define PLAT_ARM_TZC_NS_DEV_ACCESS \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_HDLCD0)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_PCI)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_AP)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_CLCD)) | \
- (TZC_REGION_ACCESS_RDWR(TZC_NSAID_VIRTIO))
-
-/* Virtual address used by dynamic mem_protect for chunk_base */
-#define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xC0000000)
-
-/* Remote chip address offset (4TB per chip) */
-#define NRD_ADDR_BITS_PER_CHIP U(42)
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE UL(0x30000000)
-#define PLAT_ARM_GICR_BASE UL(0x30140000)
-
-/* GIC SPI range for multichip */
-#define NRD_CHIP0_SPI_MIN U(32)
-#define NRD_CHIP0_SPI_MAX U(991)
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
deleted file mode 100644
index 7af0bd8..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/platform.mk
+++ /dev/null
@@ -1,89 +0,0 @@
-# Copyright (c) 2020-2025, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# Enable GICv4 extension with multichip driver
-GIC_ENABLE_V4_EXTN := 1
-GICV3_IMPL_GIC600_MULTICHIP := 1
-
-include plat/arm/board/neoverse_rd/common/nrd-common.mk
-
-RDV1MC_BASE = plat/arm/board/neoverse_rd/platform/rdv1mc
-
-PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include/nrd1/ \
- -I${RDV1MC_BASE}/include/
-
-NRD_CPU_SOURCES := lib/cpus/aarch64/neoverse_v1.S
-
-PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat1.c
-
-BL1_SOURCES += ${NRD_CPU_SOURCES} \
- ${RDV1MC_BASE}/rdv1mc_err.c
-
-BL2_SOURCES += ${RDV1MC_BASE}/rdv1mc_plat.c \
- ${RDV1MC_BASE}/rdv1mc_security.c \
- ${RDV1MC_BASE}/rdv1mc_err.c \
- drivers/arm/tzc/tzc400.c \
- plat/arm/common/arm_tzc400.c \
- lib/utils/mem_region.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
-
-BL31_SOURCES += ${NRD_CPU_SOURCES} \
- ${RDV1MC_BASE}/rdv1mc_plat.c \
- ${RDV1MC_BASE}/rdv1mc_topology.c \
- drivers/cfi/v2m/v2m_flash.c \
- drivers/arm/gic/v3/gic600_multichip.c \
- lib/utils/mem_region.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
-
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
-BL1_SOURCES += ${RDV1MC_BASE}/rdv1mc_trusted_boot.c
-BL2_SOURCES += ${RDV1MC_BASE}/rdv1mc_trusted_boot.c
-endif
-
-# Enable dynamic addition of MMAP regions in BL31
-BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
-
-# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES += ${RDV1MC_BASE}/fdts/${PLAT}_fw_config.dts \
- ${RDV1MC_BASE}/fdts/${PLAT}_tb_fw_config.dts
-FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
-TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
-
-# Add the FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
-# Add the TB_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
-
-$(eval $(call CREATE_SEQ,SEQ,4))
-ifneq ($(NRD_CHIP_COUNT),$(filter $(NRD_CHIP_COUNT),$(SEQ)))
- $(error "Chip count for RD-V1-MC should be either $(SEQ) \
- currently it is set to ${NRD_CHIP_COUNT}.")
-endif
-
-FDT_SOURCES += ${RDV1MC_BASE}/fdts/${PLAT}_nt_fw_config.dts
-NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
-
-# Add the NT_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
-
-override CTX_INCLUDE_AARCH32_REGS := 0
-override ENABLE_FEAT_AMU := 2
-override SPMD_SPM_AT_SEL2 := 0
-
-# FEAT_SVE related flags
-override SVE_VECTOR_LEN := 256
-
-ifneq ($(NRD_PLATFORM_VARIANT),0)
- $(error "NRD_PLATFORM_VARIANT for RD-V1-MC should always be 0, \
- currently set to ${NRD_PLATFORM_VARIANT}.")
-endif
-
-ifneq (${RESET_TO_BL31},0)
- $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
- Please set RESET_TO_BL31 to 0.")
-endif
-
-# Enable the flag since RD-V1-MC has a system level cache
-NEOVERSE_Nx_EXTERNAL_LLC := 1
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_err.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_err.c
deleted file mode 100644
index b855edd..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_err.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * rdv1mc error handler
- */
-void __dead2 plat_arm_error_handler(int err)
-{
- while (true) {
- wfi();
- }
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
deleted file mode 100644
index 0a40762..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_plat.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <drivers/arm/gic600_multichip.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/common/platform.h>
-
-#include <nrd_plat.h>
-
-#define RT_OWNER 0
-
-#if defined(IMAGE_BL31)
-static const mmap_region_t rdv1mc_dynamic_mmap[] = {
- NRD_CSS_SHARED_RAM_MMAP(1),
- NRD_CSS_PERIPH_MMAP(1),
- NRD_ROS_PERIPH_MMAP(1),
-#if (NRD_CHIP_COUNT > 2)
- NRD_CSS_SHARED_RAM_MMAP(2),
- NRD_CSS_PERIPH_MMAP(2),
- NRD_ROS_PERIPH_MMAP(2),
-#endif
-#if (NRD_CHIP_COUNT > 3)
- NRD_CSS_SHARED_RAM_MMAP(3),
- NRD_CSS_PERIPH_MMAP(3),
- NRD_ROS_PERIPH_MMAP(3)
-#endif
-};
-
-static struct gic600_multichip_data rdv1mc_multichip_data __init = {
- .base_addrs = {
- PLAT_ARM_GICD_BASE
- },
- .rt_owner = RT_OWNER,
- .chip_count = NRD_CHIP_COUNT,
- .chip_addrs = {
- [RT_OWNER] = {
- PLAT_ARM_GICD_BASE >> 16,
- (PLAT_ARM_GICD_BASE
- + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
-#if (NRD_CHIP_COUNT > 2)
- (PLAT_ARM_GICD_BASE
- + NRD_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
-#endif
-#if (NRD_CHIP_COUNT > 3)
- (PLAT_ARM_GICD_BASE
- + NRD_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
-#endif
- }
- },
- .spi_ids = {
- {PLAT_ARM_GICD_BASE,
- NRD_CHIP0_SPI_MIN,
- NRD_CHIP0_SPI_MAX},
- {0, 0, 0},
-#if (NRD_CHIP_COUNT > 2)
- {0, 0, 0},
-#endif
-#if (NRD_CHIP_COUNT > 3)
- {0, 0, 0},
-#endif
- }
-};
-
-static uintptr_t rdv1mc_multichip_gicr_frames[] = {
- /* Chip 0's GICR Base */
- PLAT_ARM_GICR_BASE,
- /* Chip 1's GICR BASE */
- PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1),
-#if (NRD_CHIP_COUNT > 2)
- /* Chip 2's GICR BASE */
- PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2),
-#endif
-#if (NRD_CHIP_COUNT > 3)
- /* Chip 3's GICR BASE */
- PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3),
-#endif
- UL(0) /* Zero Termination */
-};
-#endif /* IMAGE_BL31 */
-
-unsigned int plat_arm_nrd_get_platform_id(void)
-{
- return mmio_read_32(SID_REG_BASE + SID_SYSTEM_ID_OFFSET)
- & SID_SYSTEM_ID_PART_NUM_MASK;
-}
-
-unsigned int plat_arm_nrd_get_config_id(void)
-{
- return mmio_read_32(SID_REG_BASE + SID_SYSTEM_CFG_OFFSET);
-}
-
-unsigned int plat_arm_nrd_get_multi_chip_mode(void)
-{
- return (mmio_read_32(SID_REG_BASE + SID_NODE_ID_OFFSET) &
- SID_MULTI_CHIP_MODE_MASK) >> SID_MULTI_CHIP_MODE_SHIFT;
-}
-
-/*
- * bl31_platform_setup_function is guarded by IMAGE_BL31 macro because
- * PLAT_XLAT_TABLES_DYNAMIC macro is set to build only for BL31 and not
- * for other stages.
- */
-#if defined(IMAGE_BL31)
-void bl31_platform_setup(void)
-{
- int ret;
- unsigned int i;
-
- if ((plat_arm_nrd_get_multi_chip_mode() == 0) &&
- (NRD_CHIP_COUNT > 1)) {
- ERROR("Chip Count is %u but multi-chip mode is not enabled\n",
- NRD_CHIP_COUNT);
- panic();
- } else if ((plat_arm_nrd_get_multi_chip_mode() == 1) &&
- (NRD_CHIP_COUNT > 1)) {
- INFO("Enabling support for multi-chip in RD-V1-MC\n");
-
- for (i = 0; i < ARRAY_SIZE(rdv1mc_dynamic_mmap); i++) {
- ret = mmap_add_dynamic_region(
- rdv1mc_dynamic_mmap[i].base_pa,
- rdv1mc_dynamic_mmap[i].base_va,
- rdv1mc_dynamic_mmap[i].size,
- rdv1mc_dynamic_mmap[i].attr);
- if (ret != 0) {
- ERROR("Failed to add dynamic mmap entry "
- "(ret=%d)\n", ret);
- panic();
- }
- }
-
- plat_arm_override_gicr_frames(
- rdv1mc_multichip_gicr_frames);
- gic600_multichip_init(&rdv1mc_multichip_data);
- }
-
- nrd_bl31_common_platform_setup();
-}
-#endif /* IMAGE_BL31 */
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
deleted file mode 100644
index 1e59831..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_security.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <plat/arm/common/plat_arm.h>
-#include <platform_def.h>
-
-/* TZC memory regions for the first chip */
-static const arm_tzc_regions_info_t tzc_regions[] = {
- ARM_TZC_REGIONS_DEF,
- {}
-};
-
-#if NRD_CHIP_COUNT > 1
-static const arm_tzc_regions_info_t tzc_regions_mc[][NRD_CHIP_COUNT - 1] = {
- {
- /* TZC memory regions for second chip */
- NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(1),
- {}
- },
-#if NRD_CHIP_COUNT > 2
- {
- /* TZC memory regions for third chip */
- NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(2),
- {}
- },
-#endif
-#if NRD_CHIP_COUNT > 3
- {
- /* TZC memory regions for fourth chip */
- NRD_ROS_TZC_NS_REMOTE_REGIONS_DEF(3),
- {}
- },
-#endif
-};
-#endif /* NRD_CHIP_COUNT */
-
-/* Initialize the secure environment */
-void plat_arm_security_setup(void)
-{
- unsigned int i;
-
- INFO("Configuring TrustZone Controller for Chip 0\n");
-
- for (i = 0; i < TZC400_COUNT; i++) {
- arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
- }
-
-#if NRD_CHIP_COUNT > 1
- unsigned int j;
-
- for (i = 1; i < NRD_CHIP_COUNT; i++) {
- INFO("Configuring TrustZone Controller for Chip %u\n", i);
-
- for (j = 0; j < TZC400_COUNT; j++) {
- arm_tzc400_setup(NRD_REMOTE_CHIP_MEM_OFFSET(i)
- + TZC400_BASE(j), tzc_regions_mc[i-1]);
- }
- }
-#endif
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c
deleted file mode 100644
index 52514ca..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_topology.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/debug.h>
-#include <plat/arm/common/plat_arm.h>
-#include <plat/arm/css/common/css_pm.h>
-
-#include <nrd_variant.h>
-
-/******************************************************************************
- * The power domain tree descriptor.
- ******************************************************************************/
-const unsigned char rd_v1_mc_pd_tree_desc_multi_chip[] = {
- ((PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT)),
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
-#if (NRD_CHIP_COUNT > 1)
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
-#endif
-#if (NRD_CHIP_COUNT > 2)
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
-#endif
-#if (NRD_CHIP_COUNT > 3)
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER
-#endif
-};
-
-/*******************************************************************************
- * This function returns the topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
- if (plat_arm_nrd_get_multi_chip_mode() == 1)
- return rd_v1_mc_pd_tree_desc_multi_chip;
- panic();
-}
-
-/*******************************************************************************
- * The array mapping platform core position (implemented by plat_my_core_pos())
- * to the SCMI power domain ID implemented by SCP.
- ******************************************************************************/
-const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
- (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
-#if (NRD_CHIP_COUNT > 1)
- (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
- (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
- (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
- (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
-#endif
-#if (NRD_CHIP_COUNT > 2)
- (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)),
- (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)),
- (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)),
- (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)),
-#endif
-#if (NRD_CHIP_COUNT > 3)
- (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)),
- (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)),
- (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)),
- (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x3))
-#endif
-};
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_trusted_boot.c b/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_trusted_boot.c
deleted file mode 100644
index 84622d0..0000000
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/rdv1mc_trusted_boot.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * Return the ROTPK hash in the following ASN.1 structure in DER format:
- *
- * AlgorithmIdentifier ::= SEQUENCE {
- * algorithm OBJECT IDENTIFIER,
- * parameters ANY DEFINED BY algorithm OPTIONAL
- * }
- *
- * DigestInfo ::= SEQUENCE {
- * digestAlgorithm AlgorithmIdentifier,
- * digest OCTET STRING
- * }
- */
-int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
- unsigned int *flags)
-{
- return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
-}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common_measured_boot.c b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common_measured_boot.c
index f5160ce..c3abc4f 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common_measured_boot.c
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/rdv3_common_measured_boot.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -34,7 +34,7 @@
return err;
}
-int plat_mboot_measure_key(void *pk_oid, void *pk_ptr, unsigned int pk_len)
+int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr, unsigned int pk_len)
{
return rse_mboot_set_signer_id(rdv3_rse_mboot_metadata, pk_oid,
pk_ptr, pk_len);
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_fw_config.dts b/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_fw_config.dts
deleted file mode 100644
index fe62b6d..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_fw_config.dts
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common/tbbr/tbbr_img_def.h>
-
-/dts-v1/;
-
-/ {
- dtb-registry {
- compatible = "fconf,dyn_cfg-dtb_registry";
-
- tb_fw-config {
- load-address = <0x0 0x4001300>;
- max-size = <0x200>;
- id = <TB_FW_CONFIG_ID>;
- };
-
- nt_fw-config {
- load-address = <0x0 0xFEF00000>;
- max-size = <0x0100000>;
- id = <NT_FW_CONFIG_ID>;
- };
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_nt_fw_config.dts b/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_nt_fw_config.dts
deleted file mode 100644
index 0573488..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_nt_fw_config.dts
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
- /* compatible string */
- compatible = "arm,sgi575";
-
- /*
- * Place holder for system-id node with default values. The
- * value of platform-id and config-id will be set to the
- * correct values during the BL2 stage of boot.
- */
- system-id {
- platform-id = <0x0>;
- config-id = <0x0>;
- multi-chip-mode = <0x0>;
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_tb_fw_config.dts b/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_tb_fw_config.dts
deleted file mode 100644
index c370623..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/fdts/sgi575_tb_fw_config.dts
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-
-/ {
- tb_fw-config {
- compatible = "arm,tb_fw";
-
- /* Disable authentication for development */
- disable_auth = <0x0>;
-
- /*
- * The following two entries are placeholders for Mbed TLS
- * heap information. The default values don't matter since
- * they will be overwritten by BL1.
- * In case of having shared Mbed TLS heap between BL1 and BL2,
- * BL1 will populate these two properties with the respective
- * info about the shared heap. This info will be available for
- * BL2 in order to locate and re-use the heap.
- */
- mbedtls_heap_addr = <0x0 0x0>;
- mbedtls_heap_size = <0x0>;
- };
-};
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
deleted file mode 100644
index 0797017..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef PLATFORM_DEF_H
-#define PLATFORM_DEF_H
-
-#include <lib/utils_def.h>
-#include <nrd_css_fw_def1.h>
-#include <nrd_plat_arm_def1.h>
-#include <nrd_ros_fw_def1.h>
-#include <nrd_sdei.h>
-
-/* Remote chip address offset */
-#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
- ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
-
-#define PLAT_ARM_CLUSTER_COUNT U(2)
-#define NRD_MAX_CPUS_PER_CLUSTER U(4)
-#define NRD_MAX_PE_PER_CPU U(1)
-
-#define PLAT_CSS_MHU_BASE UL(0x45000000)
-
-/* Base address of DMC-620 instances */
-#define SGI575_DMC620_BASE0 UL(0x4e000000)
-#define SGI575_DMC620_BASE1 UL(0x4e100000)
-
-/* Maximum number of address bits used per chip */
-#define NRD_ADDR_BITS_PER_CHIP U(36)
-
-/* GIC related constants */
-#define PLAT_ARM_GICD_BASE UL(0x30000000)
-#define PLAT_ARM_GICR_BASE UL(0x300C0000)
-
-#endif /* PLATFORM_DEF_H */
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk b/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
deleted file mode 100644
index 1f40107..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/platform.mk
+++ /dev/null
@@ -1,73 +0,0 @@
-#
-# Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-include plat/arm/board/neoverse_rd/common/nrd-common.mk
-
-SGI575_BASE = plat/arm/board/neoverse_rd/platform/sgi575
-
-PLAT_INCLUDES += -I${NRD_COMMON_BASE}/include/nrd1/ \
- -I${SGI575_BASE}/include/
-
-NRD_CPU_SOURCES := lib/cpus/aarch64/cortex_a75.S
-
-PLAT_BL_COMMON_SOURCES += ${NRD_COMMON_BASE}/nrd_plat1.c
-
-BL1_SOURCES += ${NRD_CPU_SOURCES} \
- ${SGI575_BASE}/sgi575_err.c
-
-BL2_SOURCES += ${SGI575_BASE}/sgi575_plat.c \
- ${SGI575_BASE}/sgi575_security.c \
- ${SGI575_BASE}/sgi575_err.c \
- drivers/arm/tzc/tzc_dmc620.c \
- lib/utils/mem_region.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
-
-BL31_SOURCES += ${NRD_CPU_SOURCES} \
- ${SGI575_BASE}/sgi575_plat.c \
- ${SGI575_BASE}/sgi575_topology.c \
- drivers/cfi/v2m/v2m_flash.c \
- lib/utils/mem_region.c \
- plat/arm/common/arm_nor_psci_mem_protect.c
-
-ifeq (${TRUSTED_BOARD_BOOT}, 1)
-BL1_SOURCES += ${SGI575_BASE}/sgi575_trusted_boot.c
-BL2_SOURCES += ${SGI575_BASE}/sgi575_trusted_boot.c
-endif
-
-# Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES += ${SGI575_BASE}/fdts/${PLAT}_fw_config.dts \
- ${SGI575_BASE}/fdts/${PLAT}_tb_fw_config.dts
-
-FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
-TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
-
-# Add the FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
-# Add the TB_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
-
-FDT_SOURCES += ${SGI575_BASE}/fdts/${PLAT}_nt_fw_config.dts
-NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
-
-# Add the NT_FW_CONFIG to FIP and specify the same to certtool
-$(eval $(call TOOL_ADD_PAYLOAD,${NT_FW_CONFIG},--nt-fw-config,${NT_FW_CONFIG}))
-
-ifneq ($(NRD_CHIP_COUNT),1)
- $(error "Chip count for SGI575 should be 1, currently set to \
- ${NRD_CHIP_COUNT}.")
-endif
-
-ifneq ($(NRD_PLATFORM_VARIANT),0)
- $(error "NRD_PLATFORM_VARIANT for SGI575 should always be 0,\
- currently set to ${NRD_PLATFORM_VARIANT}.")
-endif
-
-ifneq (${RESET_TO_BL31},0)
- $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
- Please set RESET_TO_BL31 to 0.")
-endif
-
-override SPMD_SPM_AT_SEL2 := 0
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_err.c b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_err.c
deleted file mode 100644
index 7e656ab..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_err.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * sgi575 error handler
- */
-void __dead2 plat_arm_error_handler(int err)
-{
- while (true) {
- wfi();
- }
-}
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_plat.c b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_plat.c
deleted file mode 100644
index 8b74616..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_plat.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/common/platform.h>
-
-#include <nrd_plat.h>
-#include <nrd_variant.h>
-
-unsigned int plat_arm_nrd_get_platform_id(void)
-{
- return mmio_read_32(SSC_VERSION) & SSC_VERSION_PART_NUM_MASK;
-}
-
-unsigned int plat_arm_nrd_get_config_id(void)
-{
- return (mmio_read_32(SSC_VERSION) >> SSC_VERSION_CONFIG_SHIFT)
- & SSC_VERSION_CONFIG_MASK;
-}
-
-unsigned int plat_arm_nrd_get_multi_chip_mode(void)
-{
- return 0;
-}
-
-void bl31_platform_setup(void)
-{
- nrd_bl31_common_platform_setup();
-}
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_security.c b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_security.c
deleted file mode 100644
index 8b8a382..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_security.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <nrd_dmc620_tzc_regions.h>
-
-uintptr_t sgi575_dmc_base[] = {
- SGI575_DMC620_BASE0,
- SGI575_DMC620_BASE1
-};
-
-static const tzc_dmc620_driver_data_t sgi575_plat_driver_data = {
- .dmc_base = sgi575_dmc_base,
- .dmc_count = ARRAY_SIZE(sgi575_dmc_base)
-};
-
-static const tzc_dmc620_acc_addr_data_t sgi575_acc_addr_data[] = {
- NRD_DMC620_TZC_REGIONS_DEF
-};
-
-static const tzc_dmc620_config_data_t sgi575_plat_config_data = {
- .plat_drv_data = &sgi575_plat_driver_data,
- .plat_acc_addr_data = sgi575_acc_addr_data,
- .acc_addr_count = ARRAY_SIZE(sgi575_acc_addr_data)
-};
-
-/* Initialize the secure environment */
-void plat_arm_security_setup(void)
-{
- arm_tzc_dmc620_setup(&sgi575_plat_config_data);
-}
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_topology.c b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_topology.c
deleted file mode 100644
index 15ffc65..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_topology.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (c) 2019-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/******************************************************************************
- * The power domain tree descriptor.
- ******************************************************************************/
-static const unsigned char sgi575_pd_tree_desc[] = {
- PLAT_ARM_CLUSTER_COUNT,
- NRD_MAX_CPUS_PER_CLUSTER,
- NRD_MAX_CPUS_PER_CLUSTER
-};
-
-/*******************************************************************************
- * This function returns the topology tree information.
- ******************************************************************************/
-const unsigned char *plat_get_power_domain_tree_desc(void)
-{
- return sgi575_pd_tree_desc;
-}
-
-/*******************************************************************************
- * The array mapping platform core position (implemented by plat_my_core_pos())
- * to the SCMI power domain ID implemented by SCP.
- ******************************************************************************/
-const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
- 0, 1, 2, 3, 4, 5, 6, 7
-};
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_trusted_boot.c b/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_trusted_boot.c
deleted file mode 100644
index 84622d0..0000000
--- a/plat/arm/board/neoverse_rd/platform/sgi575/sgi575_trusted_boot.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2020-2024, Arm Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <plat/arm/common/plat_arm.h>
-
-/*
- * Return the ROTPK hash in the following ASN.1 structure in DER format:
- *
- * AlgorithmIdentifier ::= SEQUENCE {
- * algorithm OBJECT IDENTIFIER,
- * parameters ANY DEFINED BY algorithm OPTIONAL
- * }
- *
- * DigestInfo ::= SEQUENCE {
- * digestAlgorithm AlgorithmIdentifier,
- * digest OCTET STRING
- * }
- */
-int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
- unsigned int *flags)
-{
- return arm_get_rotpk_info(cookie, key_ptr, key_len, flags);
-}
diff --git a/plat/arm/board/tc/platform.mk b/plat/arm/board/tc/platform.mk
index a056bc2..cf42243 100644
--- a/plat/arm/board/tc/platform.mk
+++ b/plat/arm/board/tc/platform.mk
@@ -35,8 +35,8 @@
ENABLE_AMU_AUXILIARY_COUNTERS := 1
ENABLE_MPMM := 1
ENABLE_FEAT_MTE2 := 2
-ENABLE_SPE_FOR_NS := 3
-ENABLE_FEAT_TCR2 := 3
+ENABLE_SPE_FOR_NS := 2
+ENABLE_FEAT_TCR2 := 2
ifneq ($(filter ${TARGET_PLATFORM}, 3),)
ENABLE_FEAT_RNG_TRAP := 0
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index 3dd38cd..9659e73 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -224,14 +224,9 @@
PLAT_BL_COMMON_SOURCES += lib/xlat_tables/xlat_tables_common.c \
lib/xlat_tables/${ARCH}/xlat_tables.c
else
-ifeq (${XLAT_MPU_LIB_V1}, 1)
-include lib/xlat_mpu/xlat_mpu.mk
-PLAT_BL_COMMON_SOURCES += ${XLAT_MPU_LIB_V1_SRCS}
-else
include lib/xlat_tables_v2/xlat_tables.mk
PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
endif
-endif
ARM_IO_SOURCES += plat/arm/common/arm_io_storage.c \
plat/arm/common/fconf/arm_fconf_io.c
diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c
index ba47b30..4423863 100644
--- a/plat/common/aarch64/plat_common.c
+++ b/plat/common/aarch64/plat_common.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -45,18 +45,6 @@
{
}
-/*
- * Helper function for platform_get_pos() when platform compatibility is
- * disabled. This is to enable SPDs using the older platform API to continue
- * to work.
- */
-unsigned int platform_core_pos_helper(unsigned long mpidr)
-{
- int idx = plat_core_pos_by_mpidr(mpidr);
- assert(idx >= 0);
- return idx;
-}
-
#if SDEI_SUPPORT
/*
* Function that handles spurious SDEI interrupts while events are masked.
diff --git a/plat/imx/imx8m/imx8m_measured_boot.c b/plat/imx/imx8m/imx8m_measured_boot.c
index 159be00..7566403 100644
--- a/plat/imx/imx8m/imx8m_measured_boot.c
+++ b/plat/imx/imx8m/imx8m_measured_boot.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
* Copyright (c) 2022, Linaro.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -78,7 +78,7 @@
/* Ensure that the Event Log is visible in Non-secure memory */
flush_dcache_range(ns_log_addr, event_log_cur_size);
- dump_event_log((uint8_t *)event_log, event_log_cur_size);
+ event_log_dump((uint8_t *)event_log, event_log_cur_size);
}
int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr,
diff --git a/plat/qemu/qemu/qemu_measured_boot.c b/plat/qemu/qemu/qemu_measured_boot.c
index 54a4156..4736f9d 100644
--- a/plat/qemu/qemu/qemu_measured_boot.c
+++ b/plat/qemu/qemu/qemu_measured_boot.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2022-2025, Arm Limited. All rights reserved.
* Copyright (c) 2022-2023, Linaro.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -7,6 +7,7 @@
#include <stdint.h>
+#include <common/debug.h>
#include <drivers/measured_boot/event_log/event_log.h>
#include <drivers/measured_boot/metadata.h>
#include <plat/common/common_def.h>
@@ -65,7 +66,7 @@
event_log_cur_size = event_log_get_cur_size((uint8_t *)event_log_base);
- dump_event_log((uint8_t *)event_log_base, event_log_cur_size);
+ event_log_dump((uint8_t *)event_log_base, event_log_cur_size);
#if TRANSFER_LIST
if (!plat_handoff_mboot((void *)event_log_base, event_log_cur_size,
diff --git a/plat/rpi/rpi3/rpi3_bl1_mboot.c b/plat/rpi/rpi3/rpi3_bl1_mboot.c
index 4294365..2057962 100644
--- a/plat/rpi/rpi3/rpi3_bl1_mboot.c
+++ b/plat/rpi/rpi3/rpi3_bl1_mboot.c
@@ -131,7 +131,7 @@
event_log_record(hash_data, EV_POST_CODE, metadata_ptr);
/* Dump Event Log for user view */
- dump_event_log((uint8_t *)event_log, event_log_get_cur_size(event_log));
+ event_log_dump((uint8_t *)event_log, event_log_get_cur_size(event_log));
return rc;
}
diff --git a/plat/rpi/rpi3/rpi3_bl2_mboot.c b/plat/rpi/rpi3/rpi3_bl2_mboot.c
index 55c6923..684e697 100644
--- a/plat/rpi/rpi3/rpi3_bl2_mboot.c
+++ b/plat/rpi/rpi3/rpi3_bl2_mboot.c
@@ -106,7 +106,7 @@
flush_dcache_range(ns_log_addr, event_log_cur_size);
/* Dump Event Log for user view */
- dump_event_log((uint8_t *)event_log_start, event_log_cur_size);
+ event_log_dump((uint8_t *)event_log_start, event_log_cur_size);
#if DISCRETE_TPM
/* relinquish control of TPM locality 0 and close interface */
diff --git a/plat/ti/k3/include/k3_console.h b/plat/ti/common/include/k3_console.h
similarity index 100%
rename from plat/ti/k3/include/k3_console.h
rename to plat/ti/common/include/k3_console.h
diff --git a/plat/ti/k3/include/k3_gicv3.h b/plat/ti/common/include/k3_gicv3.h
similarity index 100%
rename from plat/ti/k3/include/k3_gicv3.h
rename to plat/ti/common/include/k3_gicv3.h
diff --git a/plat/ti/k3/include/plat_macros.S b/plat/ti/common/include/plat_macros.S
similarity index 100%
rename from plat/ti/k3/include/plat_macros.S
rename to plat/ti/common/include/plat_macros.S
diff --git a/plat/ti/common/include/plat_private.h b/plat/ti/common/include/plat_private.h
new file mode 100644
index 0000000..697cc5c
--- /dev/null
+++ b/plat/ti/common/include/plat_private.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef PLATFORM_PRIVATE_H
+#define PLATFORM_PRIVATE_H
+
+#include <drivers/generic_delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+#include <board_def.h>
+
+#define ADDR_DOWN(_adr) (_adr & XLAT_ADDR_MASK(2U))
+#define SIZE_UP(_adr, _sz) (round_up((_adr + _sz), XLAT_BLOCK_SIZE(2U)) - ADDR_DOWN(_adr))
+
+#define K3_MAP_REGION_FLAT(_adr, _sz, _attr) \
+ MAP_REGION_FLAT(ADDR_DOWN(_adr), SIZE_UP(_adr, _sz), _attr)
+
+extern const mmap_region_t plat_k3_mmap[];
+
+/* Any kind of SOC specific init can be done here */
+int ti_soc_init(void);
+
+#endif /* PLATFORM_PRIVATE_H */
diff --git a/plat/ti/common/include/ti_platform_defs.h b/plat/ti/common/include/ti_platform_defs.h
new file mode 100644
index 0000000..44c2f94
--- /dev/null
+++ b/plat/ti/common/include/ti_platform_defs.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef TI_PLATFORM_DEF_H
+#define TI_PLATFORM_DEF_H
+
+#include <arch.h>
+#include <plat/common/common_def.h>
+
+#include <board_def.h>
+
+/*******************************************************************************
+ * Generic platform constants
+ ******************************************************************************/
+
+/* Size of cacheable stack */
+#if IMAGE_BL31
+#define PLATFORM_STACK_SIZE 0x800
+#else
+#define PLATFORM_STACK_SIZE 0x1000
+#endif
+
+#define PLATFORM_SYSTEM_COUNT 1
+#define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \
+ K3_CLUSTER1_CORE_COUNT + \
+ K3_CLUSTER2_CORE_COUNT + \
+ K3_CLUSTER3_CORE_COUNT)
+
+#define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_CORE_COUNT != 0) + \
+ (K3_CLUSTER1_CORE_COUNT != 0) + \
+ (K3_CLUSTER2_CORE_COUNT != 0) + \
+ (K3_CLUSTER3_CORE_COUNT != 0))
+
+#define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \
+ PLATFORM_CLUSTER_COUNT + \
+ PLATFORM_CORE_COUNT)
+#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
+#define PLAT_MAX_OFF_STATE U(2)
+#define PLAT_MAX_RET_STATE U(1)
+
+/*******************************************************************************
+ * Memory layout constants
+ ******************************************************************************/
+
+/*
+ * This RAM will be used for the bootloader including code, bss, and stacks.
+ * It may need to be increased if BL31 grows in size.
+ *
+ * The link addresses are determined by BL31_BASE + offset.
+ * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
+ * BL31_BASE is really arbitrary.
+ *
+ * When ENABLE_PIE is unset, BL31_BASE should be chosen so that
+ * it matches to the physical address where BL31 is loaded, that is,
+ * BL31_BASE should be the base address of the RAM region.
+ *
+ * Lets make things explicit by mapping BL31_BASE to 0x0 since ENABLE_PIE is
+ * defined as default for our platform.
+ */
+#define BL31_BASE UL(0x00000000) /* PIE remapped on fly */
+#define BL31_SIZE UL(0x00020000) /* 128k */
+#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
+
+/*
+ * Defines the maximum number of translation tables that are allocated by the
+ * translation table library code. To minimize the amount of runtime memory
+ * used, choose the smallest value needed to map the required virtual addresses
+ * for each BL stage.
+ */
+#define MAX_XLAT_TABLES 4
+
+/*
+ * Defines the maximum number of regions that are allocated by the translation
+ * table library code. A region consists of physical base address, virtual base
+ * address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
+ * defined in the `mmap_region_t` structure. The platform defines the regions
+ * that should be mapped. Then, the translation table library will create the
+ * corresponding tables and descriptors at runtime. To minimize the amount of
+ * runtime memory used, choose the smallest value needed to register the
+ * required regions for each BL stage.
+ */
+#if USE_COHERENT_MEM
+#define MAX_MMAP_REGIONS 11
+#else
+#define MAX_MMAP_REGIONS 10
+#endif
+
+/*
+ * Defines the total size of the address space in bytes. For example, for a 32
+ * bit address space, this value should be `(1ull << 32)`.
+ */
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches.
+ */
+#define CACHE_WRITEBACK_SHIFT 6
+#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
+
+/* Platform default console definitions */
+#ifndef K3_USART_BASE
+#define K3_USART_BASE (0x02800000 + 0x10000 * K3_USART)
+#endif
+
+/* USART has a default size for address space */
+#define K3_USART_SIZE 0x1000
+
+#ifndef K3_USART_CLK_SPEED
+#define K3_USART_CLK_SPEED 48000000
+#endif
+
+/* Crash console defaults */
+#define CRASH_CONSOLE_BASE K3_USART_BASE
+#define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED
+#define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD
+
+/* Timer frequency */
+#ifndef SYS_COUNTER_FREQ_IN_TICKS
+#define SYS_COUNTER_FREQ_IN_TICKS 200000000
+#endif
+
+/* Interrupt numbers */
+#define ARM_IRQ_SEC_PHY_TIMER 29
+
+#define ARM_IRQ_SEC_SGI_0 8
+#define ARM_IRQ_SEC_SGI_1 9
+#define ARM_IRQ_SEC_SGI_2 10
+#define ARM_IRQ_SEC_SGI_3 11
+#define ARM_IRQ_SEC_SGI_4 12
+#define ARM_IRQ_SEC_SGI_5 13
+#define ARM_IRQ_SEC_SGI_6 14
+#define ARM_IRQ_SEC_SGI_7 15
+
+/*
+ * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
+ * terminology. On a GICv2 system or mode, the lists will be merged and treated
+ * as Group 0 interrupts.
+ */
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE)
+
+#define PLAT_ARM_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_EDGE)
+
+
+#define K3_GTC_BASE 0x00A90000
+/* We just need 20 byte offset, but simpler to just remap the 64K page in */
+#define K3_GTC_SIZE 0x10000
+#define K3_GTC_CNTCR_OFFSET 0x00
+#define K3_GTC_CNTCR_EN_MASK 0x01
+#define K3_GTC_CNTCR_HDBG_MASK 0x02
+#define K3_GTC_CNTFID0_OFFSET 0x20
+
+#define K3_GIC_BASE 0x01800000
+#define K3_GIC_SIZE 0x200000
+
+#define TI_SCI_HOST_ID 10
+#define TI_SCI_MAX_MESSAGE_SIZE 52
+
+#endif /* TI_PLATFORM_DEF_H */
diff --git a/plat/ti/k3/common/k3_console.c b/plat/ti/common/k3_console.c
similarity index 100%
rename from plat/ti/k3/common/k3_console.c
rename to plat/ti/common/k3_console.c
diff --git a/plat/ti/k3/common/k3_gicv3.c b/plat/ti/common/k3_gicv3.c
similarity index 100%
rename from plat/ti/k3/common/k3_gicv3.c
rename to plat/ti/common/k3_gicv3.c
diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/common/k3_helpers.S
similarity index 100%
rename from plat/ti/k3/common/k3_helpers.S
rename to plat/ti/common/k3_helpers.S
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/common/plat_common.mk
similarity index 77%
rename from plat/ti/k3/common/plat_common.mk
rename to plat/ti/common/plat_common.mk
index 8db732c..1f1b618 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/common/plat_common.mk
@@ -51,12 +51,11 @@
PLAT_INCLUDES += \
-I${PLAT_PATH}/include \
- -I${PLAT_PATH}/common/drivers/sec_proxy \
- -I${PLAT_PATH}/common/drivers/ti_sci \
+ -Idrivers/ti/ti_sci \
K3_CONSOLE_SOURCES += \
drivers/ti/uart/aarch64/16550_console.S \
- ${PLAT_PATH}/common/k3_console.c \
+ plat/ti/common/k3_console.c \
# Include GICv3 driver files
include drivers/arm/gic/v3/gicv3.mk
@@ -64,17 +63,14 @@
K3_GIC_SOURCES += \
${GICV3_SOURCES} \
plat/common/plat_gicv3.c \
- ${PLAT_PATH}/common/k3_gicv3.c \
+ plat/ti/common/k3_gicv3.c \
K3_PSCI_SOURCES += \
plat/common/plat_psci_common.c \
- ${PLAT_PATH}/common/k3_psci.c \
-K3_SEC_PROXY_SOURCES += \
- ${PLAT_PATH}/common/drivers/sec_proxy/sec_proxy.c \
K3_TI_SCI_SOURCES += \
- ${PLAT_PATH}/common/drivers/ti_sci/ti_sci.c \
+ drivers/ti/ti_sci/ti_sci.c \
PLAT_BL_COMMON_SOURCES += \
lib/cpus/aarch64/cortex_a53.S \
@@ -83,10 +79,7 @@
${K3_CONSOLE_SOURCES} \
BL31_SOURCES += \
- ${PLAT_PATH}/common/k3_bl31_setup.c \
- ${PLAT_PATH}/common/k3_helpers.S \
- ${PLAT_PATH}/common/k3_topology.c \
+ plat/ti/common/ti_bl31_setup.c \
+ plat/ti/common/k3_helpers.S \
${K3_GIC_SOURCES} \
- ${K3_PSCI_SOURCES} \
- ${K3_SEC_PROXY_SOURCES} \
${K3_TI_SCI_SOURCES} \
diff --git a/plat/ti/common/ti_bl31_setup.c b/plat/ti/common/ti_bl31_setup.c
new file mode 100644
index 0000000..8038452
--- /dev/null
+++ b/plat/ti/common/ti_bl31_setup.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <string.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+#include <ti_sci.h>
+
+#include <k3_console.h>
+#include <k3_gicv3.h>
+#include <plat_private.h>
+#include <platform_def.h>
+
+/*
+ * Placeholder variables for maintaining information about the next image(s)
+ */
+static entry_point_info_t bl32_image_ep_info;
+static entry_point_info_t bl33_image_ep_info;
+
+/*******************************************************************************
+ * Gets SPSR for BL33 entry
+ ******************************************************************************/
+static uint32_t k3_get_spsr_for_bl33_entry(void)
+{
+ unsigned long el_status;
+ unsigned int mode;
+ uint32_t spsr;
+
+ /* Figure out what mode we enter the non-secure world in */
+ el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
+ el_status &= ID_AA64PFR0_ELX_MASK;
+
+ mode = (el_status) ? MODE_EL2 : MODE_EL1;
+
+ spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
+ return spsr;
+}
+
+/*******************************************************************************
+ * Perform any BL3-1 early platform setup, such as console init and deciding on
+ * memory layout.
+ ******************************************************************************/
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+ /* Initialize the console to provide early debug support */
+ k3_console_setup();
+
+#ifdef BL32_BASE
+ /* Populate entry point information for BL32 */
+ SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
+ bl32_image_ep_info.pc = BL32_BASE;
+ bl32_image_ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
+ DISABLE_ALL_EXCEPTIONS);
+ SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
+#endif
+
+ /* Populate entry point information for BL33 */
+ SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
+ bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
+ bl33_image_ep_info.spsr = k3_get_spsr_for_bl33_entry();
+ SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
+
+#ifdef K3_HW_CONFIG_BASE
+ /*
+ * According to the file ``Documentation/arch/arm64/booting.rst`` of the
+ * Linux kernel tree, Linux expects the physical address of the device
+ * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
+ * must be 0.
+ */
+ bl33_image_ep_info.args.arg0 = (u_register_t)K3_HW_CONFIG_BASE;
+ bl33_image_ep_info.args.arg1 = 0U;
+ bl33_image_ep_info.args.arg2 = 0U;
+ bl33_image_ep_info.args.arg3 = 0U;
+#endif
+}
+
+void bl31_plat_arch_setup(void)
+{
+ const mmap_region_t bl_regions[] = {
+ MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE),
+ MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
+ MT_CODE | MT_RO | MT_SECURE),
+ MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE,
+ MT_RO_DATA | MT_RO | MT_SECURE),
+#if USE_COHERENT_MEM
+ MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
+ MT_DEVICE | MT_RW | MT_SECURE),
+#endif
+ { /* sentinel */ }
+ };
+
+ setup_page_tables(bl_regions, plat_k3_mmap);
+ enable_mmu_el3(0);
+}
+
+void bl31_platform_setup(void)
+{
+ k3_gic_driver_init(K3_GIC_BASE);
+ k3_gic_init();
+ ti_soc_init();
+}
+
+void platform_mem_init(void)
+{
+ /* Do nothing for now... */
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ uint32_t gtc_freq;
+ uint32_t gtc_ctrl;
+
+ /* Lets try and provide basic diagnostics - cost is low */
+ gtc_ctrl = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTCR_OFFSET);
+ /* Did the bootloader fail to enable timer and OS guys are confused? */
+ if ((gtc_ctrl & K3_GTC_CNTCR_EN_MASK) == 0U) {
+ ERROR("GTC is disabled! Timekeeping broken. Fix Bootloader\n");
+ }
+ /*
+ * If debug will not pause time, we will have issues like
+ * drivers timing out while debugging, in cases of OS like Linux,
+ * RCU stall errors, which can be hard to differentiate vs real issues.
+ */
+ if ((gtc_ctrl & K3_GTC_CNTCR_HDBG_MASK) == 0U) {
+ WARN("GTC: Debug access doesn't stop time. Fix Bootloader\n");
+ }
+
+ gtc_freq = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTFID0_OFFSET);
+ /* Many older bootloaders may have missed programming FID0 register */
+ if (gtc_freq != 0U) {
+ return gtc_freq;
+ }
+
+ /*
+ * We could have just warned about this, but this can have serious
+ * hard to debug side effects if we are NOT sure what the actual
+ * frequency is. Lets make sure people don't miss this.
+ */
+ ERROR("GTC_CNTFID0 is 0! Assuming %d Hz. Fix Bootloader\n",
+ SYS_COUNTER_FREQ_IN_TICKS);
+
+ return SYS_COUNTER_FREQ_IN_TICKS;
+}
+
+/*******************************************************************************
+ * Return a pointer to the 'entry_point_info' structure of the next image
+ * for the security state specified. BL3-3 corresponds to the non-secure
+ * image type while BL3-2 corresponds to the secure image type. A NULL
+ * pointer is returned if the image does not exist.
+ ******************************************************************************/
+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+ entry_point_info_t *next_image_info;
+
+ assert(sec_state_is_valid(type));
+ next_image_info = (type == NON_SECURE) ? &bl33_image_ep_info :
+ &bl32_image_ep_info;
+ /*
+ * None of the images on the ARM development platforms can have 0x0
+ * as the entrypoint
+ */
+ if (next_image_info->pc)
+ return next_image_info;
+
+ NOTICE("Requested nonexistent image\n");
+ return NULL;
+}
diff --git a/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h b/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h
deleted file mode 100644
index 4005102..0000000
--- a/plat/ti/k3/common/drivers/sec_proxy/sec_proxy.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Texas Instruments K3 Secure Proxy Driver
- * Based on Linux and U-Boot implementation
- *
- * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef SEC_PROXY_H
-#define SEC_PROXY_H
-
-#include <stdint.h>
-
-/**
- * enum k3_sec_proxy_chan_id - Secure Proxy thread IDs
- *
- * These the available IDs used in k3_sec_proxy_{send,recv}()
- * There are two schemes we use:
- * * if K3_SEC_PROXY_LITE = 1, we just have two threads to talk
- * * if K3_SEC_PROXY_LITE = 0, we have the full fledged
- * communication scheme available.
- */
-enum k3_sec_proxy_chan_id {
-#if !K3_SEC_PROXY_LITE
- SP_NOTIFY = 0,
- SP_RESPONSE,
- SP_HIGH_PRIORITY,
- SP_LOW_PRIORITY,
- SP_NOTIFY_RESP,
-#else
- SP_RESPONSE = 8,
- /*
- * Note: TISCI documentation indicates "low priority", but in reality
- * with a single thread, there is no low or high priority.. This usage
- * is more appropriate for TF-A since we can reduce the churn as a
- * result.
- */
- SP_HIGH_PRIORITY,
-#endif /* K3_SEC_PROXY_LITE */
-};
-
-/**
- * struct k3_sec_proxy_msg - Secure proxy message structure
- * @len: Length of data in the Buffer
- * @buf: Buffer pointer
- *
- * This is the structure for data used in k3_sec_proxy_{send,recv}()
- */
-struct k3_sec_proxy_msg {
- size_t len;
- uint8_t *buf;
-};
-
-/**
- * k3_sec_proxy_clear_rx_thread() - Clear a receive Secure Proxy thread
- * @id: Channel Identifier
- * @msg: Pointer to k3_sec_proxy_msg
- *
- * Return: 0 if all goes well, else appropriate error message
- */
-int k3_sec_proxy_clear_rx_thread(enum k3_sec_proxy_chan_id id);
-
-/**
- * k3_sec_proxy_send() - Send data over a Secure Proxy thread
- * @id: Channel Identifier
- * @msg: Pointer to k3_sec_proxy_msg
- *
- * Return: 0 if all goes well, else appropriate error message
- */
-int k3_sec_proxy_send(enum k3_sec_proxy_chan_id id, const struct k3_sec_proxy_msg *msg);
-
-/**
- * k3_sec_proxy_recv() - Receive data from a Secure Proxy thread
- * @id: Channel Identifier
- * @msg: Pointer to k3_sec_proxy_msg
- *
- * Return: 0 if all goes well, else appropriate error message
- */
-int k3_sec_proxy_recv(enum k3_sec_proxy_chan_id id, struct k3_sec_proxy_msg *msg);
-
-#endif /* SEC_PROXY_H */
diff --git a/plat/ti/k3/common/k3_bl31_setup.c b/plat/ti/k3/common/k3_bl31_setup.c
index 63fe020..1b93dc8 100644
--- a/plat/ti/k3/common/k3_bl31_setup.c
+++ b/plat/ti/k3/common/k3_bl31_setup.c
@@ -1,30 +1,16 @@
/*
* Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/
+ * K3 SOC specific bl31_setup
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <assert.h>
-#include <string.h>
-
-#include <platform_def.h>
-
-#include <arch.h>
-#include <arch_helpers.h>
-#include <common/bl_common.h>
#include <common/debug.h>
-#include <lib/mmio.h>
-#include <lib/xlat_tables/xlat_tables_v2.h>
-
-#include <k3_console.h>
-#include <k3_gicv3.h>
#include <ti_sci.h>
+#include <ti_sci_transport.h>
-#define ADDR_DOWN(_adr) (_adr & XLAT_ADDR_MASK(2U))
-#define SIZE_UP(_adr, _sz) (round_up((_adr + _sz), XLAT_BLOCK_SIZE(2U)) - ADDR_DOWN(_adr))
-
-#define K3_MAP_REGION_FLAT(_adr, _sz, _attr) \
- MAP_REGION_FLAT(ADDR_DOWN(_adr), SIZE_UP(_adr, _sz), _attr)
+#include <plat_private.h>
/* Table of regions to map using the MMU */
const mmap_region_t plat_k3_mmap[] = {
@@ -37,98 +23,15 @@
{ /* sentinel */ }
};
-/*
- * Placeholder variables for maintaining information about the next image(s)
- */
-static entry_point_info_t bl32_image_ep_info;
-static entry_point_info_t bl33_image_ep_info;
-
-/*******************************************************************************
- * Gets SPSR for BL33 entry
- ******************************************************************************/
-static uint32_t k3_get_spsr_for_bl33_entry(void)
-{
- unsigned long el_status;
- unsigned int mode;
- uint32_t spsr;
-
- /* Figure out what mode we enter the non-secure world in */
- el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
- el_status &= ID_AA64PFR0_ELX_MASK;
-
- mode = (el_status) ? MODE_EL2 : MODE_EL1;
-
- spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
- return spsr;
-}
-
-/*******************************************************************************
- * Perform any BL3-1 early platform setup, such as console init and deciding on
- * memory layout.
- ******************************************************************************/
-void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
- u_register_t arg2, u_register_t arg3)
-{
- /* Initialize the console to provide early debug support */
- k3_console_setup();
-
-#ifdef BL32_BASE
- /* Populate entry point information for BL32 */
- SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
- bl32_image_ep_info.pc = BL32_BASE;
- bl32_image_ep_info.spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
- DISABLE_ALL_EXCEPTIONS);
- SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
-#endif
-
- /* Populate entry point information for BL33 */
- SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
- bl33_image_ep_info.pc = PRELOADED_BL33_BASE;
- bl33_image_ep_info.spsr = k3_get_spsr_for_bl33_entry();
- SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
-
-#ifdef K3_HW_CONFIG_BASE
- /*
- * According to the file ``Documentation/arm64/booting.txt`` of the
- * Linux kernel tree, Linux expects the physical address of the device
- * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
- * must be 0.
- */
- bl33_image_ep_info.args.arg0 = (u_register_t)K3_HW_CONFIG_BASE;
- bl33_image_ep_info.args.arg1 = 0U;
- bl33_image_ep_info.args.arg2 = 0U;
- bl33_image_ep_info.args.arg3 = 0U;
-#endif
-}
-
-void bl31_plat_arch_setup(void)
-{
- const mmap_region_t bl_regions[] = {
- MAP_REGION_FLAT(BL31_START, BL31_SIZE, MT_MEMORY | MT_RW | MT_SECURE),
- MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_RO | MT_SECURE),
- MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, MT_RO_DATA | MT_RO | MT_SECURE),
-#if USE_COHERENT_MEM
- MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, MT_DEVICE | MT_RW | MT_SECURE),
-#endif
- { /* sentinel */ }
- };
-
- setup_page_tables(bl_regions, plat_k3_mmap);
- enable_mmu_el3(0);
-}
-
-void bl31_platform_setup(void)
+int ti_soc_init(void)
{
struct ti_sci_msg_version version;
int ret;
- k3_gic_driver_init(K3_GIC_BASE);
- k3_gic_init();
-
ret = ti_sci_get_revision(&version);
if (ret) {
ERROR("Unable to communicate with the control firmware (%d)\n", ret);
- return;
+ return ret;
}
INFO("SYSFW ABI: %d.%d (firmware rev 0x%04x '%s')\n",
@@ -157,70 +60,5 @@
} else {
NOTICE("Upgrade Firmwares for Power off functionality\n");
}
-}
-
-void platform_mem_init(void)
-{
- /* Do nothing for now... */
-}
-
-unsigned int plat_get_syscnt_freq2(void)
-{
- uint32_t gtc_freq;
- uint32_t gtc_ctrl;
-
- /* Lets try and provide basic diagnostics - cost is low */
- gtc_ctrl = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTCR_OFFSET);
- /* Did the bootloader fail to enable timer and OS guys are confused? */
- if ((gtc_ctrl & K3_GTC_CNTCR_EN_MASK) == 0U) {
- ERROR("GTC is disabled! Timekeeping broken. Fix Bootloader\n");
- }
- /*
- * If debug will not pause time, we will have issues like
- * drivers timing out while debugging, in cases of OS like Linux,
- * RCU stall errors, which can be hard to differentiate vs real issues.
- */
- if ((gtc_ctrl & K3_GTC_CNTCR_HDBG_MASK) == 0U) {
- WARN("GTC: Debug access doesn't stop time. Fix Bootloader\n");
- }
-
- gtc_freq = mmio_read_32(K3_GTC_BASE + K3_GTC_CNTFID0_OFFSET);
- /* Many older bootloaders may have missed programming FID0 register */
- if (gtc_freq != 0U) {
- return gtc_freq;
- }
-
- /*
- * We could have just warned about this, but this can have serious
- * hard to debug side effects if we are NOT sure what the actual
- * frequency is. Lets make sure people don't miss this.
- */
- ERROR("GTC_CNTFID0 is 0! Assuming %d Hz. Fix Bootloader\n",
- SYS_COUNTER_FREQ_IN_TICKS);
-
- return SYS_COUNTER_FREQ_IN_TICKS;
-}
-
-/*******************************************************************************
- * Return a pointer to the 'entry_point_info' structure of the next image
- * for the security state specified. BL3-3 corresponds to the non-secure
- * image type while BL3-2 corresponds to the secure image type. A NULL
- * pointer is returned if the image does not exist.
- ******************************************************************************/
-entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
-{
- entry_point_info_t *next_image_info;
-
- assert(sec_state_is_valid(type));
- next_image_info = (type == NON_SECURE) ? &bl33_image_ep_info :
- &bl32_image_ep_info;
- /*
- * None of the images on the ARM development platforms can have 0x0
- * as the entrypoint
- */
- if (next_image_info->pc)
- return next_image_info;
-
- NOTICE("Requested nonexistent image\n");
- return NULL;
+ return 0;
}
diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h
index a2cc62d..db5e31d 100644
--- a/plat/ti/k3/include/platform_def.h
+++ b/plat/ti/k3/include/platform_def.h
@@ -7,174 +7,7 @@
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
-#include <arch.h>
-#include <plat/common/common_def.h>
-
-#include <board_def.h>
-
-/*******************************************************************************
- * Generic platform constants
- ******************************************************************************/
-
-/* Size of cacheable stack */
-#if IMAGE_BL31
-#define PLATFORM_STACK_SIZE 0x800
-#else
-#define PLATFORM_STACK_SIZE 0x1000
-#endif
-
-#define PLATFORM_SYSTEM_COUNT 1
-#define PLATFORM_CORE_COUNT (K3_CLUSTER0_CORE_COUNT + \
- K3_CLUSTER1_CORE_COUNT + \
- K3_CLUSTER2_CORE_COUNT + \
- K3_CLUSTER3_CORE_COUNT)
-
-#define PLATFORM_CLUSTER_COUNT ((K3_CLUSTER0_CORE_COUNT != 0) + \
- (K3_CLUSTER1_CORE_COUNT != 0) + \
- (K3_CLUSTER2_CORE_COUNT != 0) + \
- (K3_CLUSTER3_CORE_COUNT != 0))
-
-#define PLAT_NUM_PWR_DOMAINS (PLATFORM_SYSTEM_COUNT + \
- PLATFORM_CLUSTER_COUNT + \
- PLATFORM_CORE_COUNT)
-#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
-#define PLAT_MAX_OFF_STATE U(2)
-#define PLAT_MAX_RET_STATE U(1)
-
-/*******************************************************************************
- * Memory layout constants
- ******************************************************************************/
-
-/*
- * This RAM will be used for the bootloader including code, bss, and stacks.
- * It may need to be increased if BL31 grows in size.
- *
- * The link addresses are determined by BL31_BASE + offset.
- * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
- * BL31_BASE is really arbitrary.
- *
- * When ENABLE_PIE is unset, BL31_BASE should be chosen so that
- * it matches to the physical address where BL31 is loaded, that is,
- * BL31_BASE should be the base address of the RAM region.
- *
- * Lets make things explicit by mapping BL31_BASE to 0x0 since ENABLE_PIE is
- * defined as default for our platform.
- */
-#define BL31_BASE UL(0x00000000) /* PIE remapped on fly */
-#define BL31_SIZE UL(0x00020000) /* 128k */
-#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
-
-/*
- * Defines the maximum number of translation tables that are allocated by the
- * translation table library code. To minimize the amount of runtime memory
- * used, choose the smallest value needed to map the required virtual addresses
- * for each BL stage.
- */
-#define MAX_XLAT_TABLES 4
-
-/*
- * Defines the maximum number of regions that are allocated by the translation
- * table library code. A region consists of physical base address, virtual base
- * address, size and attributes (Device/Memory, RO/RW, Secure/Non-Secure), as
- * defined in the `mmap_region_t` structure. The platform defines the regions
- * that should be mapped. Then, the translation table library will create the
- * corresponding tables and descriptors at runtime. To minimize the amount of
- * runtime memory used, choose the smallest value needed to register the
- * required regions for each BL stage.
- */
-#if USE_COHERENT_MEM
-#define MAX_MMAP_REGIONS 11
-#else
-#define MAX_MMAP_REGIONS 10
-#endif
-
-/*
- * Defines the total size of the address space in bytes. For example, for a 32
- * bit address space, this value should be `(1ull << 32)`.
- */
-#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
-#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
-
-/*
- * Some data must be aligned on the biggest cache line size in the platform.
- * This is known only to the platform as it might have a combination of
- * integrated and external caches.
- */
-#define CACHE_WRITEBACK_SHIFT 6
-#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
-
-/* Platform default console definitions */
-#ifndef K3_USART_BASE
-#define K3_USART_BASE (0x02800000 + 0x10000 * K3_USART)
-#endif
-
-/* USART has a default size for address space */
-#define K3_USART_SIZE 0x1000
-
-#ifndef K3_USART_CLK_SPEED
-#define K3_USART_CLK_SPEED 48000000
-#endif
-
-/* Crash console defaults */
-#define CRASH_CONSOLE_BASE K3_USART_BASE
-#define CRASH_CONSOLE_CLK K3_USART_CLK_SPEED
-#define CRASH_CONSOLE_BAUD_RATE K3_USART_BAUD
-
-/* Timer frequency */
-#ifndef SYS_COUNTER_FREQ_IN_TICKS
-#define SYS_COUNTER_FREQ_IN_TICKS 200000000
-#endif
-
-/* Interrupt numbers */
-#define ARM_IRQ_SEC_PHY_TIMER 29
-
-#define ARM_IRQ_SEC_SGI_0 8
-#define ARM_IRQ_SEC_SGI_1 9
-#define ARM_IRQ_SEC_SGI_2 10
-#define ARM_IRQ_SEC_SGI_3 11
-#define ARM_IRQ_SEC_SGI_4 12
-#define ARM_IRQ_SEC_SGI_5 13
-#define ARM_IRQ_SEC_SGI_6 14
-#define ARM_IRQ_SEC_SGI_7 15
-
-/*
- * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3
- * terminology. On a GICv2 system or mode, the lists will be merged and treated
- * as Group 0 interrupts.
- */
-#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
- INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
- GIC_INTR_CFG_LEVEL), \
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
- GIC_INTR_CFG_EDGE), \
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
- GIC_INTR_CFG_EDGE), \
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
- GIC_INTR_CFG_EDGE), \
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
- GIC_INTR_CFG_EDGE), \
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
- GIC_INTR_CFG_EDGE), \
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
- GIC_INTR_CFG_EDGE)
-
-#define PLAT_ARM_G0_IRQ_PROPS(grp) \
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
- GIC_INTR_CFG_EDGE), \
- INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
- GIC_INTR_CFG_EDGE)
-
-
-#define K3_GTC_BASE 0x00A90000
-/* We just need 20 byte offset, but simpler to just remap the 64K page in */
-#define K3_GTC_SIZE 0x10000
-#define K3_GTC_CNTCR_OFFSET 0x00
-#define K3_GTC_CNTCR_EN_MASK 0x01
-#define K3_GTC_CNTCR_HDBG_MASK 0x02
-#define K3_GTC_CNTFID0_OFFSET 0x20
-
-#define K3_GIC_BASE 0x01800000
-#define K3_GIC_SIZE 0x200000
+#include <ti_platform_defs.h>
#if !K3_SEC_PROXY_LITE
#define SEC_PROXY_DATA_BASE 0x32C00000
@@ -195,7 +28,4 @@
#define SEC_PROXY_TIMEOUT_US 1000000
#define SEC_PROXY_MAX_MESSAGE_SIZE 56
-#define TI_SCI_HOST_ID 10
-#define TI_SCI_MAX_MESSAGE_SIZE 52
-
#endif /* PLATFORM_DEF_H */
diff --git a/plat/ti/k3/platform.mk b/plat/ti/k3/platform.mk
index bce9ef1..347a088 100644
--- a/plat/ti/k3/platform.mk
+++ b/plat/ti/k3/platform.mk
@@ -7,7 +7,7 @@
PLAT_PATH := plat/ti/k3
TARGET_BOARD ?= generic
-include ${PLAT_PATH}/common/plat_common.mk
+include plat/ti/common/plat_common.mk
include ${PLAT_PATH}/board/${TARGET_BOARD}/board.mk
BL32_BASE ?= 0x9e800000
@@ -19,7 +19,20 @@
K3_HW_CONFIG_BASE ?= 0x82000000
$(eval $(call add_define,K3_HW_CONFIG_BASE))
-PLAT_INCLUDES += -Iplat/ti/k3/board/${TARGET_BOARD}/include
+PLAT_INCLUDES += -Iplat/ti/k3/board/${TARGET_BOARD}/include \
+ -Iplat/ti/common/include \
# modify BUILD_PLAT to point to board specific build directory
BUILD_PLAT := $(abspath ${BUILD_BASE})/${PLAT}/${TARGET_BOARD}/${BUILD_TYPE}
+
+K3_PSCI_SOURCES += \
+ ${PLAT_PATH}/common/k3_psci.c \
+
+K3_TI_SCI_TRANSPORT := \
+ drivers/ti/ipc/sec_proxy.c \
+
+BL31_SOURCES += \
+ ${PLAT_PATH}/common/k3_bl31_setup.c \
+ ${PLAT_PATH}/common/k3_topology.c \
+ ${K3_TI_SCI_TRANSPORT} \
+ ${K3_PSCI_SOURCES} \
diff --git a/plat/ti/k3low/board/am62lx/board.mk b/plat/ti/k3low/board/am62lx/board.mk
new file mode 100644
index 0000000..26e58c6
--- /dev/null
+++ b/plat/ti/k3low/board/am62lx/board.mk
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2024-2025, Texas Instruments Inc. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# We dont have system level coherency capability
+USE_COHERENT_MEM := 0
+
+BL32_BASE ?= 0x80200000
+$(eval $(call add_define,BL32_BASE))
+
+PRELOADED_BL33_BASE ?= 0x82000000
+$(eval $(call add_define,PRELOADED_BL33_BASE))
+
+K3_HW_CONFIG_BASE ?= 0x88000000
+$(eval $(call add_define,K3_HW_CONFIG_BASE))
diff --git a/plat/ti/k3low/board/am62lx/include/board_def.h b/plat/ti/k3low/board/am62lx/include/board_def.h
new file mode 100644
index 0000000..ea46423
--- /dev/null
+++ b/plat/ti/k3low/board/am62lx/include/board_def.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti.com
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BOARD_DEF_H
+#define BOARD_DEF_H
+
+#include <lib/utils_def.h>
+
+/* The ports must be in order and contiguous */
+#define K3_CLUSTER0_CORE_COUNT U(2)
+#define K3_CLUSTER1_CORE_COUNT U(0)
+#define K3_CLUSTER2_CORE_COUNT U(0)
+#define K3_CLUSTER3_CORE_COUNT U(0)
+
+#define PLAT_PROC_START_ID U(32)
+#define PLAT_PROC_DEVICE_START_ID U(135)
+#define PLAT_CLUSTER_DEVICE_START_ID U(134)
+#define PLAT_BOARD_DEVICE_ID U(157)
+
+/* Pre-decided SRAM Addresses for sending and receiving messages */
+#define MAILBOX_TX_START_REGION UL(0x70814000)
+#define MAILBOX_RX_START_REGION UL(0x70815000)
+/*
+ * Pre-calculated MAX size of a message
+ * sec_hdr + (type/host/seq + flags) + payload
+ * 4 + 16 + 36
+ */
+#define MAILBOX_MAX_MESSAGE_SIZE U(56)
+
+#endif /* BOARD_DEF_H */
diff --git a/plat/ti/k3low/common/am62l_bl31_setup.c b/plat/ti/k3low/common/am62l_bl31_setup.c
new file mode 100644
index 0000000..22255f4
--- /dev/null
+++ b/plat/ti/k3low/common/am62l_bl31_setup.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2025 Texas Instruments Incorporated - http://www.ti.com/
+ * K3 SOC specific bl31_setup
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/debug.h>
+#include <ti_sci.h>
+#include <ti_sci_transport.h>
+
+#include <plat_private.h>
+
+/* Table of regions to map using the MMU */
+const mmap_region_t plat_k3_mmap[] = {
+ { /* sentinel */ }
+};
+
+int ti_soc_init(void)
+{
+ /* nothing to do right now */
+ return 0;
+}
diff --git a/plat/ti/k3low/common/am62l_psci.c b/plat/ti/k3low/common/am62l_psci.c
new file mode 100644
index 0000000..b14f0f5
--- /dev/null
+++ b/plat/ti/k3low/common/am62l_psci.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2025, Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdbool.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/el3_runtime/cpu_data.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+#include <plat/common/platform.h>
+#include <ti_sci.h>
+#include <ti_sci_protocol.h>
+
+#include <k3_gicv3.h>
+#include <platform_def.h>
+
+uintptr_t am62l_sec_entrypoint;
+uintptr_t am62l_sec_entrypoint_glob;
+void __aligned(16) jump_to_atf_func(void *unused);
+
+static int am62l_pwr_domain_on(u_register_t mpidr)
+{
+ int32_t core, ret;
+ uint8_t proc_id;
+
+ core = plat_core_pos_by_mpidr(mpidr);
+ if (core < 0) {
+ ERROR("Could not get target core id: %d\n", core);
+ return PSCI_E_INTERN_FAIL;
+ }
+
+ proc_id = (uint8_t)(PLAT_PROC_START_ID + (uint32_t)core);
+
+ ret = ti_sci_proc_request(proc_id);
+ if (ret != 0) {
+ ERROR("Request for processor ID 0x%x failed: %d\n",
+ proc_id, ret);
+ return PSCI_E_INTERN_FAIL;
+ }
+
+ ret = ti_sci_proc_set_boot_cfg(proc_id, am62l_sec_entrypoint, 0, 0);
+ if (ret != 0) {
+ ERROR("Request to set core boot address failed: %d\n", ret);
+ return PSCI_E_INTERN_FAIL;
+ }
+
+ /* sanity check these are off before starting a core */
+ ret = ti_sci_proc_set_boot_ctrl(proc_id,
+ 0, PROC_BOOT_CTRL_FLAG_ARMV8_L2FLUSHREQ |
+ PROC_BOOT_CTRL_FLAG_ARMV8_AINACTS |
+ PROC_BOOT_CTRL_FLAG_ARMV8_ACINACTM);
+ if (ret != 0) {
+ ERROR("Request to clear boot config failed: %d\n", ret);
+ return PSCI_E_INTERN_FAIL;
+ }
+
+ /*
+ * TODO: Add the actual PM operation call
+ * to turn on the core here
+ */
+ return PSCI_E_SUCCESS;
+}
+
+static void am62l_pwr_domain_off(const psci_power_state_t *target_state)
+{
+ /* At very least the local core should be powering down */
+ assert(((target_state)->pwr_domain_state[MPIDR_AFFLVL0]) == PLAT_MAX_OFF_STATE);
+
+ /* Prevent interrupts from spuriously waking up this cpu */
+ k3_gic_cpuif_disable();
+
+}
+
+static void am62l_pwr_down_domain(const psci_power_state_t *target_state)
+{
+ /* TODO: Add the actual pm operation call to turn off the core */
+}
+
+void am62l_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+ k3_gic_pcpu_init();
+ k3_gic_cpuif_enable();
+}
+
+static void am62l_system_reset(void)
+{
+ mmio_write_32(WKUP_CTRL_MMR0_DEVICE_MANAGEMENT_BASE + WKUP_CTRL_MMR0_DEVICE_RESET_OFFSET,
+ 0x6);
+
+ /* Wait for reset to complete for 500ms before printing error */
+ mdelay(500);
+
+ /* Ideally we should not reach here */
+ ERROR("%s: Failed to reset device\n", __func__);
+}
+
+static plat_psci_ops_t am62l_plat_psci_ops = {
+ .pwr_domain_on = am62l_pwr_domain_on,
+ .pwr_domain_off = am62l_pwr_domain_off,
+ .pwr_domain_pwr_down = am62l_pwr_down_domain,
+ .pwr_domain_on_finish = am62l_pwr_domain_on_finish,
+ .system_reset = am62l_system_reset,
+};
+
+void __aligned(16) jump_to_atf_func(void *unused)
+{
+ /*
+ * MISRA Deviation observed:
+ * Rule 11.1 (MISRA C:2012) Prohibits conversion performed between a
+ * pointer to a function and another incompatible type.
+ * This conversion is required for handling secure boot entry points.
+ * The conversion is safe as the address is verified before execution.
+ */
+ void (*bl31_loc_warm_entry)(void) = (void *)am62l_sec_entrypoint_glob;
+
+ bl31_loc_warm_entry();
+}
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+ const plat_psci_ops_t **psci_ops)
+{
+ am62l_sec_entrypoint_glob = sec_entrypoint;
+ /* Note that boot vector reg in sec mmr requires 16B aligned start address */
+ am62l_sec_entrypoint = (uint64_t)(void *)&jump_to_atf_func;
+ VERBOSE("am62l_sec_entrypoint = 0x%lx\n", am62l_sec_entrypoint);
+
+ *psci_ops = &am62l_plat_psci_ops;
+
+ return 0;
+}
diff --git a/plat/ti/k3low/common/am62l_topology.c b/plat/ti/k3low/common/am62l_topology.c
new file mode 100644
index 0000000..15f5118
--- /dev/null
+++ b/plat/ti/k3low/common/am62l_topology.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2025, Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/psci/psci.h>
+
+#include <platform_def.h>
+
+/* The power domain tree descriptor */
+static unsigned char power_domain_tree_desc[] = {
+ PLATFORM_SYSTEM_COUNT,
+ PLATFORM_CLUSTER_COUNT,
+ K3_CLUSTER0_CORE_COUNT,
+};
+
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ return power_domain_tree_desc;
+}
+
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+ unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
+
+ if (MPIDR_AFFLVL3_VAL(mpidr) > 0 ||
+ MPIDR_AFFLVL2_VAL(mpidr) > 0) {
+ return -1;
+ }
+
+ return core;
+}
diff --git a/plat/ti/k3low/include/platform_def.h b/plat/ti/k3low/include/platform_def.h
new file mode 100644
index 0000000..37f984c
--- /dev/null
+++ b/plat/ti/k3low/include/platform_def.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025, Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <ti_platform_defs.h>
+
+#define TI_MAILBOX_TX_BASE UL(0x44240000) /* TFA sending IPC messages to TIFS */
+#define TI_MAILBOX_RX_BASE UL(0x44250000) /* TIFS sending IPC messages to A53 */
+
+#define WKUP_CTRL_MMR0_DEVICE_MANAGEMENT_BASE (0x43050000UL)
+#define WKUP_CTRL_MMR0_DEVICE_RESET_OFFSET (0x4000UL)
+
+#endif /* PLATFORM_DEF_H */
diff --git a/plat/ti/k3low/platform.mk b/plat/ti/k3low/platform.mk
new file mode 100644
index 0000000..5bc47ff
--- /dev/null
+++ b/plat/ti/k3low/platform.mk
@@ -0,0 +1,29 @@
+#
+# Copyright (c) 2025, Texas Instruments Incorporated - https://www.ti.com/
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+PLAT_PATH := plat/ti/k3low
+TARGET_BOARD ?= am62lx
+
+include plat/ti/common/plat_common.mk
+include ${PLAT_PATH}/board/${TARGET_BOARD}/board.mk
+
+PLAT_INCLUDES += \
+ -I${PLAT_PATH}/board/${TARGET_BOARD}/include \
+ -I${PLAT_PATH} \
+ -Iplat/ti/common/include \
+
+K3_PSCI_SOURCES += \
+ ${PLAT_PATH}/common/am62l_psci.c \
+
+K3_TI_SCI_TRANSPORT := \
+ drivers/ti/ipc/mailbox.c \
+
+BL31_SOURCES += \
+ drivers/delay_timer/delay_timer.c \
+ ${K3_PSCI_SOURCES} \
+ ${K3_TI_SCI_TRANSPORT} \
+ ${PLAT_PATH}/common/am62l_bl31_setup.c \
+ ${PLAT_PATH}/common/am62l_topology.c \
diff --git a/plat/xilinx/common/include/ipi.h b/plat/xilinx/common/include/ipi.h
index d792710..71c06c3 100644
--- a/plat/xilinx/common/include/ipi.h
+++ b/plat/xilinx/common/include/ipi.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018, Xilinx, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -60,7 +61,7 @@
void ipi_mb_release(uint32_t local, uint32_t remote);
/* Enquire IPI mailbox status */
-int ipi_mb_enquire_status(uint32_t local, uint32_t remote);
+uint32_t ipi_mb_enquire_status(uint32_t local, uint32_t remote);
/* Trigger notification on the IPI mailbox */
void ipi_mb_notify(uint32_t local, uint32_t remote, uint32_t is_blocking);
diff --git a/plat/xilinx/common/include/pm_api_sys.h b/plat/xilinx/common/include/pm_api_sys.h
index 029bb43..2e4b342 100644
--- a/plat/xilinx/common/include/pm_api_sys.h
+++ b/plat/xilinx/common/include/pm_api_sys.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -36,7 +36,7 @@
uint32_t state, uint32_t flag);
enum pm_ret_status pm_req_wakeup(uint32_t target, uint32_t set_address,
uintptr_t address, uint8_t ack, uint32_t flag);
-enum pm_ret_status pm_set_wakeup_source(uint32_t target, uint32_t device_id,
+enum pm_ret_status pm_set_wakeup_source(uint32_t target, uint32_t wkup_device,
uint8_t enable, uint32_t flag);
enum pm_ret_status pm_get_callbackdata(uint32_t *data, size_t count, uint32_t flag,
uint32_t ack);
diff --git a/plat/xilinx/common/ipi.c b/plat/xilinx/common/ipi.c
index cc4b04d..18ae096 100644
--- a/plat/xilinx/common/ipi.c
+++ b/plat/xilinx/common/ipi.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2017-2020, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -20,6 +20,7 @@
#include <ipi.h>
#include <plat_private.h>
+#include "pm_defs.h"
/*********************************************************************
* Macros definitions
@@ -139,13 +140,12 @@
* @local: local IPI ID.
* @remote: remote IPI ID.
*
- * Return: 0 idle, positive value for pending sending or receiving,
- * negative value for errors.
+ * Return: 0 idle and positive value for pending sending or receiving.
*
*/
-int ipi_mb_enquire_status(uint32_t local, uint32_t remote)
+uint32_t ipi_mb_enquire_status(uint32_t local, uint32_t remote)
{
- int ret = 0U;
+ uint32_t ret = (uint32_t)PM_RET_SUCCESS;
uint32_t status;
uint64_t obr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_OBR_OFFSET);
uint64_t isr_offset = (uint64_t)(IPI_REG_BASE(local) + IPI_ISR_OFFSET);
diff --git a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
index 1882669..a2541a3 100644
--- a/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
+++ b/plat/xilinx/common/ipi_mailbox_service/ipi_mailbox_svc.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -109,7 +109,7 @@
bool disable_interrupt;
disable_interrupt = ((x3 & IPI_SMC_ENQUIRY_DIRQ_MASK) != 0U);
- ret = ipi_mb_enquire_status(ipi_local_id, ipi_remote_id);
+ ret = (int32_t)ipi_mb_enquire_status(ipi_local_id, ipi_remote_id);
if ((((uint32_t)ret & IPI_MB_STATUS_RECV_PENDING) > 0U) && disable_interrupt) {
ipi_mb_disable_irq(ipi_local_id, ipi_remote_id);
}
diff --git a/plat/xilinx/common/pm_service/pm_ipi.c b/plat/xilinx/common/pm_service/pm_ipi.c
index bf1fd55..610acc7 100644
--- a/plat/xilinx/common/pm_service/pm_ipi.c
+++ b/plat/xilinx/common/pm_service/pm_ipi.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -186,7 +186,12 @@
value[i] = mmio_read_32(buffer_base + ((i + 1U) * PAYLOAD_ARG_SIZE));
}
- ret = mmio_read_32(buffer_base);
+ /*
+ * Here mmio_read_32() reads return status stored in IPI payload that
+ * is received from firmware and it's value will be one the values
+ * listed in enum pm_ret_status.
+ */
+ ret = (enum pm_ret_status)mmio_read_32(buffer_base);
#if IPI_CRC_CHECK
crc = mmio_read_32(buffer_base + (PAYLOAD_CRC_POS * PAYLOAD_ARG_SIZE));
if (crc != calculate_crc((uint32_t *)buffer_base, IPI_W0_TO_W6_SIZE)) {
@@ -273,7 +278,8 @@
goto unlock;
}
- ret = ERROR_CODE_MASK & (uint32_t)(pm_ipi_buff_read(proc, value, count));
+ ret = (enum pm_ret_status)(ERROR_CODE_MASK &
+ (uint32_t)(pm_ipi_buff_read(proc, value, count)));
unlock:
pm_ipi_lock_release();
@@ -293,15 +299,13 @@
uint32_t pm_ipi_irq_status(const struct pm_proc *proc)
{
- int32_t ret;
- int32_t result = 0;
+ uint32_t ret;
+ uint32_t result = (uint32_t)PM_RET_SUCCESS;
ret = ipi_mb_enquire_status(proc->ipi->local_ipi_id,
proc->ipi->remote_ipi_id);
- if (((uint32_t)ret & IPI_MB_STATUS_RECV_PENDING) != 0U) {
- result = 1;
- } else {
- result = 0;
+ if ((ret & IPI_MB_STATUS_RECV_PENDING) != 0U) {
+ result = IPI_MB_STATUS_RECV_PENDING;
}
return result;
diff --git a/plat/xilinx/common/pm_service/pm_svc_main.c b/plat/xilinx/common/pm_service/pm_svc_main.c
index f586ac3..bc8e251 100644
--- a/plat/xilinx/common/pm_service/pm_svc_main.c
+++ b/plat/xilinx/common/pm_service/pm_svc_main.c
@@ -72,7 +72,7 @@
static void notify_os(void)
{
- plat_ic_raise_ns_sgi(sgi, read_mpidr_el1());
+ plat_ic_raise_ns_sgi((int)sgi, read_mpidr_el1());
}
static uint64_t cpu_pwrdwn_req_handler(uint32_t id, uint32_t flags,
@@ -89,7 +89,7 @@
/* Deactivate CPU power down SGI */
plat_ic_end_of_interrupt(CPU_PWR_DOWN_REQ_INTR);
- return psci_cpu_off();
+ return (uint64_t)psci_cpu_off();
}
/**
@@ -101,19 +101,19 @@
*/
static void raise_pwr_down_interrupt(u_register_t mpidr)
{
- plat_ic_raise_el3_sgi(CPU_PWR_DOWN_REQ_INTR, mpidr);
+ plat_ic_raise_el3_sgi((int)CPU_PWR_DOWN_REQ_INTR, mpidr);
}
void request_cpu_pwrdwn(void)
{
- enum pm_ret_status ret;
+ int ret;
VERBOSE("CPU power down request received\n");
/* Send powerdown request to online secondary core(s) */
ret = psci_stop_other_cores(plat_my_core_pos(), PWRDWN_WAIT_TIMEOUT,
raise_pwr_down_interrupt);
- if (ret != (uint32_t)PSCI_E_SUCCESS) {
+ if (ret != PSCI_E_SUCCESS) {
ERROR("Failed to powerdown secondary core(s)\n");
}
@@ -132,7 +132,7 @@
(void)cookie;
uint32_t payload[4] = {0};
enum pm_ret_status ret;
- int ipi_status, i;
+ uint32_t ipi_status, i;
VERBOSE("Received IPI FIQ from firmware\n");
@@ -140,19 +140,19 @@
(void)plat_ic_acknowledge_interrupt();
/* Check status register for each IPI except PMC */
- for (i = (int32_t)IPI_ID_APU; i <= IPI_ID_5; i++) {
+ for (i = IPI_ID_APU; i <= IPI_ID_5; i++) {
ipi_status = ipi_mb_enquire_status(IPI_ID_APU, i);
/* If any agent other than PMC has generated IPI FIQ then send SGI to mbox driver */
- if ((uint32_t)ipi_status & IPI_MB_STATUS_RECV_PENDING) {
- plat_ic_raise_ns_sgi(MBOX_SGI_SHARED_IPI, read_mpidr_el1());
+ if ((ipi_status & IPI_MB_STATUS_RECV_PENDING) != 0U) {
+ plat_ic_raise_ns_sgi((int)MBOX_SGI_SHARED_IPI, read_mpidr_el1());
break;
}
}
/* If PMC has not generated interrupt then end ISR */
ipi_status = ipi_mb_enquire_status(IPI_ID_APU, IPI_ID_PMC);
- if (((uint32_t)ipi_status & IPI_MB_STATUS_RECV_PENDING) == 0U) {
+ if ((ipi_status & IPI_MB_STATUS_RECV_PENDING) == 0U) {
plat_ic_end_of_interrupt(id);
goto exit_label;
}
@@ -187,7 +187,7 @@
(void)psci_cpu_off();
}
break;
- case PM_RET_ERROR_INVALID_CRC:
+ case (uint32_t)PM_RET_ERROR_INVALID_CRC:
pm_ipi_irq_clear(primary_proc);
WARN("Invalid CRC in the payload\n");
break;
@@ -359,16 +359,16 @@
SMC_RET1(handle, (u_register_t)ret);
case (uint32_t)PM_FORCE_POWERDOWN:
- ret = pm_force_powerdown(pm_arg[0], pm_arg[1], security_flag);
+ ret = pm_force_powerdown(pm_arg[0], (uint8_t)pm_arg[1], security_flag);
SMC_RET1(handle, (u_register_t)ret);
case (uint32_t)PM_REQ_SUSPEND:
- ret = pm_req_suspend(pm_arg[0], pm_arg[1], pm_arg[2],
+ ret = pm_req_suspend(pm_arg[0], (uint8_t)pm_arg[1], pm_arg[2],
pm_arg[3], security_flag);
SMC_RET1(handle, (u_register_t)ret);
case (uint32_t)PM_ABORT_SUSPEND:
- ret = pm_abort_suspend(pm_arg[0], security_flag);
+ ret = pm_abort_suspend((enum pm_abort_reason)pm_arg[0], security_flag);
SMC_RET1(handle, (u_register_t)ret);
case (uint32_t)PM_SYSTEM_SHUTDOWN:
@@ -426,7 +426,7 @@
enum pm_ret_status ret;
ret = pm_get_callbackdata(result, ARRAY_SIZE(result), security_flag, 1U);
- if (ret != 0) {
+ if (ret != PM_RET_SUCCESS) {
result[0] = (uint32_t)ret;
}
@@ -597,7 +597,8 @@
return ret;
}
- ret = eemi_psci_debugfs_handler(api_id, pm_arg, handle, flags);
+ ret = eemi_psci_debugfs_handler(api_id, pm_arg, handle,
+ (uint32_t)flags);
if (ret != (uintptr_t)0) {
return ret;
}
diff --git a/plat/xilinx/versal/plat_psci.c b/plat/xilinx/versal/plat_psci.c
index 396d7c7..032339f 100644
--- a/plat/xilinx/versal/plat_psci.c
+++ b/plat/xilinx/versal/plat_psci.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,6 +22,9 @@
#include "pm_ipi.h"
#include "pm_svc_main.h"
+#define SEC_ENTRY_ADDRESS_MASK 0xFFFFFFFFUL
+#define RESUME_ADDR_SET 0x1UL
+
static uintptr_t versal_sec_entry;
static int32_t versal_pwr_domain_on(u_register_t mpidr)
@@ -42,8 +45,9 @@
}
/* Send request to PMC to wake up selected ACPU core */
- (void)pm_req_wakeup(proc->node_id, (versal_sec_entry & 0xFFFFFFFFU) | 0x1U,
- versal_sec_entry >> 32, 0, SECURE_FLAG);
+ (void)pm_req_wakeup(proc->node_id,
+ (uint32_t)((versal_sec_entry & SEC_ENTRY_ADDRESS_MASK) |
+ RESUME_ADDR_SET), versal_sec_entry >> 32, 0, SECURE_FLAG);
/* Clear power down request */
pm_client_wakeup(proc);
@@ -237,7 +241,8 @@
* invoking CPU_on function, during which resume address will
* be set.
*/
- ret = pm_feature_check((uint32_t)PM_SELF_SUSPEND, &version_type[0], SECURE_FLAG);
+ ret = (uint32_t)pm_feature_check((uint32_t)PM_SELF_SUSPEND,
+ &version_type[0], SECURE_FLAG);
if (ret == (uint32_t)PM_RET_SUCCESS) {
fw_api_version = version_type[0] & 0xFFFFU;
if (fw_api_version >= 3U) {
@@ -311,7 +316,7 @@
/*******************************************************************************
* Export the platform specific power ops.
******************************************************************************/
-int32_t plat_setup_psci_ops(uintptr_t sec_entrypoint,
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
const struct plat_psci_ops **psci_ops)
{
versal_sec_entry = sec_entrypoint;
diff --git a/plat/xilinx/versal/sip_svc_setup.c b/plat/xilinx/versal/sip_svc_setup.c
index 3027946..bb3f728 100644
--- a/plat/xilinx/versal/sip_svc_setup.c
+++ b/plat/xilinx/versal/sip_svc_setup.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -116,6 +116,6 @@
sip_svc,
OEN_SIP_START,
OEN_SIP_END,
- SMC_TYPE_FAST,
+ (uint8_t)SMC_TYPE_FAST,
sip_svc_setup,
sip_svc_smc_handler);
diff --git a/plat/xilinx/versal/versal_ipi.c b/plat/xilinx/versal/versal_ipi.c
index 74b082d..ac2a3c0 100644
--- a/plat/xilinx/versal/versal_ipi.c
+++ b/plat/xilinx/versal/versal_ipi.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -73,5 +73,6 @@
*/
void versal_ipi_config_table_init(void)
{
- ipi_config_table_init(versal_ipi_table, ARRAY_SIZE(versal_ipi_table));
+ ipi_config_table_init(versal_ipi_table,
+ (uint32_t)ARRAY_SIZE(versal_ipi_table));
}
diff --git a/services/spd/tlkd/tlkd.mk b/services/spd/tlkd/tlkd.mk
index fc8840d..6d71632 100644
--- a/services/spd/tlkd/tlkd.mk
+++ b/services/spd/tlkd/tlkd.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2024, ARM Limited and Contributors. All rights reserved.
+# Copyright (c) 2024-2025, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@@ -8,9 +8,11 @@
SPD_INCLUDES := -Iinclude/bl32/payloads
endif
-ifeq (${ENABLE_FEAT_D128}, 0)
+ifneq (${ENABLE_FEAT_D128}, 0)
+ $(error spd=tlkd will not work with ENABLE_FEAT_D128 enabled.)
+endif
+
SPD_SOURCES := services/spd/tlkd/tlkd_common.c \
services/spd/tlkd/tlkd_helpers.S \
services/spd/tlkd/tlkd_main.c \
services/spd/tlkd/tlkd_pm.c
-endif
\ No newline at end of file
diff --git a/services/std_svc/spm/spm_mm/spm_mm_main.c b/services/std_svc/spm/spm_mm/spm_mm_main.c
index 34e2c00..7fe826d 100644
--- a/services/std_svc/spm/spm_mm/spm_mm_main.c
+++ b/services/std_svc/spm/spm_mm/spm_mm_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -34,53 +34,19 @@
/*******************************************************************************
* Set state of a Secure Partition context.
******************************************************************************/
-void sp_state_set(sp_context_t *sp_ptr, sp_state_t state)
+static void sp_state_set(sp_context_t *sp_ptr, sp_state_t state)
{
- spin_lock(&(sp_ptr->state_lock));
sp_ptr->state = state;
spin_unlock(&(sp_ptr->state_lock));
}
/*******************************************************************************
- * Wait until the state of a Secure Partition is the specified one and change it
- * to the desired state.
+ * Change the state of a Secure Partition to the one specified.
******************************************************************************/
-void sp_state_wait_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to)
+static void sp_state_wait_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to)
{
- int success = 0;
-
- while (success == 0) {
- spin_lock(&(sp_ptr->state_lock));
-
- if (sp_ptr->state == from) {
- sp_ptr->state = to;
-
- success = 1;
- }
-
- spin_unlock(&(sp_ptr->state_lock));
- }
-}
-
-/*******************************************************************************
- * Check if the state of a Secure Partition is the specified one and, if so,
- * change it to the desired state. Returns 0 on success, -1 on error.
- ******************************************************************************/
-int sp_state_try_switch(sp_context_t *sp_ptr, sp_state_t from, sp_state_t to)
-{
- int ret = -1;
-
spin_lock(&(sp_ptr->state_lock));
-
- if (sp_ptr->state == from) {
- sp_ptr->state = to;
-
- ret = 0;
- }
-
- spin_unlock(&(sp_ptr->state_lock));
-
- return ret;
+ sp_ptr->state = to;
}
/*******************************************************************************