diff --git a/plat/rockchip/common/aarch64/platform_common.c b/plat/rockchip/common/aarch64/platform_common.c
index 25eab43..9a74314 100644
--- a/plat/rockchip/common/aarch64/platform_common.c
+++ b/plat/rockchip/common/aarch64/platform_common.c
@@ -5,7 +5,6 @@
  */
 
 #include <arch_helpers.h>
-#include <arm_gic.h>
 #include <bl_common.h>
 #include <cci.h>
 #include <debug.h>
diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c
index e5ee68f..b8ec8c1 100644
--- a/plat/rockchip/common/bl31_plat_setup.c
+++ b/plat/rockchip/common/bl31_plat_setup.c
@@ -4,7 +4,6 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <arm_gic.h>
 #include <assert.h>
 #include <bl_common.h>
 #include <console.h>
@@ -61,10 +60,12 @@
  * BL2 has flushed this information to memory, so we are guaranteed to pick up
  * good data.
  ******************************************************************************/
-void bl31_early_platform_setup(bl31_params_t *from_bl2,
-			       void *plat_params_from_bl2)
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+				u_register_t arg2, u_register_t arg3)
 {
 	static console_16550_t console;
+	struct rockchip_bl31_params *arg_from_bl2 = (struct rockchip_bl31_params *) arg0;
+	void *plat_params_from_bl2 = (void *) arg1;
 
 	params_early_setup(plat_params_from_bl2);
 
@@ -82,13 +83,13 @@
 	VERBOSE("bl31_setup\n");
 
 	/* Passing a NULL context is a critical programming error */
-	assert(from_bl2);
+	assert(arg_from_bl2);
 
-	assert(from_bl2->h.type == PARAM_BL31);
-	assert(from_bl2->h.version >= VERSION_1);
+	assert(arg_from_bl2->h.type == PARAM_BL31);
+	assert(arg_from_bl2->h.version >= VERSION_1);
 
-	bl32_ep_info = *from_bl2->bl32_ep_info;
-	bl33_ep_info = *from_bl2->bl33_ep_info;
+	bl32_ep_info = *arg_from_bl2->bl32_ep_info;
+	bl33_ep_info = *arg_from_bl2->bl33_ep_info;
 }
 
 /*******************************************************************************
diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h
index 5456773..e1e4f33 100644
--- a/plat/rockchip/common/include/plat_private.h
+++ b/plat/rockchip/common/include/plat_private.h
@@ -28,6 +28,14 @@
 extern uint32_t __sram_incbin_start, __sram_incbin_end;
 extern uint32_t __sram_incbin_real_end;
 
+struct rockchip_bl31_params {
+       param_header_t h;
+       image_info_t *bl31_image_info;
+       entry_point_info_t *bl32_ep_info;
+       image_info_t *bl32_image_info;
+       entry_point_info_t *bl33_ep_info;
+       image_info_t *bl33_image_info;
+};
 
 /******************************************************************************
  * The register have write-mask bits, it is mean, if you want to set the bits,
diff --git a/plat/rockchip/common/params_setup.c b/plat/rockchip/common/params_setup.c
index 3dac013..a7ba83e 100644
--- a/plat/rockchip/common/params_setup.c
+++ b/plat/rockchip/common/params_setup.c
@@ -4,7 +4,6 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <arm_gic.h>
 #include <assert.h>
 #include <bl_common.h>
 #include <console.h>
diff --git a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
index 991fe6c..d91ee0e 100644
--- a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
+++ b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S
@@ -48,5 +48,5 @@
 #endif
 	bl	sram_restore
 sys_resume:
-	bl	psci_entrypoint
+	bl	bl31_warm_entrypoint
 endfunc pmu_cpuson_entrypoint
diff --git a/plat/rockchip/common/rockchip_gicv2.c b/plat/rockchip/common/rockchip_gicv2.c
index afdc6aa..4705042 100644
--- a/plat/rockchip/common/rockchip_gicv2.c
+++ b/plat/rockchip/common/rockchip_gicv2.c
@@ -6,6 +6,7 @@
 
 #include <bl_common.h>
 #include <gicv2.h>
+#include <interrupt_props.h>
 #include <platform_def.h>
 #include <utils.h>
 
@@ -23,8 +24,8 @@
  * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
  * interrupts.
  *****************************************************************************/
-const unsigned int g0_interrupt_array[] = {
-	PLAT_RK_G1S_IRQS,
+static const interrupt_prop_t g0_interrupt_props[] = {
+	PLAT_RK_GICV2_G1S_IRQS
 };
 
 /*
@@ -35,8 +36,8 @@
 gicv2_driver_data_t rockchip_gic_data = {
 	.gicd_base = PLAT_RK_GICD_BASE,
 	.gicc_base = PLAT_RK_GICC_BASE,
-	.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
-	.g0_interrupt_array = g0_interrupt_array,
+	.interrupt_props = g0_interrupt_props,
+	.interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
 };
 
 /******************************************************************************
diff --git a/plat/rockchip/common/rockchip_gicv3.c b/plat/rockchip/common/rockchip_gicv3.c
index 0500da6..efbf1d1 100644
--- a/plat/rockchip/common/rockchip_gicv3.c
+++ b/plat/rockchip/common/rockchip_gicv3.c
@@ -6,6 +6,7 @@
 
 #include <bl_common.h>
 #include <gicv3.h>
+#include <interrupt_props.h>
 #include <platform.h>
 #include <platform_def.h>
 #include <utils.h>
@@ -23,14 +24,9 @@
 /* The GICv3 driver only needs to be initialized in EL3 */
 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
 
-/* Array of Group1 secure interrupts to be configured by the gic driver */
-const unsigned int g1s_interrupt_array[] = {
-	PLAT_RK_G1S_IRQS
-};
-
-/* Array of Group0 interrupts to be configured by the gic driver */
-const unsigned int g0_interrupt_array[] = {
-	PLAT_RK_G0_IRQS
+static const interrupt_prop_t g01s_interrupt_props[] = {
+	PLAT_RK_GICV3_G0_IRQS,
+	PLAT_RK_GICV3_G1S_IRQS
 };
 
 static unsigned int plat_rockchip_mpidr_to_core_pos(unsigned long mpidr)
@@ -41,10 +37,8 @@
 const gicv3_driver_data_t rockchip_gic_data = {
 	.gicd_base = PLAT_RK_GICD_BASE,
 	.gicr_base = PLAT_RK_GICR_BASE,
-	.g0_interrupt_num = ARRAY_SIZE(g0_interrupt_array),
-	.g1s_interrupt_num = ARRAY_SIZE(g1s_interrupt_array),
-	.g0_interrupt_array = g0_interrupt_array,
-	.g1s_interrupt_array = g1s_interrupt_array,
+	.interrupt_props = g01s_interrupt_props,
+	.interrupt_props_num = ARRAY_SIZE(g01s_interrupt_props),
 	.rdistif_num = PLATFORM_CORE_COUNT,
 	.rdistif_base_addrs = rdistif_base_addrs,
 	.mpidr_to_core_pos = plat_rockchip_mpidr_to_core_pos,