tree 57b52c2c7ce90141e0911634479a96eedac477b0
parent 8b76bf0c420cc93a38c40ac14be9c679481a3cee
author Govindraj Raja <govindraj.raja@arm.com> 1738959674 -0600
committer Varun Wadekar <vwadekar@nvidia.com> 1740765314 +0000

fix(cpus): workaround for Cortex-X4 erratum 2957258

Cortex-X4 erratum 2957258 that applies to r0p0, r0p1 and is fixed in
r0p2.

In EL3, reads of MPIDR_EL1 and MIDR_EL1 might incorrectly virtualize
which register to return when reading the value of
MPIDR_EL1/VMPIDR_EL2 and MIDR_EL1/VPIDR_EL2, respectively.

The workaround is to do an ISB prior to an MRS read to either
MPIDR_EL1 and MIDR_EL1.

SDEN documentation:
https://developer.arm.com/documentation/109148/latest/

Change-Id: I2d8e7f4ce19ca2e1d87527c31e7778d81aff0279
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
(cherry picked from commit 09c1edb84b9d2e91ce425b4300042751b3899434)