refactor(cpus): reorder Cortex-A510 errata by ascending order
Change-Id: Id6b4ae42d413f2c501c8200305cdb8068219912b
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index e10ebb0..5aaa738 100644
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -51,66 +51,6 @@
endfunc check_errata_1922240
/* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2288014.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0. (fixed in r1p1)
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2288014_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2288014
- cbz x0, 1f
-
- /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */
- mrs x0, CORTEX_A510_CPUACTLR_EL1
- mov x1, #1
- bfi x0, x1, #18, #1
- msr CORTEX_A510_CPUACTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2288014_wa
-
-func check_errata_2288014
- /* Applies to r1p0 and below */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2288014
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2042739.
- * This applies only to revisions r0p0, r0p1 and r0p2.
- * (fixed in r0p3)
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2042739_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2042739
- cbz x0, 1f
-
- /* Apply the workaround by disabling ReadPreferUnique. */
- mrs x0, CORTEX_A510_CPUECTLR_EL1
- mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE
- bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1
- msr CORTEX_A510_CPUECTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2042739_wa
-
-func check_errata_2042739
- /* Applies to revisions r0p0 - r0p2 */
- mov x1, #0x02
- b cpu_rev_var_ls
-endfunc check_errata_2042739
-
- /* --------------------------------------------------
* Errata Workaround for Cortex-A510 Errata #2041909.
* This applies only to revision r0p2 and it is fixed in
* r0p3. The issue is also present in r0p0 and r0p1 but
@@ -154,6 +94,107 @@
endfunc check_errata_2041909
/* --------------------------------------------------
+ * Errata Workaround for Cortex-A510 Errata #2042739.
+ * This applies only to revisions r0p0, r0p1 and r0p2.
+ * (fixed in r0p3)
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0, x1, x17
+ * --------------------------------------------------
+ */
+func errata_cortex_a510_2042739_wa
+ /* Check workaround compatibility. */
+ mov x17, x30
+ bl check_errata_2042739
+ cbz x0, 1f
+
+ /* Apply the workaround by disabling ReadPreferUnique. */
+ mrs x0, CORTEX_A510_CPUECTLR_EL1
+ mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE
+ bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1
+ msr CORTEX_A510_CPUECTLR_EL1, x0
+
+1:
+ ret x17
+endfunc errata_cortex_a510_2042739_wa
+
+func check_errata_2042739
+ /* Applies to revisions r0p0 - r0p2 */
+ mov x1, #0x02
+ b cpu_rev_var_ls
+endfunc check_errata_2042739
+
+ /* --------------------------------------------------
+ * Errata Workaround for Cortex-A510 Errata #2172148.
+ * This applies only to revisions r0p0, r0p1, r0p2,
+ * r0p3 and r1p0, and is fixed in r1p1.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0, x1, x17
+ * --------------------------------------------------
+ */
+func errata_cortex_a510_2172148_wa
+ /* Check workaround compatibility. */
+ mov x17, x30
+ bl check_errata_2172148
+ cbz x0, 1f
+
+ /*
+ * Force L2 allocation of transient lines by setting
+ * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
+ */
+ mrs x0, CORTEX_A510_CPUECTLR_EL1
+ mov x1, #1
+ bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
+ bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
+ msr CORTEX_A510_CPUECTLR_EL1, x0
+
+1:
+ ret x17
+endfunc errata_cortex_a510_2172148_wa
+
+func check_errata_2172148
+ /* Applies to r1p0 and lower */
+ mov x1, #0x10
+ b cpu_rev_var_ls
+endfunc check_errata_2172148
+
+ /* --------------------------------------------------
+ * Errata Workaround for Cortex-A510 Errata #2218950.
+ * This applies only to revisions r0p0, r0p1, r0p2,
+ * r0p3 and r1p0, and is fixed in r1p1.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0, x1, x17
+ * --------------------------------------------------
+ */
+func errata_cortex_a510_2218950_wa
+ /* Check workaround compatibility. */
+ mov x17, x30
+ bl check_errata_2218950
+ cbz x0, 1f
+
+ /* Source register for BFI */
+ mov x1, #1
+
+ /* Set bit 18 in CPUACTLR_EL1 */
+ mrs x0, CORTEX_A510_CPUACTLR_EL1
+ bfi x0, x1, #18, #1
+ msr CORTEX_A510_CPUACTLR_EL1, x0
+
+ /* Set bit 25 in CMPXACTLR_EL1 */
+ mrs x0, CORTEX_A510_CMPXACTLR_EL1
+ bfi x0, x1, #25, #1
+ msr CORTEX_A510_CMPXACTLR_EL1, x0
+
+1:
+ ret x17
+endfunc errata_cortex_a510_2218950_wa
+
+func check_errata_2218950
+ /* Applies to r1p0 and lower */
+ mov x1, #0x10
+ b cpu_rev_var_ls
+endfunc check_errata_2218950
+
+ /* --------------------------------------------------
* Errata Workaround for Cortex-A510 Errata #2250311.
* This applies only to revisions r0p0, r0p1, r0p2,
* r0p3 and r1p0, and is fixed in r1p1.
@@ -194,75 +235,34 @@
endfunc check_errata_2250311
/* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2218950.
+ * Errata Workaround for Cortex-A510 Errata #2288014.
* This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0, and is fixed in r1p1.
+ * r0p3 and r1p0. (fixed in r1p1)
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0, x1, x17
* --------------------------------------------------
*/
-func errata_cortex_a510_2218950_wa
+func errata_cortex_a510_2288014_wa
/* Check workaround compatibility. */
mov x17, x30
- bl check_errata_2218950
+ bl check_errata_2288014
cbz x0, 1f
- /* Source register for BFI */
- mov x1, #1
-
- /* Set bit 18 in CPUACTLR_EL1 */
+ /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */
mrs x0, CORTEX_A510_CPUACTLR_EL1
+ mov x1, #1
bfi x0, x1, #18, #1
msr CORTEX_A510_CPUACTLR_EL1, x0
- /* Set bit 25 in CMPXACTLR_EL1 */
- mrs x0, CORTEX_A510_CMPXACTLR_EL1
- bfi x0, x1, #25, #1
- msr CORTEX_A510_CMPXACTLR_EL1, x0
-
1:
- ret x17
-endfunc errata_cortex_a510_2218950_wa
+ ret x17
+endfunc errata_cortex_a510_2288014_wa
-func check_errata_2218950
- /* Applies to r1p0 and lower */
+func check_errata_2288014
+ /* Applies to r1p0 and below */
mov x1, #0x10
b cpu_rev_var_ls
-endfunc check_errata_2218950
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2172148.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0, and is fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2172148_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2172148
- cbz x0, 1f
-
- /*
- * Force L2 allocation of transient lines by setting
- * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
- */
- mrs x0, CORTEX_A510_CPUECTLR_EL1
- mov x1, #1
- bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
- bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
- msr CORTEX_A510_CPUECTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2172148_wa
-
-func check_errata_2172148
- /* Applies to r1p0 and lower */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2172148
+endfunc check_errata_2288014
/* ----------------------------------------------------
* Errata Workaround for Cortex-A510 Errata #2347730.