Fix MISRA C issues in BL1/BL2/BL31
Attempts to address MISRA compliance issues in BL1, BL2, and BL31 code.
Mainly issues like not using boolean expressions in conditionals,
conflicting variable names, ignoring return values without (void), adding
explicit casts, etc.
Change-Id: If1fa18ab621b9c374db73fa6eaa6f6e5e55c146a
Signed-off-by: John Powell <john.powell@arm.com>
diff --git a/include/lib/smccc.h b/include/lib/smccc.h
index 5e13e6f..26509ae 100644
--- a/include/lib/smccc.h
+++ b/include/lib/smccc.h
@@ -122,18 +122,18 @@
*/
#define DEFINE_SVC_UUID2(_name, _tl, _tm, _th, _cl, _ch, \
_n0, _n1, _n2, _n3, _n4, _n5) \
- CASSERT((uint32_t)(_tl) != (uint32_t) SMC_UNK, invalid_svc_uuid);\
+ CASSERT((uint32_t)(_tl) != (uint32_t)SMC_UNK, invalid_svc_uuid);\
static const uuid_t _name = { \
- {(_tl >> 24) & 0xFF, \
- (_tl >> 16) & 0xFF, \
- (_tl >> 8) & 0xFF, \
- (_tl & 0xFF)}, \
- {(_tm >> 8) & 0xFF, \
- (_tm & 0xFF)}, \
- {(_th >> 8) & 0xFF, \
- (_th & 0xFF)}, \
- _cl, _ch, \
- { _n0, _n1, _n2, _n3, _n4, _n5 } \
+ {((_tl) >> 24) & 0xFF, \
+ ((_tl) >> 16) & 0xFF, \
+ ((_tl) >> 8) & 0xFF, \
+ ((_tl) & 0xFF)}, \
+ {((_tm) >> 8) & 0xFF, \
+ ((_tm) & 0xFF)}, \
+ {((_th) >> 8) & 0xFF, \
+ ((_th) & 0xFF)}, \
+ (_cl), (_ch), \
+ { (_n0), (_n1), (_n2), (_n3), (_n4), (_n5) } \
}
/*