Unmask SError and Debug exceptions.
Any asynchronous exception caused by the firmware should be handled
in the firmware itself. For this reason, unmask SError exceptions
(and Debug ones as well) on all boot paths. Also route external
abort and SError interrupts to EL3, otherwise they will target EL1.
Change-Id: I9c191d2d0dcfef85f265641c8460dfbb4d112092
diff --git a/common/psci/psci_afflvl_suspend.c b/common/psci/psci_afflvl_suspend.c
index 030f15d..9a2c0cf 100644
--- a/common/psci/psci_afflvl_suspend.c
+++ b/common/psci/psci_afflvl_suspend.c
@@ -82,6 +82,8 @@
psci_secure_context[index].tcr = read_tcr();
psci_secure_context[index].ttbr = read_ttbr0();
psci_secure_context[index].vbar = read_vbar();
+ psci_secure_context[index].pstate =
+ read_daif() & (DAIF_ABT_BIT | DAIF_DBG_BIT);
/* Set the secure world (EL3) re-entry point after BL1 */
psci_entrypoint = (unsigned long) psci_aff_suspend_finish_entry;
@@ -370,6 +372,7 @@
* context in the right order.
*/
write_vbar(psci_secure_context[index].vbar);
+ write_daif(read_daif() | psci_secure_context[index].pstate);
write_mair(psci_secure_context[index].mair);
write_tcr(psci_secure_context[index].tcr);
write_ttbr0(psci_secure_context[index].ttbr);
diff --git a/common/psci/psci_private.h b/common/psci/psci_private.h
index 48d40d0..6505adf 100644
--- a/common/psci/psci_private.h
+++ b/common/psci/psci_private.h
@@ -64,6 +64,7 @@
unsigned long tcr;
unsigned long ttbr;
unsigned long vbar;
+ unsigned long pstate;
} secure_context;
/*******************************************************************************