Merge changes from topic "versal2-qemu" into integration
* changes:
fix(versal2): align QEMU APU GT frequency with silicon
fix(zynqmp): fix syscnt frequency for QEMU
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 6562139..117372f 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -311,10 +311,6 @@
- ``ERRATA_A78_1952683``: This applies errata 1952683 workaround to Cortex-A78
CPU. This needs to be enabled for revision r0p0, it is fixed in r1p0.
-- ``ERRATA_A78_2132060``: This applies errata 2132060 workaround to Cortex-A78
- CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2. It
- is still open.
-
- ``ERRATA_A78_2242635``: This applies errata 2242635 workaround to Cortex-A78
CPU. This needs to be enabled for revisions r1p0, r1p1, and r1p2. The issue
is present in r0p0 but there is no workaround. It is still open.
@@ -377,10 +373,6 @@
Cortex-A78C CPU. This needs to be enabled for revision r0p0. The erratum is
fixed in r0p1.
-- ``ERRATA_A78C_2132064`` : This applies errata 2132064 workaround to
- Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
- it is still open.
-
- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to
Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and
it is still open.
@@ -505,10 +497,6 @@
CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the
CPU. It is still open.
-- ``ERRATA_V1_2108267``: This applies errata 2108267 workaround to Neoverse-V1
- CPU. This needs to be enabled for revisions r0p0, r1p0, and r1p1 of the CPU.
- It is still open.
-
- ``ERRATA_V1_2216392``: This applies errata 2216392 workaround to Neoverse-V1
CPU. This needs to be enabled for revisions r1p0 and r1p1 of the CPU, the
issue is present in r0p0 as well but there is no workaround for that
@@ -545,10 +533,6 @@
For Neoverse V2, the following errata build flags are defined :
-- ``ERRATA_V2_2331132``: This applies errata 2331132 workaround to Neoverse-V2
- CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is still
- open.
-
- ``ERRATA_V2_2618597``: This applies errata 2618597 workaround to Neoverse-V2
CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in
r0p2.
@@ -609,10 +593,6 @@
Cortex-A710 CPU. This needs to be enabled for revision r2p0 of the CPU and
is still open.
-- ``ERRATA_A710_2058056``: This applies errata 2058056 workaround to
- Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
- and r2p1 of the CPU and is still open.
-
- ``ERRATA_A710_2267065``: This applies errata 2267065 workaround to
Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0
of the CPU and is fixed in r2p1.
@@ -686,9 +666,6 @@
- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
-- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2
- CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is still open.
-
- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
@@ -752,10 +729,6 @@
CPU. This needs to be enabled for revisions r0p0, r1p0, and r2p0 of the CPU,
it is still open.
-- ``ERRATA_X2_2058056``: This applies errata 2058056 workaround to Cortex-X2
- CPU. This needs to be enabled for revisions r0p0, r1p0, r2p0 and r2p1 of the CPU,
- it is still open.
-
- ``ERRATA_X2_2083908``: This applies errata 2083908 workaround to Cortex-X2
CPU. This needs to be enabled for revision r2p0 of the CPU, it is still open.
@@ -806,10 +779,6 @@
For Cortex-X3, the following errata build flags are defined :
-- ``ERRATA_X3_2070301``: This applies errata 2070301 workaround to the Cortex-X3
- CPU. This needs to be enabled only for revisions r0p0, r1p0, r1p1 and r1p2 of
- the CPU and is still open.
-
- ``ERRATA_X3_2266875``: This applies errata 2266875 workaround to the Cortex-X3
CPU. This needs to be enabled only for revisions r0p0 and r1p0 of the CPU, it
is fixed in r1p1.
diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h
index 650193c..a47a47e 100644
--- a/include/lib/cpus/aarch64/cortex_a710.h
+++ b/include/lib/cpus/aarch64/cortex_a710.h
@@ -52,14 +52,6 @@
#define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
/*******************************************************************************
- * CPU Auxiliary Control register specific definitions.
- ******************************************************************************/
-#define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5
-#define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
-#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
-#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
-
-/*******************************************************************************
* CPU Selected Instruction Private register specific definitions.
******************************************************************************/
#define CORTEX_A710_CPUPSELR_EL3 S3_6_C15_C8_0
diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h
index 2984f82..203bdfd 100644
--- a/include/lib/cpus/aarch64/cortex_a78.h
+++ b/include/lib/cpus/aarch64/cortex_a78.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -19,9 +19,6 @@
******************************************************************************/
#define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
-#define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
-#define CPUECTLR_EL1_PF_MODE_LSB U(6)
-#define CPUECTLR_EL1_PF_MODE_WIDTH U(2)
/*******************************************************************************
* CPU Power Control register specific definitions
diff --git a/include/lib/cpus/aarch64/cortex_a78c.h b/include/lib/cpus/aarch64/cortex_a78c.h
index d600eca..2033120 100644
--- a/include/lib/cpus/aarch64/cortex_a78c.h
+++ b/include/lib/cpus/aarch64/cortex_a78c.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,8 +24,6 @@
* CPU Extended Control register specific definitions.
******************************************************************************/
#define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4
-#define CORTEX_A78C_CPUECTLR_EL1_BIT_6 (ULL(1) << 6)
-#define CORTEX_A78C_CPUECTLR_EL1_BIT_7 (ULL(1) << 7)
#define CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN (ULL(1) << 53)
/*******************************************************************************
diff --git a/include/lib/cpus/aarch64/cortex_x2.h b/include/lib/cpus/aarch64/cortex_x2.h
index 9ec5177..4516339 100644
--- a/include/lib/cpus/aarch64/cortex_x2.h
+++ b/include/lib/cpus/aarch64/cortex_x2.h
@@ -19,15 +19,6 @@
#define CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
/*******************************************************************************
- * CPU Extended Control register 2 specific definitions
- ******************************************************************************/
-#define CORTEX_X2_CPUECTLR2_EL1 S3_0_C15_C1_5
-
-#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT U(11)
-#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
-#define CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9)
-
-/*******************************************************************************
* CPU Auxiliary Control register 3 specific definitions.
******************************************************************************/
#define CORTEX_X2_CPUACTLR3_EL1 S3_0_C15_C1_2
diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h
index 8834db1..2869ec8 100644
--- a/include/lib/cpus/aarch64/cortex_x3.h
+++ b/include/lib/cpus/aarch64/cortex_x3.h
@@ -49,15 +49,6 @@
#define CORTEX_X3_CPUACTLR6_EL1 S3_0_C15_C8_1
/*******************************************************************************
- * CPU Extended Control register 2 specific definitions.
- ******************************************************************************/
-#define CORTEX_X3_CPUECTLR2_EL1 S3_0_C15_C1_5
-
-#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB U(11)
-#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
-#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9)
-
-/*******************************************************************************
* CPU Auxiliary Control register 3 specific definitions.
******************************************************************************/
#define CORTEX_X3_CPUACTLR3_EL1 S3_0_C15_C1_2
diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h
index f5837d4..e4487c4 100644
--- a/include/lib/cpus/aarch64/neoverse_n2.h
+++ b/include/lib/cpus/aarch64/neoverse_n2.h
@@ -62,9 +62,6 @@
* CPU Auxiliary Control register specific definitions.
******************************************************************************/
#define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5
-#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
-#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
-#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
#define CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0)
#define CPUECTLR2_EL1_TXREQ_LSB U(0)
#define CPUECTLR2_EL1_TXREQ_WIDTH U(3)
diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h
index 1e2d7ea..bbba2a7 100644
--- a/include/lib/cpus/aarch64/neoverse_v1.h
+++ b/include/lib/cpus/aarch64/neoverse_v1.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,9 +22,6 @@
#define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1
#define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
-#define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
-#define CPUECTLR_EL1_PF_MODE_LSB U(6)
-#define CPUECTLR_EL1_PF_MODE_WIDTH U(2)
/*******************************************************************************
* CPU Power Control register specific definitions
diff --git a/include/lib/cpus/aarch64/neoverse_v2.h b/include/lib/cpus/aarch64/neoverse_v2.h
index 427cafa..cdbe2bb 100644
--- a/include/lib/cpus/aarch64/neoverse_v2.h
+++ b/include/lib/cpus/aarch64/neoverse_v2.h
@@ -32,9 +32,6 @@
* CPU Extended Control register 2 specific definitions.
******************************************************************************/
#define NEOVERSE_V2_CPUECTLR2_EL1 S3_0_C15_C1_5
-#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
-#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB U(11)
-#define NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
#define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_STATIC_FULL ULL(0)
#define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_LSB U(0)
#define NEOVERSE_V2_CPUECTLR2_EL1_TXREQ_WIDTH U(3)
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index 2e72de2..396bd14 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -249,7 +249,8 @@
void arm_bl1_plat_arch_setup(void);
/* BL2 utility functions */
-void arm_bl2_early_platform_setup(uintptr_t fw_config, struct meminfo *mem_layout);
+void arm_bl2_early_platform_setup(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3);
void arm_bl2_platform_setup(void);
void arm_bl2_plat_arch_setup(void);
uint32_t arm_get_spsr_for_bl32_entry(void);
@@ -273,13 +274,8 @@
void arm_bl2u_plat_arch_setup(void);
/* BL31 utility functions */
-#if TRANSFER_LIST
void arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3);
-#else
-void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
- uintptr_t hw_config, void *plat_params_from_bl2);
-#endif
void arm_bl31_platform_setup(void);
void arm_bl31_plat_runtime_setup(void);
void arm_bl31_plat_arch_setup(void);
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S
index 23f7850..54bb453 100644
--- a/lib/cpus/aarch64/cortex_a710.S
+++ b/lib/cpus/aarch64/cortex_a710.S
@@ -87,13 +87,6 @@
check_erratum_range cortex_a710, ERRATUM(2055002), CPU_REV(1, 0), CPU_REV(2, 0)
-workaround_reset_start cortex_a710, ERRATUM(2058056), ERRATA_A710_2058056
- sysreg_bitfield_insert CORTEX_A710_CPUECTLR2_EL1, CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV, \
- CPUECTLR2_EL1_PF_MODE_LSB, CPUECTLR2_EL1_PF_MODE_WIDTH
-workaround_reset_end cortex_a710, ERRATUM(2058056)
-
-check_erratum_ls cortex_a710, ERRATUM(2058056), CPU_REV(2, 1)
-
workaround_reset_start cortex_a710, ERRATUM(2081180), ERRATA_A710_2081180
ldr x0,=0x3
msr S3_6_c15_c8_0,x0
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index 36b0a04..b166823 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -99,16 +99,6 @@
check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0)
-workaround_reset_start cortex_a78, ERRATUM(2132060), ERRATA_A78_2132060
- /* Apply the workaround. */
- mrs x1, CORTEX_A78_CPUECTLR_EL1
- mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV
- bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
- msr CORTEX_A78_CPUECTLR_EL1, x1
-workaround_reset_end cortex_a78, ERRATUM(2132060)
-
-check_erratum_ls cortex_a78, ERRATUM(2132060), CPU_REV(1, 2)
-
workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635
ldr x0, =0x5
msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
index 8f2dea8..19d988e 100644
--- a/lib/cpus/aarch64/cortex_a78c.S
+++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -37,18 +37,6 @@
check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0)
-workaround_reset_start cortex_a78c, ERRATUM(2132064), ERRATA_A78C_2132064
- /* --------------------------------------------------------
- * Place the data prefetcher in the most conservative mode
- * to reduce prefetches by writing the following bits to
- * the value indicated: ecltr[7:6], PF_MODE = 2'b11
- * --------------------------------------------------------
- */
- sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, (CORTEX_A78C_CPUECTLR_EL1_BIT_6 | CORTEX_A78C_CPUECTLR_EL1_BIT_7)
-workaround_reset_end cortex_a78c, ERRATUM(2132064)
-
-check_erratum_range cortex_a78c, ERRATUM(2132064), CPU_REV(0, 1), CPU_REV(0, 2)
-
workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638
ldr x0, =0x5
msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
index ccdd3b8..910a6a9 100644
--- a/lib/cpus/aarch64/cortex_x2.S
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -50,13 +50,6 @@
check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0)
-workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056
- sysreg_bitfield_insert CORTEX_X2_CPUECTLR2_EL1, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV, \
- CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH
-workaround_reset_end cortex_x2, ERRATUM(2058056)
-
-check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 1)
-
workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180
/* Apply instruction patching sequence */
ldr x0, =0x3
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index 628642b..c4872fe 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -30,13 +30,6 @@
cpu_reset_prologue cortex_x3
-workaround_reset_start cortex_x3, ERRATUM(2070301), ERRATA_X3_2070301
- sysreg_bitfield_insert CORTEX_X3_CPUECTLR2_EL1, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV, \
- CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB, CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH
-workaround_reset_end cortex_x3, ERRATUM(2070301)
-
-check_erratum_ls cortex_x3, ERRATUM(2070301), CPU_REV(1, 2)
-
workaround_reset_start cortex_x3, ERRATUM(2266875), ERRATA_X3_2266875
sysreg_bit_set CORTEX_X3_CPUACTLR_EL1, BIT(22)
workaround_reset_end cortex_x3, ERRATUM(2266875)
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index 4f1d53d..7d9d7f1 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -79,16 +79,6 @@
check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0)
-workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953
- /* Apply instruction patching sequence */
- mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
- mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV
- bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH
- msr NEOVERSE_N2_CPUECTLR2_EL1, x1
-workaround_reset_end neoverse_n2, ERRATUM(2138953)
-
-check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3)
-
workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956
/* Apply instruction patching sequence */
ldr x0,=0x3
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index a3b05e1..f975be0 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -156,15 +156,6 @@
check_erratum_range neoverse_v1, ERRATUM(1966096), CPU_REV(1, 0), CPU_REV(1, 1)
-workaround_reset_start neoverse_v1, ERRATUM(2108267), ERRATA_V1_2108267
- mrs x1, NEOVERSE_V1_CPUECTLR_EL1
- mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV
- bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
- msr NEOVERSE_V1_CPUECTLR_EL1, x1
-workaround_reset_end neoverse_v1, ERRATUM(2108267)
-
-check_erratum_ls neoverse_v1, ERRATUM(2108267), CPU_REV(1, 2)
-
workaround_reset_start neoverse_v1, ERRATUM(2139242), ERRATA_V1_2139242
mov x0, #0x3
msr S3_6_C15_C8_0, x0
diff --git a/lib/cpus/aarch64/neoverse_v2.S b/lib/cpus/aarch64/neoverse_v2.S
index a320d44..ce84942 100644
--- a/lib/cpus/aarch64/neoverse_v2.S
+++ b/lib/cpus/aarch64/neoverse_v2.S
@@ -24,13 +24,6 @@
cpu_reset_prologue neoverse_v2
-workaround_reset_start neoverse_v2, ERRATUM(2331132), ERRATA_V2_2331132
- sysreg_bitfield_insert NEOVERSE_V2_CPUECTLR2_EL1, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_CNSRV, \
- NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_LSB, NEOVERSE_V2_CPUECTLR2_EL1_PF_MODE_WIDTH
-workaround_reset_end neoverse_v2, ERRATUM(2331132)
-
-check_erratum_ls neoverse_v2, ERRATUM(2331132), CPU_REV(0, 2)
-
workaround_reset_start neoverse_v2, ERRATUM(2618597), ERRATA_V2_2618597
/* Disable retention control for WFI and WFE. */
mrs x0, NEOVERSE_V2_CPUPWRCTLR_EL1
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 4cfa765..4b8de00 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -315,10 +315,6 @@
# to revision r0p0 of the A78 cpu and was fixed in the revision r1p0.
CPU_FLAG_LIST += ERRATA_A78_1952683
-# Flag to apply erratum 2132060 workaround during reset. This erratum applies
-# to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open.
-CPU_FLAG_LIST += ERRATA_A78_2132060
-
# Flag to apply erratum 2242635 workaround during reset. This erratum applies
# to revisions r1p0, r1p1, and r1p2 of the A78 cpu and is open. The issue is
# present in r0p0 as well but there is no workaround for that revision.
@@ -380,10 +376,6 @@
# It is still open.
CPU_FLAG_LIST += ERRATA_A78_AE_2712574
-# Flag to apply erratum 2132064 workaround during reset. This erratum applies
-# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
-CPU_FLAG_LIST += ERRATA_A78C_2132064
-
# Flag to apply erratum 2242638 workaround during reset. This erratum applies
# to revisions r0p1 and r0p2 of the A78C cpu. It is still open.
CPU_FLAG_LIST += ERRATA_A78C_2242638
@@ -523,10 +515,6 @@
# to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open.
CPU_FLAG_LIST += ERRATA_V1_2139242
-# Flag to apply erratum 2108267 workaround during reset. This erratum applies
-# to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open.
-CPU_FLAG_LIST += ERRATA_V1_2108267
-
# Flag to apply erratum 2216392 workaround during reset. This erratum applies
# to revisions r1p0 and r1p1 of the Neoverse V1 cpu and is still open. This
# issue exists in r0p0 as well but there is no workaround for that revision.
@@ -585,11 +573,6 @@
# to revision r2p0 of the Cortex-A710 cpu and is still open.
CPU_FLAG_LIST += ERRATA_A710_2083908
-# Flag to apply erratum 2058056 workaround during reset. This erratum applies
-# to revisions r0p0, r1p0, r2p0 and r2p1 of the Cortex-A710 cpu and is still
-# open.
-CPU_FLAG_LIST += ERRATA_A710_2058056
-
# Flag to apply erratum 2055002 workaround during reset. This erratum applies
# to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open.
CPU_FLAG_LIST += ERRATA_A710_2055002
@@ -680,10 +663,6 @@
# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2138956
-# Flag to apply erratum 2138953 workaround during reset. This erratum applies
-# to revision r0p0, r0p1, r0p2, r0p3 of the Neoverse N2 cpu and is still open.
-CPU_FLAG_LIST += ERRATA_N2_2138953
-
# Flag to apply erratum 2242415 workaround during reset. This erratum applies
# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2242415
@@ -751,10 +730,6 @@
# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_X2_2002765
-# Flag to apply erratum 2058056 workaround during reset. This erratum applies
-# to revisions r0p0, r1p0, r2p0 and r2p1 of the Cortex-X2 cpu and is still open.
-CPU_FLAG_LIST += ERRATA_X2_2058056
-
# Flag to apply erratum 2083908 workaround during reset. This erratum applies
# to revision r2p0 of the Cortex-X2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_X2_2083908
@@ -810,11 +785,6 @@
# of the Cortex-X2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_X2_3701772
-# Flag to apply erratum 2070301 workaround on reset. This erratum applies
-# to revisions r0p0, r1p0, r1p1 and r1p2 of the Cortex-X3 cpu and is
-# still open.
-CPU_FLAG_LIST += ERRATA_X3_2070301
-
# Flag to apply erratum 2266875 workaround during reset. This erratum applies
# to revisions r0p0 and r1p0 of the Cortex-X3 cpu, it is fixed in r1p1.
CPU_FLAG_LIST += ERRATA_X3_2266875
@@ -983,10 +953,6 @@
# applies to revision r0p0 and r0p1 of the Cortex-A520 cpu and is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_A520_2938996
-# Flag to apply erratum 2331132 workaround during reset. This erratum applies
-# to revisions r0p0, r0p1 and r0p2. It is still open.
-CPU_FLAG_LIST += ERRATA_V2_2331132
-
# Flag to apply erratum 2618597 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1. It is fixed in r0p2.
CPU_FLAG_LIST += ERRATA_V2_2618597
diff --git a/plat/arm/board/a5ds/a5ds_bl2_setup.c b/plat/arm/board/a5ds/a5ds_bl2_setup.c
index a0aa639..3e26188 100644
--- a/plat/arm/board/a5ds/a5ds_bl2_setup.c
+++ b/plat/arm/board/a5ds/a5ds_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,7 +9,7 @@
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
+ arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3);
}
void bl2_platform_setup(void)
diff --git a/plat/arm/board/fvp/fvp_bl2_setup.c b/plat/arm/board/fvp/fvp_bl2_setup.c
index 90d9608..989f058 100644
--- a/plat/arm/board/fvp/fvp_bl2_setup.c
+++ b/plat/arm/board/fvp/fvp_bl2_setup.c
@@ -52,10 +52,7 @@
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
{
-#if TRANSFER_LIST
- arg0 = arg3;
-#endif
- arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
+ arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3);
/* Initialize the platform config for future decision making */
fvp_config_setup();
diff --git a/plat/arm/board/fvp/fvp_bl31_setup.c b/plat/arm/board/fvp/fvp_bl31_setup.c
index e087565..aa7b875 100644
--- a/plat/arm/board/fvp/fvp_bl31_setup.c
+++ b/plat/arm/board/fvp/fvp_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -28,10 +28,7 @@
/* Initialize the console to provide early debug support */
arm_console_boot_init();
-#if TRANSFER_LIST
- arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
-#else
-#if !RESET_TO_BL31 && !RESET_TO_BL2
+#if !(TRANSFER_LIST || RESET_TO_BL31 || RESET_TO_BL2)
const struct dyn_cfg_dtb_info_t *soc_fw_config_info;
INFO("BL31 FCONF: FW_CONFIG address = %lx\n", (uintptr_t)arg1);
@@ -53,9 +50,9 @@
assert(hw_config_info != NULL);
assert(hw_config_info->secondary_config_addr != 0UL);
arg2 = hw_config_info->secondary_config_addr;
-#endif /* !RESET_TO_BL31 && !RESET_TO_BL2 */
- arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
-#endif /* TRANSFER_LIST */
+#endif /* !(TRANSFER_LIST || RESET_TO_BL31 || RESET_TO_BL2)*/
+
+ arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
/* Initialize the platform config for future decision making */
fvp_config_setup();
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index e43d025..8c114e7 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -433,7 +433,6 @@
$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG}))
ifeq (${TRANSFER_LIST}, 1)
-include lib/transfer_list/transfer_list.mk
ifeq ($(RESET_TO_BL31), 1)
FW_HANDOFF_SIZE := 20000
diff --git a/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c b/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c
index cc29f36..3209a1c 100644
--- a/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c
+++ b/plat/arm/board/fvp_ve/fvp_ve_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,7 +15,7 @@
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
{
- arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
+ arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3);
/* Initialize the platform config for future decision making */
fvp_ve_config_setup();
diff --git a/plat/arm/board/juno/juno_bl31_setup.c b/plat/arm/board/juno/juno_bl31_setup.c
index 7a0a6d9..2eec105 100644
--- a/plat/arm/board/juno/juno_bl31_setup.c
+++ b/plat/arm/board/juno/juno_bl31_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,7 +27,7 @@
arg1 = soc_fw_config_info->config_addr;
}
- arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+ arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
/*
* Initialize Interconnect for this cluster during cold boot.
diff --git a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
index 2dd8b45..bb89c04 100644
--- a/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/common/nrd_bl31_setup.c
@@ -179,7 +179,7 @@
arg1 = soc_fw_config_info->config_addr;
}
#endif /* SPMD_SPM_AT_SEL2 && !RESET_TO_BL31 */
- arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+ arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
}
/*******************************************************************************
diff --git a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
index 5776948..421c14e 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdn2/platform.mk
@@ -125,7 +125,6 @@
ERRATA_N2_2025414 := 1
ERRATA_N2_2189731 := 1
ERRATA_N2_2138956 := 1
-ERRATA_N2_2138953 := 1
ERRATA_N2_2242415 := 1
ERRATA_N2_2138958 := 1
ERRATA_N2_2242400 := 1
diff --git a/plat/arm/board/tc/tc_bl31_setup.c b/plat/arm/board/tc/tc_bl31_setup.c
index 5d19aeb..66d921d 100644
--- a/plat/arm/board/tc/tc_bl31_setup.c
+++ b/plat/arm/board/tc/tc_bl31_setup.c
@@ -154,7 +154,10 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
+ /* Initialize the console to provide early debug support */
+ arm_console_boot_init();
+
+ arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
/* Fill the properties struct with the info from the config dtb */
fconf_populate("FW_CONFIG", arg1);
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 17dc0ed..6418628 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -66,8 +66,8 @@
* in x0. This memory layout is sitting at the base of the free trusted SRAM.
* Copy it to a safe location before its reclaimed by later BL2 functionality.
******************************************************************************/
-void arm_bl2_early_platform_setup(uintptr_t fw_config,
- struct meminfo *mem_layout)
+void arm_bl2_early_platform_setup(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
struct transfer_list_entry *te __unused;
int __maybe_unused ret;
@@ -76,8 +76,7 @@
arm_console_boot_init();
#if TRANSFER_LIST
- // TODO: modify the prototype of this function fw_config != bl2_tl
- secure_tl = (struct transfer_list_header *)fw_config;
+ secure_tl = (struct transfer_list_header *)arg3;
te = transfer_list_find(secure_tl, TL_TAG_SRAM_LAYOUT64);
assert(te != NULL);
@@ -85,11 +84,11 @@
bl2_tzram_layout = *(meminfo_t *)transfer_list_entry_data(te);
transfer_list_rem(secure_tl, te);
#else
- config_base = fw_config;
+ config_base = (uintptr_t)arg0;
/* Setup the BL2 memory layout */
- bl2_tzram_layout = *mem_layout;
-#endif
+ bl2_tzram_layout = *(meminfo_t *)arg1;
+#endif /* TRANSFER_LIST */
/* Initialise the IO layer and register platform IO devices */
plat_arm_io_setup();
@@ -105,9 +104,10 @@
#endif /* ARM_GPT_SUPPORT */
}
-void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
+void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
{
- arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
+ arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3);
generic_delay_timer_init();
}
diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c
index b67df36..bf2d8cd 100644
--- a/plat/arm/common/arm_bl31_setup.c
+++ b/plat/arm/common/arm_bl31_setup.c
@@ -154,10 +154,10 @@
* while creating page tables. BL2 has flushed this information to memory, so
* we are guaranteed to pick up good data.
******************************************************************************/
-#if TRANSFER_LIST
void __init arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+#if TRANSFER_LIST
#if RESET_TO_BL31
/* Populate entry point information for BL33 */
SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
@@ -208,18 +208,11 @@
}
}
#endif /* RESET_TO_BL31 */
-}
-#else
-void __init arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
- uintptr_t hw_config, void *plat_params_from_bl2)
-{
- /* Initialize the console to provide early debug support */
- arm_console_boot_init();
-
+#else /* (!TRANSFER_LIST) */
#if RESET_TO_BL31
/* There are no parameters from BL2 if BL31 is a reset vector */
- assert(from_bl2 == NULL);
- assert(plat_params_from_bl2 == NULL);
+ assert((void *)arg0 == NULL);
+ assert((void *)arg3 == NULL);
# ifdef BL32_BASE
/* Populate entry point information for BL32 */
@@ -258,21 +251,18 @@
*/
rmm_image_ep_info.pc = RMM_BASE;
#endif /* ENABLE_RME */
-
#else /* RESET_TO_BL31 */
-
/*
- * In debug builds, we pass a special value in 'plat_params_from_bl2'
+ * In debug builds, we pass a special value in 'arg3'
* to verify platform parameters from BL2 to BL31.
* In release builds, it's not used.
*/
- assert(((unsigned long long)plat_params_from_bl2) ==
- ARM_BL31_PLAT_PARAM_VAL);
+ assert(((unsigned long long)arg3) == ARM_BL31_PLAT_PARAM_VAL);
/*
* Check params passed from BL2 should not be NULL,
*/
- bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
+ bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
assert(params_from_bl2 != NULL);
assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
assert(params_from_bl2->h.version >= VERSION_2);
@@ -325,7 +315,7 @@
#endif
#endif /* RESET_TO_BL31 */
-# if ARM_LINUX_KERNEL_AS_BL33
+#if ARM_LINUX_KERNEL_AS_BL33
/*
* According to the file ``Documentation/arm64/booting.txt`` of the
* Linux kernel tree, Linux expects the physical address of the device
@@ -339,23 +329,19 @@
#if RESET_TO_BL31
bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
#else
- bl33_image_ep_info.args.arg0 = (u_register_t)hw_config;
-#endif
+ bl33_image_ep_info.args.arg0 = arg2;
+#endif /* RESET_TO_BL31 */
bl33_image_ep_info.args.arg1 = 0U;
bl33_image_ep_info.args.arg2 = 0U;
bl33_image_ep_info.args.arg3 = 0U;
-# endif
+#endif /* ARM_LINUX_KERNEL_AS_BL33 */
+#endif /* TRANSFER_LIST */
}
-#endif
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
-#if TRANSFER_LIST
arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3);
-#else
- arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
-#endif
/*
* Initialize Interconnect for this cluster during cold boot.
diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk
index c8f6b41..3dd38cd 100644
--- a/plat/arm/common/arm_common.mk
+++ b/plat/arm/common/arm_common.mk
@@ -311,6 +311,7 @@
plat/common/plat_psci_common.c
ifeq (${TRANSFER_LIST}, 1)
+ include lib/transfer_list/transfer_list.mk
TRANSFER_LIST_SOURCES += plat/arm/common/arm_transfer_list.c
endif
diff --git a/plat/arm/css/common/css_bl2_setup.c b/plat/arm/css/common/css_bl2_setup.c
index 1e055c5..995ef78 100644
--- a/plat/arm/css/common/css_bl2_setup.c
+++ b/plat/arm/css/common/css_bl2_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -56,7 +56,7 @@
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
+ arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3);
/* Save SCP Boot config before it gets overwritten by SCP_BL2 loading */
scp_boot_config = mmio_read_32(SCP_BOOT_CFG_ADDR);
diff --git a/plat/intel/soc/agilex/bl31_plat_setup.c b/plat/intel/soc/agilex/bl31_plat_setup.c
index 4c10e7b..a3c3545 100644
--- a/plat/intel/soc/agilex/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex/bl31_plat_setup.c
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -175,6 +175,16 @@
mmio_write_64(PLAT_CPU_RELEASE_ADDR,
(uint64_t)plat_secondary_cpus_bl31_entry);
+#if SIP_SVC_V3
+ /*
+ * Re-initialize the mailbox to include V3 specific routines.
+ * In V3, this re-initialize is required because prior to BL31, U-Boot
+ * SPL has its own mailbox settings and this initialization will
+ * override to those settings as required by the V3 framework.
+ */
+ mailbox_init();
+#endif
+
mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
}
diff --git a/plat/intel/soc/agilex5/bl31_plat_setup.c b/plat/intel/soc/agilex5/bl31_plat_setup.c
index 20701a4..9cf1e11 100644
--- a/plat/intel/soc/agilex5/bl31_plat_setup.c
+++ b/plat/intel/soc/agilex5/bl31_plat_setup.c
@@ -177,6 +177,17 @@
gicv3_distif_init();
gicv3_rdistif_init(plat_my_core_pos());
gicv3_cpuif_enable(plat_my_core_pos());
+
+#if SIP_SVC_V3
+ /*
+ * Re-initialize the mailbox to include V3 specific routines.
+ * In V3, this re-initialize is required because prior to BL31, U-Boot
+ * SPL has its own mailbox settings and this initialization will
+ * override to those settings as required by the V3 framework.
+ */
+ mailbox_init();
+#endif
+
mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
}
diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h
index e2efeb1..6325d35 100644
--- a/plat/intel/soc/common/include/platform_def.h
+++ b/plat/intel/soc/common/include/platform_def.h
@@ -1,7 +1,7 @@
/*
* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -207,6 +207,9 @@
#define MAX_IO_DEVICES 4
#define MAX_IO_BLOCK_DEVICES 2
+/* Define this, to support the SiPSVC V3 implementation. */
+#define SIP_SVC_V3 1
+
#ifndef __ASSEMBLER__
struct socfpga_bl31_params {
param_header_t h;
diff --git a/plat/intel/soc/common/include/socfpga_fcs.h b/plat/intel/soc/common/include/socfpga_fcs.h
index 6bb70e0..f92678f 100644
--- a/plat/intel/soc/common/include/socfpga_fcs.h
+++ b/plat/intel/soc/common/include/socfpga_fcs.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -88,12 +89,22 @@
#define FCS_ECDSA_HASH_SIG_VERIFY_CMD_MAX_WORD_SIZE 52U
#define FCS_ECDH_REQUEST_CMD_MAX_WORD_SIZE 29U
-#define FCS_CRYPTO_ECB_BUFFER_SIZE 12U
-#define FCS_CRYPTO_CBC_CTR_BUFFER_SIZE 28U
-#define FCS_CRYPTO_BLOCK_MODE_MASK 0x07
-#define FCS_CRYPTO_ECB_MODE 0x00
-#define FCS_CRYPTO_CBC_MODE 0x01
-#define FCS_CRYPTO_CTR_MODE 0x02
+#define FCS_CRYPTO_ECB_BUFFER_SIZE 12U
+#define FCS_CRYPTO_CBC_CTR_BUFFER_SIZE 28U
+#define FCS_CRYPTO_BLOCK_MODE_MASK 0x07
+#define FCS_CRYPTO_ECB_MODE 0x00
+#define FCS_CRYPTO_CBC_MODE 0x01
+#define FCS_CRYPTO_CTR_MODE 0x02
+#define FCS_CRYPTO_GCM_MODE 0x03
+#define FCS_CRYPTO_GCM_GHASH_MODE 0x04
+
+#define FCS_HKDF_REQUEST_DATA_SIZE 512U
+#define FCS_HKDF_KEY_OBJ_MAX_SIZE 352U
+#define FCS_HKDF_KEY_DATA_SIZE 168U
+#define FCS_HKDF_STEP0_1_KEY_OBJ_SIZE_BITS 384U
+#define FCS_HKDF_STEP2_KEY_OBJ_SIZE_BITS 256U
+#define FCS_HKDF_INPUT_BLOCK_SIZE 80U
+#define FCS_HKDF_SHA2_384_KEY_DATA_SIZE 48U
/* FCS Payload Structure */
typedef struct fcs_rng_payload_t {
@@ -183,10 +194,12 @@
uint32_t *mbox_error);
int intel_fcs_random_number_gen_ext(uint32_t session_id, uint32_t context_id,
uint32_t size, uint32_t *send_id);
-uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size,
+uint32_t intel_fcs_send_cert(uint32_t smc_fid, uint32_t trans_id,
+ uint64_t addr, uint64_t size,
uint32_t *send_id);
uint32_t intel_fcs_get_provision_data(uint32_t *send_id);
-uint32_t intel_fcs_cntr_set_preauth(uint8_t counter_type,
+uint32_t intel_fcs_cntr_set_preauth(uint32_t smc_fid, uint32_t trans_id,
+ uint8_t counter_type,
int32_t counter_value,
uint32_t test_bit,
uint32_t *mbox_error);
@@ -198,14 +211,18 @@
uint32_t dst_addr, uint32_t dst_size,
uint32_t *send_id);
-int intel_fcs_encryption_ext(uint32_t session_id, uint32_t context_id,
+int intel_fcs_encryption_ext(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
uint32_t src_addr, uint32_t src_size,
uint32_t dst_addr, uint32_t *dst_size,
- uint32_t *mbox_error);
-int intel_fcs_decryption_ext(uint32_t sesion_id, uint32_t context_id,
+ uint32_t *mbox_error, uint32_t smmu_src_addr,
+ uint32_t smmu_dst_addr);
+int intel_fcs_decryption_ext(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t sesion_id, uint32_t context_id,
uint32_t src_addr, uint32_t src_size,
uint32_t dst_addr, uint32_t *dst_size,
- uint32_t *mbox_error);
+ uint32_t *mbox_error, uint64_t owner_id,
+ uint32_t smmu_src_addr, uint32_t smmu_dst_addr);
int intel_fcs_sigma_teardown(uint32_t session_id, uint32_t *mbox_error);
int intel_fcs_chip_id(uint32_t *id_low, uint32_t *id_high, uint32_t *mbox_error);
@@ -218,9 +235,10 @@
uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size,
uint32_t *mbox_error);
-int intel_fcs_create_cert_on_reload(uint32_t cert_request,
- uint32_t *mbox_error);
-int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr,
+int intel_fcs_create_cert_on_reload(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t cert_request, uint32_t *mbox_error);
+int intel_fcs_get_attestation_cert(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t cert_request, uint64_t dst_addr,
uint32_t *dst_size, uint32_t *mbox_error);
int intel_fcs_open_crypto_service_session(uint32_t *session_id,
@@ -242,10 +260,12 @@
int intel_fcs_get_digest_init(uint32_t session_id, uint32_t context_id,
uint32_t key_id, uint32_t param_size,
uint64_t param_data, uint32_t *mbox_error);
-int intel_fcs_get_digest_update_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_get_digest_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
uint32_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t *dst_size,
- uint8_t is_finalised, uint32_t *mbox_error);
+ uint8_t is_finalised, uint32_t *mbox_error,
+ uint32_t smmu_src_addr);
int intel_fcs_get_digest_smmu_update_finalize(uint32_t session_id, uint32_t context_id,
uint32_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t *dst_size,
@@ -255,11 +275,12 @@
int intel_fcs_mac_verify_init(uint32_t session_id, uint32_t context_id,
uint32_t key_id, uint32_t param_size,
uint64_t param_data, uint32_t *mbox_error);
-int intel_fcs_mac_verify_update_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_mac_verify_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
uint32_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t *dst_size,
uint32_t data_size, uint8_t is_finalised,
- uint32_t *mbox_error);
+ uint32_t *mbox_error, uint64_t smmu_src_addr);
int intel_fcs_mac_verify_smmu_update_finalize(uint32_t session_id, uint32_t context_id,
uint32_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t *dst_size,
@@ -269,7 +290,8 @@
int intel_fcs_ecdsa_hash_sign_init(uint32_t session_id, uint32_t context_id,
uint32_t key_id, uint32_t param_size,
uint64_t param_data, uint32_t *mbox_error);
-int intel_fcs_ecdsa_hash_sign_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_ecdsa_hash_sign_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
uint32_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t *dst_size,
uint32_t *mbox_error);
@@ -277,7 +299,8 @@
int intel_fcs_ecdsa_hash_sig_verify_init(uint32_t session_id, uint32_t context_id,
uint32_t key_id, uint32_t param_size,
uint64_t param_data, uint32_t *mbox_error);
-int intel_fcs_ecdsa_hash_sig_verify_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_ecdsa_hash_sig_verify_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
uint32_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t *dst_size,
uint32_t *mbox_error);
@@ -286,11 +309,12 @@
uint32_t context_id, uint32_t key_id,
uint32_t param_size, uint64_t param_data,
uint32_t *mbox_error);
-int intel_fcs_ecdsa_sha2_data_sign_update_finalize(uint32_t session_id,
- uint32_t context_id, uint32_t src_addr,
- uint32_t src_size, uint64_t dst_addr,
- uint32_t *dst_size, uint8_t is_finalised,
- uint32_t *mbox_error);
+int intel_fcs_ecdsa_sha2_data_sign_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
+ uint32_t src_addr, uint32_t src_size,
+ uint64_t dst_addr, uint32_t *dst_size,
+ uint8_t is_finalised, uint32_t *mbox_error,
+ uint64_t smmu_src_addr);
int intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(uint32_t session_id,
uint32_t context_id, uint32_t src_addr,
uint32_t src_size, uint64_t dst_addr,
@@ -301,11 +325,12 @@
uint32_t context_id, uint32_t key_id,
uint32_t param_size, uint64_t param_data,
uint32_t *mbox_error);
-int intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(uint32_t session_id,
- uint32_t context_id, uint32_t src_addr,
- uint32_t src_size, uint64_t dst_addr,
- uint32_t *dst_size, uint32_t data_size,
- uint8_t is_finalised, uint32_t *mbox_error);
+int intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
+ uint32_t src_addr, uint32_t src_size,
+ uint64_t dst_addr, uint32_t *dst_size,
+ uint32_t data_size, uint8_t is_finalised,
+ uint32_t *mbox_error, uint64_t smmu_src_addr);
int intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize(uint32_t session_id,
uint32_t context_id, uint32_t src_addr,
uint32_t src_size, uint64_t dst_addr,
@@ -316,14 +341,16 @@
int intel_fcs_ecdsa_get_pubkey_init(uint32_t session_id, uint32_t context_id,
uint32_t key_id, uint32_t param_size,
uint64_t param_data, uint32_t *mbox_error);
-int intel_fcs_ecdsa_get_pubkey_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_ecdsa_get_pubkey_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
uint64_t dst_addr, uint32_t *dst_size,
uint32_t *mbox_error);
int intel_fcs_ecdh_request_init(uint32_t session_id, uint32_t context_id,
uint32_t key_id, uint32_t param_size,
uint64_t param_data, uint32_t *mbox_error);
-int intel_fcs_ecdh_request_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_ecdh_request_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
uint32_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t *dst_size,
uint32_t *mbox_error);
@@ -331,10 +358,16 @@
int intel_fcs_aes_crypt_init(uint32_t session_id, uint32_t context_id,
uint32_t key_id, uint64_t param_addr,
uint32_t param_size, uint32_t *mbox_error);
-int intel_fcs_aes_crypt_update_finalize(uint32_t session_id,
- uint32_t context_id, uint64_t src_addr,
- uint32_t src_size, uint64_t dst_addr,
- uint32_t dst_size, uint8_t is_finalised,
- uint32_t *send_id);
+int intel_fcs_aes_crypt_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
+ uint64_t src_addr, uint32_t src_size,
+ uint64_t dst_addr, uint32_t dst_size,
+ uint32_t aad_size, uint8_t is_finalised,
+ uint32_t *send_id, uint64_t smmu_src_addr,
+ uint64_t smmu_dst_addr);
+int intel_fcs_hkdf_request(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t step_type,
+ uint32_t mac_mode, uint32_t src_addr,
+ uint32_t key_uid, uint32_t op_key_size);
#endif /* SOCFPGA_FCS_H */
diff --git a/plat/intel/soc/common/include/socfpga_mailbox.h b/plat/intel/soc/common/include/socfpga_mailbox.h
index e27af21..f965b7d 100644
--- a/plat/intel/soc/common/include/socfpga_mailbox.h
+++ b/plat/intel/soc/common/include/socfpga_mailbox.h
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,20 +23,22 @@
#define MBOX_TEST_BIT BIT(31)
/* Mailbox Shared Memory Register Map */
-#define MBOX_CIN 0x00
-#define MBOX_ROUT 0x04
-#define MBOX_URG 0x08
-#define MBOX_INT 0x0C
-#define MBOX_COUT 0x20
-#define MBOX_RIN 0x24
-#define MBOX_STATUS 0x2C
-#define MBOX_CMD_BUFFER 0x40
-#define MBOX_RESP_BUFFER 0xC0
+#define MBOX_CIN 0x00 /* Command valid offset, to SDM */
+#define MBOX_ROUT 0x04 /* Response output offset, to SDM */
+#define MBOX_URG 0x08 /* Urgent command, to SDM */
+#define MBOX_INT 0x0C /* Interrupt enables, to SDM */
+/* 0x10 - 0x1F, Reserved */
-/* Mailbox SDM doorbell */
-#define MBOX_DOORBELL_TO_SDM 0x400
-#define MBOX_DOORBELL_FROM_SDM 0x480
+#define MBOX_COUT 0x20 /* Command free offset, from SDM */
+#define MBOX_RIN 0x24 /* Response valid offset, from SDM */
+#define MBOX_STATUS 0x2C /* Mailbox status from SDM to client */
+/* 0x30 - 0x3F, Reserved */
+#define MBOX_CMD_BUFFER 0x40 /* Circular buffer, cmds to SDM */
+#define MBOX_RESP_BUFFER 0xC0 /* Circular buffer, resp from SDM */
+
+#define MBOX_DOORBELL_TO_SDM 0x400 /* Doorbell from HPS to SDM */
+#define MBOX_DOORBELL_FROM_SDM 0x480 /* Doorbell from SDM to HPS */
/* Mailbox commands */
@@ -61,12 +63,15 @@
#define MBOX_HWMON_READVOLT 0x18
#define MBOX_HWMON_READTEMP 0x19
-
/* QSPI Commands */
#define MBOX_CMD_QSPI_OPEN 0x32
#define MBOX_CMD_QSPI_CLOSE 0x33
#define MBOX_CMD_QSPI_SET_CS 0x34
+#define MBOX_CMD_QSPI_ERASE 0x38
+#define MBOX_CMD_QSPI_WRITE 0x39
+#define MBOX_CMD_QSPI_READ 0x3A
#define MBOX_CMD_QSPI_DIRECT 0x3B
+#define MBOX_CMD_QSPI_GET_DEV_INFO 0x74
/* SEU Commands */
#define MBOX_CMD_SEU_ERR_READ 0x3C
@@ -94,12 +99,14 @@
#define MBOX_FCS_ECDSA_SHA2_DATA_SIGN_VERIFY 0x87
#define MBOX_FCS_ECDSA_GET_PUBKEY 0x88
#define MBOX_FCS_ECDH_REQUEST 0x89
+#define MBOX_FCS_HKDF_REQUEST 0x8B
#define MBOX_FCS_OPEN_CS_SESSION 0xA0
#define MBOX_FCS_CLOSE_CS_SESSION 0xA1
#define MBOX_FCS_IMPORT_CS_KEY 0xA5
#define MBOX_FCS_EXPORT_CS_KEY 0xA6
#define MBOX_FCS_REMOVE_CS_KEY 0xA7
#define MBOX_FCS_GET_CS_KEY_INFO 0xA8
+#define MBOX_FCS_CREATE_CS_KEY 0xA9
/* PSG SIGMA Commands */
#define MBOX_PSG_SIGMA_TEARDOWN 0xD5
@@ -111,7 +118,9 @@
#define MBOX_GET_MEASUREMENT 0x183
/* Miscellaneous commands */
+#define MBOX_CMD_MCTP_MSG 0x194
#define MBOX_GET_ROM_PATCH_SHA384 0x1B0
+#define MBOX_CMD_GET_DEVICEID 0x500
/* Mailbox Definitions */
@@ -120,6 +129,18 @@
#define CMD_CASUAL 0
#define CMD_URGENT 1
+/* Mailbox command flags and related macros */
+#define MBOX_CMD_FLAG_DIRECT BIT(0)
+#define MBOX_CMD_FLAG_INDIRECT BIT(1)
+#define MBOX_CMD_FLAG_CASUAL BIT(2)
+#define MBOX_CMD_FLAG_URGENT BIT(3)
+
+#define MBOX_CMD_FLAG_CASUAL_INDIRECT (MBOX_CMD_FLAG_CASUAL | \
+ MBOX_CMD_FLAG_INDIRECT)
+
+#define IS_CMD_SET(cmd, _type) ((((cmd) & MBOX_CMD_FLAG_##_type) != 0) ? \
+ 1 : 0)
+
#define MBOX_WORD_BYTE 4U
#define MBOX_RESP_BUFFER_SIZE 16
#define MBOX_CMD_BUFFER_SIZE 32
@@ -171,22 +192,25 @@
+ MBOX_WORD_BYTE * (ptr))
/* Mailbox interrupt flags and masks */
-#define MBOX_INT_FLAG_COE 0x1
-#define MBOX_INT_FLAG_RIE 0x2
-#define MBOX_INT_FLAG_UAE 0x100
-#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & 0x3)
-#define MBOX_UAE_BIT(INTERRUPT) (((INTERRUPT) & (1<<8)))
+#define MBOX_INT_FLAG_COE BIT(0) /* COUT update interrupt enable */
+#define MBOX_INT_FLAG_RIE BIT(1) /* RIN update interrupt enable */
+#define MBOX_INT_FLAG_UAE BIT(8) /* Urgent ACK interrupt enable */
+
+#define MBOX_COE_BIT(INTERRUPT) ((INTERRUPT) & MBOX_INT_FLAG_COE)
+#define MBOX_RIE_BIT(INTERRUPT) ((INTERRUPT) & MBOX_INT_FLAG_RIE)
+#define MBOX_UAE_BIT(INTERRUPT) ((INTERRUPT) & MBOX_INT_FLAG_UAE)
/* Mailbox response and status */
#define MBOX_RESP_ERR(BUFFER) ((BUFFER) & 0x000007ff)
#define MBOX_RESP_LEN(BUFFER) (((BUFFER) & 0x007ff000) >> 12)
#define MBOX_RESP_CLIENT_ID(BUFFER) (((BUFFER) & 0xf0000000) >> 28)
#define MBOX_RESP_JOB_ID(BUFFER) (((BUFFER) & 0x0f000000) >> 24)
+#define MBOX_RESP_TRANSACTION_ID(BUFFER) (((BUFFER) & 0xff000000) >> 24)
#define MBOX_STATUS_UA_MASK (1<<8)
/* Mailbox command and response */
#define MBOX_CLIENT_ID_CMD(CLIENT_ID) ((CLIENT_ID) << 28)
-#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID<<24)
+#define MBOX_JOB_ID_CMD(JOB_ID) (JOB_ID << 24)
#define MBOX_CMD_LEN_CMD(CMD_LEN) ((CMD_LEN) << 12)
#define MBOX_INDIRECT(val) ((val) << 11)
#define MBOX_CMD_MASK(header) ((header) & 0x7ff)
@@ -204,6 +228,17 @@
#define CONFIG_STATUS_FW_VER_OFFSET 1
#define CONFIG_STATUS_FW_VER_MASK 0x00FFFFFF
+/* QSPI mailbox command macros */
+#define MBOX_QSPI_SET_CS_OFFSET (28)
+#define MBOX_QSPI_SET_CS_MODE_OFFSET (27)
+#define MBOX_QSPI_SET_CS_CA_OFFSET (26)
+#define MBOX_QSPI_ERASE_SIZE_GRAN (0x400)
+
+#define MBOX_4K_ALIGNED_MASK (0xFFF)
+#define MBOX_IS_4K_ALIGNED(x) ((x) & MBOX_4K_ALIGNED_MASK)
+#define MBOX_IS_WORD_ALIGNED(x) (!((x) & 0x3))
+#define MBOX_QSPI_RW_MAX_WORDS (0x1000)
+
/* Data structure */
typedef struct mailbox_payload {
@@ -264,4 +299,107 @@
int mailbox_send_fpga_config_comp(void);
+#if SIP_SVC_V3
+#define MBOX_CLIENT_ID_SHIFT (28)
+#define MBOX_JOB_ID_SHIFT (24)
+#define MBOX_CMD_LEN_SHIFT (12)
+#define MBOX_INDIRECT_SHIFT (11)
+
+#define MBOX_FRAME_CMD_HEADER(client_id, job_id, args_len, indirect, cmd)\
+ ((client_id << MBOX_CLIENT_ID_SHIFT) | \
+ (job_id << MBOX_JOB_ID_SHIFT) | \
+ (args_len << MBOX_CMD_LEN_SHIFT) | \
+ (indirect << MBOX_CMD_LEN_SHIFT) | \
+ cmd)
+
+#define FLAG_SDM_RESPONSE_IS_VALID BIT(0)
+#define FLAG_SDM_RESPONSE_IS_USED BIT(1)
+#define FLAG_SDM_RESPONSE_IS_IN_PROGRESS BIT(2)
+#define FLAG_SDM_RESPONSE_IS_POLL_ON_INTR BIT(3)
+
+/*
+ * TODO: Re-visit this queue size based on the system load.
+ * 4 bits for client ID and 4 bits for job ID, total 8 bits and we can have up to
+ * 256 transactions. We can tune this based on our system load at any given time
+ */
+#define MBOX_SVC_CMD_QUEUE_SIZE (32)
+#define MBOX_SVC_RESP_QUEUE_SIZE (32)
+#define MBOX_SVC_MAX_JOB_ID (16)
+#define MBOX_SVC_CMD_ARG_SIZE (2)
+#define MBOX_SVC_CMD_IS_USED BIT(0)
+#define MBOX_SVC_CMD_CB_ARGS_SIZE (4)
+#define MBOX_SVC_MAX_CLIENTS (16)
+#define MBOX_SVC_MAX_RESP_DATA_SIZE (32)
+#define MBOX_SVC_SMC_RET_MAX_SIZE (8)
+
+/* Client ID(4bits) + Job ID(4bits) = Transcation ID(TID - 8bits, 256 combinations) */
+#define MBOX_MAX_TIDS (256)
+/* Each transcation ID bitmap holds 64bits */
+#define MBOX_TID_BITMAP_SIZE (sizeof(uint64_t) * 8)
+/* Number of transcation ID bitmaps required to hold 256 combinations */
+#define MBOX_MAX_TIDS_BITMAP (MBOX_MAX_TIDS / MBOX_TID_BITMAP_SIZE)
+
+/* SDM Response State (SRS) enums */
+typedef enum sdm_resp_state {
+ SRS_WAIT_FOR_RESP = 0x00U,
+ SRS_WAIT_FOR_HEADER,
+ SRS_WAIT_FOR_ARGUMENTS,
+ SRS_SYNC_ERROR
+} sdm_resp_state_t;
+
+/* SDM response data structure */
+typedef struct sdm_response {
+ bool is_poll_intr;
+ uint8_t client_id;
+ uint8_t job_id;
+ uint16_t resp_len;
+ uint16_t err_code;
+ uint32_t flags;
+ uint32_t header;
+ uint16_t rcvd_resp_len;
+ uint32_t resp_data[MBOX_SVC_MAX_RESP_DATA_SIZE];
+} sdm_response_t;
+
+/* SDM client callback template */
+typedef uint8_t (*sdm_command_callback)(void *resp, void *cmd,
+ uint32_t *ret_args);
+
+/* SDM command data structure */
+typedef struct sdm_command {
+ uint8_t client_id;
+ uint8_t job_id;
+ uint32_t flags;
+ sdm_command_callback cb;
+ uint32_t *cb_args;
+ uint8_t cb_args_len;
+} sdm_command_t;
+
+/* Get the transcation ID from client ID and job ID. */
+#define MBOX_GET_TRANS_ID(cid, jib) (((cid) << 4) | (jib))
+
+/* Mailbox service data structure */
+typedef struct mailbox_service {
+ sdm_resp_state_t resp_state;
+ sdm_resp_state_t next_resp_state;
+ uint32_t flags;
+ int curr_di;
+ uint64_t received_bitmap[MBOX_MAX_TIDS_BITMAP];
+ uint64_t interrupt_bitmap[MBOX_MAX_TIDS_BITMAP];
+ sdm_command_t cmd_queue[MBOX_SVC_CMD_QUEUE_SIZE];
+ sdm_response_t resp_queue[MBOX_SVC_RESP_QUEUE_SIZE];
+} mailbox_service_t;
+
+int mailbox_send_cmd_async_v3(uint8_t client_id, uint8_t job_id, uint32_t cmd,
+ uint32_t *args, uint32_t args_len, uint8_t cmd_flag,
+ sdm_command_callback cb, uint32_t *cb_args,
+ uint32_t cb_args_len);
+
+int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id, uint32_t *ret_args,
+ uint32_t *ret_args_size);
+
+int mailbox_response_poll_on_intr_v3(uint8_t *client_id, uint8_t *job_id,
+ uint64_t *bitmap);
+
+#endif /* #if SIP_SVC_V3 */
+
#endif /* SOCFPGA_MBOX_H */
diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h
index fc667cc..7f96adb 100644
--- a/plat/intel/soc/common/include/socfpga_sip_svc.h
+++ b/plat/intel/soc/common/include/socfpga_sip_svc.h
@@ -26,6 +26,10 @@
#define INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN 0x400
#define INTEL_SIP_SMC_CMD_V2_RANGE_END 0x4FF
+/* SiP V3 command code range */
+#define INTEL_SIP_SMC_CMD_V3_RANGE_BEGIN 0x00C8
+#define INTEL_SIP_SMC_CMD_V3_RANGE_END 0x01F4
+
/* SiP V2 protocol header */
#define INTEL_SIP_SMC_HEADER_JOB_ID_MASK 0xF
#define INTEL_SIP_SMC_HEADER_JOB_ID_OFFSET 0U
@@ -189,11 +193,11 @@
/*
* Increase if there is any backward compatibility impact
*/
-#define SIP_SVC_VERSION_MAJOR 2
+#define SIP_SVC_VERSION_MAJOR 3
/*
* Increase if there is new SMC function ID being added
*/
-#define SIP_SVC_VERSION_MINOR 2
+#define SIP_SVC_VERSION_MINOR 1
/* Structure Definitions */
@@ -243,4 +247,103 @@
void *handle,
u_register_t flags);
+
+#if SIP_SVC_V3
+#define SMC_RET_ARGS_ONE (1)
+#define SMC_RET_ARGS_TWO (2)
+#define SMC_RET_ARGS_THREE (3)
+#define SMC_RET_ARGS_FOUR (4)
+#define SMC_RET_ARGS_FIVE (5)
+#define SMC_RET_ARGS_SIX (6)
+
+/*
+ * SiP SVC Version3 SMC Functions IDs
+ */
+
+/* Generic response POLL commands */
+#define ALTERA_SIP_SMC_ASYNC_RESP_POLL (0x420000C8)
+#define ALTERA_SIP_SMC_ASYNC_RESP_POLL_ON_INTR (0x420000C9)
+
+/* QSPI related commands */
+#define ALTERA_SIP_SMC_ASYNC_QSPI_OPEN (0x420000CC)
+#define ALTERA_SIP_SMC_ASYNC_QSPI_CLOSE (0x420000CD)
+#define ALTERA_SIP_SMC_ASYNC_QSPI_SET_CS (0x420000CE)
+#define ALTERA_SIP_SMC_ASYNC_QSPI_ERASE (0x420000CF)
+#define ALTERA_SIP_SMC_ASYNC_QSPI_WRITE (0x420000D0)
+#define ALTERA_SIP_SMC_ASYNC_QSPI_READ (0x420000D1)
+#define ALTERA_SIP_SMC_ASYNC_GET_DEVICE_IDENTITY (0x420000D2)
+#define ALTERA_SIP_SMC_ASYNC_GET_IDCODE (0x420000D3)
+#define ALTERA_SIP_SMC_ASYNC_QSPI_GET_DEV_INFO (0x420000D4)
+
+#define ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP (0x420000E8)
+#define ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT (0x420000E9)
+
+/* FCS crypto service VAB/SDOS commands */
+#define ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER (0x4200012C)
+#define ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT (0x4200012D)
+#define ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION (0x4200012E)
+#define ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT (0x4200012F)
+#define ALTERA_SIP_SMC_ASYNC_FCS_SERVICE_REQUEST (0x42000130)
+#define ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE (0x42000131)
+#define ALTERA_SIP_SMC_ASYNC_FCS_GET_PROVISION_DATA (0x42000132)
+#define ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH (0x42000133)
+#define ALTERA_SIP_SMC_ASYNC_FCS_PSGSIGMA_TEARDOWN (0x42000134)
+#define ALTERA_SIP_SMC_ASYNC_FCS_CHIP_ID (0x42000135)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ATTESTATION_SUBKEY (0x42000136)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ATTESTATION_MEASUREMENTS (0x42000137)
+#define ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT (0x42000138)
+#define ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD (0x42000139)
+
+/* FCS crypto service session management commands */
+#define ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION (0x4200013A)
+#define ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION (0x4200013B)
+
+/* FCS crypto service key management commands */
+#define ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY (0x4200013C)
+#define ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY (0x4200013D)
+#define ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY (0x4200013E)
+#define ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO (0x4200013F)
+#define ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY (0x42000167)
+
+/* FCS crypto service primitive commands */
+#define ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_INIT (0x42000140)
+#define ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE (0x42000141)
+#define ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE (0x42000142)
+#define ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT (0x42000143)
+#define ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE (0x42000144)
+#define ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE (0x42000145)
+#define ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_SMMU_UPDATE (0x42000146)
+#define ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_SMMU_FINALIZE (0x42000147)
+#define ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT (0x42000148)
+#define ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE (0x42000149)
+#define ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE (0x4200014A)
+#define ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_SMMU_UPDATE (0x4200014B)
+#define ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_SMMU_FINALIZE (0x4200014C)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT (0x4200014D)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE (0x4200014E)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT (0x4200014F)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE (0x42000150)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE (0x42000151)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE (0x42000152)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE (0x42000153)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT (0x42000154)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE (0x42000155)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT (0x42000156)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE (0x42000157)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE (0x42000158)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE (0x42000159)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE (0x4200015A)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT (0x42000160)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE (0x42000161)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT (0x42000162)
+#define ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE (0x42000163)
+#define ALTERA_SIP_SMC_ASYNC_FCS_SDM_REMAPPER_CONFIG (0x42000164)
+#define ALTERA_SIP_SMC_ASYNC_MCTP_MSG (0x42000165)
+#define ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST (0x42000166)
+#define ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY (0x42000167)
+
+#define GET_CLIENT_ID(x) (((x) & 0xF0) >> 4)
+#define GET_JOB_ID(x) ((x) & 0x0F)
+#endif /* SIP_SVC_V3 */
+
#endif /* SOCFPGA_SIP_SVC_H */
diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
index 91df934..b9c7b59 100644
--- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c
+++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c
@@ -1,13 +1,15 @@
/*
* Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
+#include <common/debug.h>
#include <lib/mmio.h>
+#include "socfpga_plat_def.h"
#include "socfpga_fcs.h"
#include "socfpga_mailbox.h"
#include "socfpga_sip_svc.h"
@@ -23,6 +25,267 @@
static fcs_crypto_service_data fcs_ecdsa_get_pubkey_param;
static fcs_crypto_service_data fcs_ecdh_request_param;
+uint8_t fcs_send_cert_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ INFO("MBOX: %s: mailbox_err 0x%x, status_word %d\n",
+ __func__, resp->err_code, resp->resp_data[0]);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ ret_args[ret_args_len++] = resp->resp_data[0];
+
+ return ret_args_len;
+}
+
+uint8_t fcs_cntr_set_preauth_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ INFO("MBOX: %s: mailbox_err 0x%x\n", __func__, resp->err_code);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+
+ return ret_args_len;
+}
+
+uint8_t fcs_get_attest_cert_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ INFO("MBOX: %s: mailbox_err 0x%x, nbytes_ret %d\n",
+ __func__, resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+ return ret_args_len;
+}
+
+uint8_t fcs_hkdf_request_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+
+ INFO("MBOX: %s: mbox_err 0x%x, hkdf_status 0x%x\n", __func__,
+ resp->err_code, resp->resp_data[0]);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ ret_args[ret_args_len++] = resp->resp_data[0];
+
+ return ret_args_len;
+}
+
+uint8_t fcs_create_cert_reload_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ INFO("MBOX: %s: mailbox_err 0x%x\n", __func__, resp->err_code);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+
+ return ret_args_len;
+}
+
+uint8_t fcs_cs_get_digest_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ INFO("MBOX: %s: mbox_err 0x%x, nbytes_ret %d\n", __func__,
+ resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+ return ret_args_len;
+}
+
+uint8_t fcs_cs_mac_verify_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ INFO("MBOX: %s: mbox_err 0x%x, nbytes_ret %d, verify_result 0x%x\n",
+ __func__, resp->err_code,
+ resp->rcvd_resp_len * MBOX_WORD_BYTE,
+ resp->resp_data[3]);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+ ret_args[ret_args_len++] = resp->resp_data[3];
+
+ return ret_args_len;
+}
+
+uint8_t fcs_cs_hash_sign_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ INFO("MBOX: %s: [0] 0%x, [1] 0x%x, [2] 0x%x, len_words %d\n",
+ __func__, resp->resp_data[0], resp->resp_data[1],
+ resp->resp_data[2], resp->rcvd_resp_len);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+ return ret_args_len;
+}
+
+uint8_t fcs_cs_hash_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ INFO("MBOX: %s: [0] 0%x, [1] 0x%x, [2] 0x%x, [3] 0x%x\n",
+ __func__, resp->resp_data[0], resp->resp_data[1],
+ resp->resp_data[2], resp->resp_data[3]);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+ return ret_args_len;
+}
+
+uint8_t fcs_cs_aes_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+
+ INFO("MBOX: %s: mbox_err 0x%x, nbytes_ret %d\n", __func__,
+ resp->err_code, resp->resp_data[3]);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ ret_args[ret_args_len++] = resp->resp_data[3];
+
+ return ret_args_len;
+}
+
+uint8_t fcs_cs_data_sign_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ INFO("MBOX: %s: mbox_err 0x%x, nbytes_ret %d\n", __func__,
+ resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+ return ret_args_len;
+}
+
+uint8_t fcs_sdos_crypto_request_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ INFO("MBOX: %s: mailbox_err 0x%x, nbytes_ret %d\n",
+ __func__, resp->err_code, resp->resp_data[3]);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ /* Encrypted/Decrypted data size written to the destination buffer */
+ ret_args[ret_args_len++] = resp->resp_data[3];
+
+ return ret_args_len;
+}
+
+uint8_t fcs_cs_get_public_key_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ INFO("MBOX: %s: mbox_err 0x%x, nbytes_ret %u\n",
+ __func__, resp->err_code,
+ resp->rcvd_resp_len * MBOX_WORD_BYTE);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+ return ret_args_len;
+}
+
+uint8_t fcs_cs_data_sig_verify_req_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ INFO("MBOX: %s: mbox_err 0x%x, nbytes_ret 0x%x\n",
+ __func__, resp->err_code, resp->rcvd_resp_len);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+ return ret_args_len;
+}
+
+uint8_t fcs_cs_ecdh_request_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ INFO("MBOX: %s: [0] 0%x, [1] 0x%x, [2] 0x%x, len_words %d\n",
+ __func__, resp->resp_data[0], resp->resp_data[1],
+ resp->resp_data[2], resp->rcvd_resp_len);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+ return ret_args_len;
+}
+
bool is_size_4_bytes_aligned(uint32_t size)
{
if ((size % MBOX_WORD_BYTE) != 0U) {
@@ -155,7 +418,8 @@
return INTEL_SIP_SMC_STATUS_OK;
}
-uint32_t intel_fcs_send_cert(uint64_t addr, uint64_t size,
+uint32_t intel_fcs_send_cert(uint32_t smc_fid, uint32_t trans_id,
+ uint64_t addr, uint64_t size,
uint32_t *send_id)
{
int status;
@@ -168,7 +432,17 @@
return INTEL_SIP_SMC_STATUS_REJECTED;
}
- status = mailbox_send_cmd_async(send_id, MBOX_CMD_VAB_SRC_CERT,
+ status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE) ?
+ mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+ GET_JOB_ID(trans_id),
+ MBOX_CMD_VAB_SRC_CERT,
+ (uint32_t *) addr,
+ size / MBOX_WORD_BYTE,
+ MBOX_CMD_FLAG_CASUAL,
+ fcs_send_cert_cb,
+ NULL,
+ 0U) :
+ mailbox_send_cmd_async(send_id, MBOX_CMD_VAB_SRC_CERT,
(uint32_t *)addr, size / MBOX_WORD_BYTE,
CMD_DIRECT);
@@ -195,7 +469,8 @@
return INTEL_SIP_SMC_STATUS_OK;
}
-uint32_t intel_fcs_cntr_set_preauth(uint8_t counter_type, int32_t counter_value,
+uint32_t intel_fcs_cntr_set_preauth(uint32_t smc_fid, uint32_t trans_id,
+ uint8_t counter_type, int32_t counter_value,
uint32_t test_bit, uint32_t *mbox_error)
{
int status;
@@ -230,7 +505,18 @@
};
payload_size = sizeof(payload) / MBOX_WORD_BYTE;
- status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_CNTR_SET_PREAUTH,
+
+ status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH) ?
+ mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+ GET_JOB_ID(trans_id),
+ MBOX_FCS_CNTR_SET_PREAUTH,
+ (uint32_t *) &payload,
+ payload_size,
+ MBOX_CMD_FLAG_CASUAL,
+ fcs_cntr_set_preauth_cb,
+ NULL,
+ 0U) :
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_CNTR_SET_PREAUTH,
(uint32_t *) &payload, payload_size,
CMD_CASUAL, NULL, NULL);
@@ -317,14 +603,18 @@
return INTEL_SIP_SMC_STATUS_OK;
}
-int intel_fcs_encryption_ext(uint32_t session_id, uint32_t context_id,
+int intel_fcs_encryption_ext(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
uint32_t src_addr, uint32_t src_size,
- uint32_t dst_addr, uint32_t *dst_size, uint32_t *mbox_error)
+ uint32_t dst_addr, uint32_t *dst_size, uint32_t *mbox_error,
+ uint32_t smmu_src_addr, uint32_t smmu_dst_addr)
{
int status;
uint32_t payload_size;
uint32_t resp_len = FCS_CRYPTION_RESP_WORD_SIZE;
uint32_t resp_data[FCS_CRYPTION_RESP_WORD_SIZE] = {0U};
+ uint32_t src_addr_sdm = src_addr;
+ uint32_t dst_addr_sdm = dst_addr;
if ((dst_size == NULL) || (mbox_error == NULL)) {
return INTEL_SIP_SMC_STATUS_REJECTED;
@@ -339,19 +629,35 @@
return INTEL_SIP_SMC_STATUS_REJECTED;
}
+ /* On the Agilex5 platform, we will use the SMMU payload address */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ src_addr_sdm = smmu_src_addr;
+ dst_addr_sdm = smmu_dst_addr;
+#endif
+
fcs_encrypt_ext_payload payload = {
session_id,
context_id,
FCS_CRYPTION_CRYPTO_HEADER,
- src_addr,
+ src_addr_sdm,
src_size,
- dst_addr,
+ dst_addr_sdm,
*dst_size
};
payload_size = sizeof(payload) / MBOX_WORD_BYTE;
- status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ENCRYPT_REQ,
+ status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT) ?
+ mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+ GET_JOB_ID(trans_id),
+ MBOX_FCS_ENCRYPT_REQ,
+ (uint32_t *) &payload,
+ payload_size,
+ MBOX_CMD_FLAG_INDIRECT,
+ fcs_sdos_crypto_request_cb,
+ NULL,
+ 0U) :
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ENCRYPT_REQ,
(uint32_t *) &payload, payload_size,
CMD_CASUAL, resp_data, &resp_len);
@@ -371,15 +677,20 @@
return INTEL_SIP_SMC_STATUS_OK;
}
-int intel_fcs_decryption_ext(uint32_t session_id, uint32_t context_id,
+int intel_fcs_decryption_ext(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
uint32_t src_addr, uint32_t src_size,
- uint32_t dst_addr, uint32_t *dst_size, uint32_t *mbox_error)
+ uint32_t dst_addr, uint32_t *dst_size,
+ uint32_t *mbox_error, uint64_t owner_id,
+ uint32_t smmu_src_addr, uint32_t smmu_dst_addr)
{
int status;
uintptr_t id_offset;
uint32_t payload_size;
uint32_t resp_len = FCS_CRYPTION_RESP_WORD_SIZE;
uint32_t resp_data[FCS_CRYPTION_RESP_WORD_SIZE] = {0U};
+ uint32_t src_addr_sdm = src_addr;
+ uint32_t dst_addr_sdm = dst_addr;
if ((dst_size == NULL) || (mbox_error == NULL)) {
return INTEL_SIP_SMC_STATUS_REJECTED;
@@ -394,6 +705,12 @@
return INTEL_SIP_SMC_STATUS_REJECTED;
}
+ /* On the Agilex5 platform, we will use the SMMU payload address */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ src_addr_sdm = smmu_src_addr;
+ dst_addr_sdm = smmu_dst_addr;
+#endif
+
inv_dcache_range(src_addr, src_size); /* flush cache before mmio read to avoid reading old values */
id_offset = src_addr + FCS_OWNER_ID_OFFSET;
fcs_decrypt_ext_payload payload = {
@@ -402,15 +719,25 @@
FCS_CRYPTION_CRYPTO_HEADER,
{mmio_read_32(id_offset),
mmio_read_32(id_offset + MBOX_WORD_BYTE)},
- src_addr,
+ src_addr_sdm,
src_size,
- dst_addr,
+ dst_addr_sdm,
*dst_size
};
payload_size = sizeof(payload) / MBOX_WORD_BYTE;
- status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_DECRYPT_REQ,
+ status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT) ?
+ mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+ GET_JOB_ID(trans_id),
+ MBOX_FCS_DECRYPT_REQ,
+ (uint32_t *) &payload,
+ payload_size,
+ MBOX_CMD_FLAG_INDIRECT,
+ fcs_sdos_crypto_request_cb,
+ NULL,
+ 0U) :
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_DECRYPT_REQ,
(uint32_t *) &payload, payload_size,
CMD_CASUAL, resp_data, &resp_len);
@@ -567,7 +894,8 @@
return INTEL_SIP_SMC_STATUS_OK;
}
-int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr,
+int intel_fcs_get_attestation_cert(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t cert_request, uint64_t dst_addr,
uint32_t *dst_size, uint32_t *mbox_error)
{
int status;
@@ -586,7 +914,17 @@
return INTEL_SIP_SMC_STATUS_REJECTED;
}
- status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_GET_ATTESTATION_CERT,
+ status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT) ?
+ mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+ GET_JOB_ID(trans_id),
+ MBOX_GET_ATTESTATION_CERT,
+ (uint32_t *) &cert_request,
+ 1U,
+ MBOX_CMD_FLAG_CASUAL,
+ fcs_get_attest_cert_cb,
+ (uint32_t *)dst_addr,
+ 2U) :
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_GET_ATTESTATION_CERT,
(uint32_t *) &cert_request, 1U, CMD_CASUAL,
(uint32_t *) dst_addr, &ret_size);
@@ -601,8 +939,8 @@
return INTEL_SIP_SMC_STATUS_OK;
}
-int intel_fcs_create_cert_on_reload(uint32_t cert_request,
- uint32_t *mbox_error)
+int intel_fcs_create_cert_on_reload(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t cert_request, uint32_t *mbox_error)
{
int status;
@@ -615,7 +953,17 @@
return INTEL_SIP_SMC_STATUS_REJECTED;
}
- status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CREATE_CERT_ON_RELOAD,
+ status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD) ?
+ mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+ GET_JOB_ID(trans_id),
+ MBOX_CREATE_CERT_ON_RELOAD,
+ (uint32_t *) &cert_request,
+ 1U,
+ MBOX_CMD_FLAG_CASUAL,
+ fcs_create_cert_reload_cb,
+ NULL,
+ 0U) :
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_CREATE_CERT_ON_RELOAD,
(uint32_t *) &cert_request, 1U, CMD_CASUAL,
NULL, NULL);
@@ -851,11 +1199,12 @@
mbox_error);
}
-int intel_fcs_get_digest_update_finalize(uint32_t session_id,
- uint32_t context_id, uint32_t src_addr,
- uint32_t src_size, uint64_t dst_addr,
- uint32_t *dst_size, uint8_t is_finalised,
- uint32_t *mbox_error)
+int intel_fcs_get_digest_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
+ uint32_t src_addr, uint32_t src_size,
+ uint64_t dst_addr, uint32_t *dst_size,
+ uint8_t is_finalised, uint32_t *mbox_error,
+ uint32_t smmu_src_addr)
{
int status;
uint32_t i;
@@ -928,12 +1277,29 @@
i++;
}
/* Data source address and size */
+
+ /* On the Agilex5 platform, we will use the SMMU payload address */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ payload[i] = smmu_src_addr;
+#else
payload[i] = src_addr;
+#endif
i++;
payload[i] = src_size;
i++;
- status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_GET_DIGEST_REQ,
+ status = ((smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE) ||
+ (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE)) ?
+ mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+ GET_JOB_ID(trans_id),
+ MBOX_FCS_GET_DIGEST_REQ,
+ payload,
+ i,
+ MBOX_CMD_FLAG_CASUAL,
+ fcs_cs_get_digest_cb,
+ (uint32_t *)dst_addr,
+ 2U) :
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_GET_DIGEST_REQ,
payload, i, CMD_CASUAL,
(uint32_t *) dst_addr, &resp_len);
@@ -1061,11 +1427,12 @@
mbox_error);
}
-int intel_fcs_mac_verify_update_finalize(uint32_t session_id,
- uint32_t context_id, uint32_t src_addr,
- uint32_t src_size, uint64_t dst_addr,
- uint32_t *dst_size, uint32_t data_size,
- uint8_t is_finalised, uint32_t *mbox_error)
+int intel_fcs_mac_verify_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
+ uint32_t src_addr, uint32_t src_size,
+ uint64_t dst_addr, uint32_t *dst_size,
+ uint32_t data_size, uint8_t is_finalised,
+ uint32_t *mbox_error, uint64_t smmu_src_addr)
{
int status;
uint32_t i;
@@ -1149,8 +1516,13 @@
<< FCS_SHA_HMAC_CRYPTO_PARAM_SIZE_OFFSET;
i++;
}
+
/* Data source address and size */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ payload[i] = (uint32_t)smmu_src_addr;
+#else
payload[i] = src_addr;
+#endif
i++;
payload[i] = data_size;
i++;
@@ -1171,7 +1543,18 @@
i += (src_size - data_size) / MBOX_WORD_BYTE;
}
- status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_MAC_VERIFY_REQ,
+ status = ((smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE) ||
+ (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE)) ?
+ mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+ GET_JOB_ID(trans_id),
+ MBOX_FCS_MAC_VERIFY_REQ,
+ payload,
+ i,
+ MBOX_CMD_FLAG_CASUAL,
+ fcs_cs_mac_verify_cb,
+ (uint32_t *)dst_addr,
+ 2U) :
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_MAC_VERIFY_REQ,
payload, i, CMD_CASUAL,
(uint32_t *) dst_addr, &resp_len);
@@ -1336,7 +1719,8 @@
mbox_error);
}
-int intel_fcs_ecdsa_hash_sign_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_ecdsa_hash_sign_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
uint32_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t *dst_size,
uint32_t *mbox_error)
@@ -1407,7 +1791,17 @@
i += src_size / MBOX_WORD_BYTE;
- status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDSA_HASH_SIGN_REQ,
+ status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE) ?
+ mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+ GET_JOB_ID(trans_id),
+ MBOX_FCS_ECDSA_HASH_SIGN_REQ,
+ payload,
+ i,
+ MBOX_CMD_FLAG_CASUAL,
+ fcs_cs_hash_sign_req_cb,
+ (uint32_t *)dst_addr,
+ 2U) :
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDSA_HASH_SIGN_REQ,
payload, i, CMD_CASUAL, (uint32_t *) dst_addr,
&resp_len);
@@ -1435,7 +1829,8 @@
mbox_error);
}
-int intel_fcs_ecdsa_hash_sig_verify_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_ecdsa_hash_sig_verify_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
uint32_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t *dst_size,
uint32_t *mbox_error)
@@ -1451,8 +1846,8 @@
return INTEL_SIP_SMC_STATUS_REJECTED;
}
- if (fcs_ecdsa_hash_sig_verify_param.session_id != session_id ||
- fcs_ecdsa_hash_sig_verify_param.context_id != context_id) {
+ if ((fcs_ecdsa_hash_sig_verify_param.session_id != session_id) ||
+ (fcs_ecdsa_hash_sig_verify_param.context_id != context_id)) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
@@ -1508,7 +1903,18 @@
i += (src_size / MBOX_WORD_BYTE);
- status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDSA_HASH_SIG_VERIFY,
+ status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE) ?
+ mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+ GET_JOB_ID(trans_id),
+ MBOX_FCS_ECDSA_HASH_SIG_VERIFY,
+ payload,
+ i,
+ MBOX_CMD_FLAG_CASUAL,
+ fcs_cs_hash_sig_verify_req_cb,
+ (uint32_t *)dst_addr,
+ 2U) :
+
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDSA_HASH_SIG_VERIFY,
payload, i, CMD_CASUAL, (uint32_t *) dst_addr,
&resp_len);
@@ -1537,11 +1943,12 @@
mbox_error);
}
-int intel_fcs_ecdsa_sha2_data_sign_update_finalize(uint32_t session_id,
- uint32_t context_id, uint32_t src_addr,
- uint32_t src_size, uint64_t dst_addr,
- uint32_t *dst_size, uint8_t is_finalised,
- uint32_t *mbox_error)
+int intel_fcs_ecdsa_sha2_data_sign_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
+ uint32_t src_addr, uint32_t src_size,
+ uint64_t dst_addr, uint32_t *dst_size,
+ uint8_t is_finalised, uint32_t *mbox_error,
+ uint64_t smmu_src_addr)
{
int status;
int i;
@@ -1608,11 +2015,27 @@
}
/* Data source address and size */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ payload[i] = (uint32_t)smmu_src_addr;
+#else
payload[i] = src_addr;
+#endif
i++;
payload[i] = src_size;
i++;
- status = mailbox_send_cmd(MBOX_JOB_ID,
+
+ status = ((smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE) ||
+ (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE)) ?
+ mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+ GET_JOB_ID(trans_id),
+ MBOX_FCS_ECDSA_SHA2_DATA_SIGN_REQ,
+ payload,
+ i,
+ MBOX_CMD_FLAG_CASUAL,
+ fcs_cs_data_sign_req_cb,
+ (uint32_t *)dst_addr,
+ 2U) :
+ mailbox_send_cmd(MBOX_JOB_ID,
MBOX_FCS_ECDSA_SHA2_DATA_SIGN_REQ, payload,
i, CMD_CASUAL, (uint32_t *) dst_addr,
&resp_len);
@@ -1737,11 +2160,12 @@
mbox_error);
}
-int intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(uint32_t session_id,
- uint32_t context_id, uint32_t src_addr,
- uint32_t src_size, uint64_t dst_addr,
- uint32_t *dst_size, uint32_t data_size,
- uint8_t is_finalised, uint32_t *mbox_error)
+int intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
+ uint32_t src_addr, uint32_t src_size,
+ uint64_t dst_addr, uint32_t *dst_size,
+ uint32_t data_size, uint8_t is_finalised,
+ uint32_t *mbox_error, uint64_t smmu_src_addr)
{
int status;
uint32_t i;
@@ -1825,7 +2249,12 @@
}
/* Data source address and size */
+ /* On the Agilex5 platform, the SMMU remapped address is used */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ payload[i] = smmu_src_addr;
+#else
payload[i] = src_addr;
+#endif
i++;
payload[i] = data_size;
i++;
@@ -1846,7 +2275,18 @@
i += (src_size - data_size) / MBOX_WORD_BYTE;
}
- status = mailbox_send_cmd(MBOX_JOB_ID,
+ status = ((smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE) ||
+ (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE)) ?
+ mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+ GET_JOB_ID(trans_id),
+ MBOX_FCS_ECDSA_SHA2_DATA_SIGN_VERIFY,
+ payload,
+ i,
+ MBOX_CMD_FLAG_CASUAL,
+ fcs_cs_data_sig_verify_req_cb,
+ (uint32_t *)dst_addr,
+ 2U) :
+ mailbox_send_cmd(MBOX_JOB_ID,
MBOX_FCS_ECDSA_SHA2_DATA_SIGN_VERIFY, payload, i,
CMD_CASUAL, (uint32_t *) dst_addr, &resp_len);
@@ -2010,7 +2450,8 @@
mbox_error);
}
-int intel_fcs_ecdsa_get_pubkey_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_ecdsa_get_pubkey_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
uint64_t dst_addr, uint32_t *dst_size,
uint32_t *mbox_error)
{
@@ -2054,7 +2495,18 @@
INTEL_SIP_SMC_FCS_ECC_ALGO_MASK;
i++;
- status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDSA_GET_PUBKEY,
+ status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE) ?
+ mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+ GET_JOB_ID(trans_id),
+ MBOX_FCS_ECDSA_GET_PUBKEY,
+ payload,
+ i,
+ MBOX_CMD_FLAG_CASUAL,
+ fcs_cs_get_public_key_cb,
+ (uint32_t *)dst_addr,
+ 2U) :
+ mailbox_send_cmd(MBOX_JOB_ID,
+ MBOX_FCS_ECDSA_GET_PUBKEY,
payload, i, CMD_CASUAL,
(uint32_t *) dst_addr, &ret_size);
@@ -2082,7 +2534,8 @@
mbox_error);
}
-int intel_fcs_ecdh_request_finalize(uint32_t session_id, uint32_t context_id,
+int intel_fcs_ecdh_request_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
uint32_t src_addr, uint32_t src_size,
uint64_t dst_addr, uint32_t *dst_size,
uint32_t *mbox_error)
@@ -2098,7 +2551,6 @@
return INTEL_SIP_SMC_STATUS_REJECTED;
}
-
if (fcs_ecdh_request_param.session_id != session_id ||
fcs_ecdh_request_param.context_id != context_id) {
return INTEL_SIP_SMC_STATUS_REJECTED;
@@ -2110,10 +2562,9 @@
}
dst_size_check = *dst_size;
- if ((dst_size_check > FCS_MAX_DATA_SIZE ||
- dst_size_check < FCS_MIN_DATA_SIZE) ||
- (src_size > FCS_MAX_DATA_SIZE ||
- src_size < FCS_MIN_DATA_SIZE)) {
+
+ if ((dst_size_check > FCS_MAX_DATA_SIZE || dst_size_check < FCS_MIN_DATA_SIZE) ||
+ (src_size > FCS_MAX_DATA_SIZE || src_size < FCS_MIN_DATA_SIZE)) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
@@ -2150,7 +2601,17 @@
(void *) pubkey, src_size / MBOX_WORD_BYTE);
i += src_size / MBOX_WORD_BYTE;
- status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDH_REQUEST,
+ status = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE) ?
+ mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+ GET_JOB_ID(trans_id),
+ MBOX_FCS_ECDH_REQUEST,
+ payload,
+ i,
+ MBOX_CMD_FLAG_CASUAL,
+ fcs_cs_ecdh_request_cb,
+ (uint32_t *)dst_addr,
+ 2U) :
+ mailbox_send_cmd(MBOX_JOB_ID, MBOX_FCS_ECDH_REQUEST,
payload, i, CMD_CASUAL, (uint32_t *) dst_addr,
&resp_len);
@@ -2189,13 +2650,19 @@
}
/*
- * Check if not ECB, CBC and CTR mode, addr ptr is NULL.
- * Return "Reject" status
+ * Check if not ECB, CBC and CTR, GCM and GCM-GHASH mode (only for Agilex5),
+ * addr ptr is NULL. Return "Reject" status
*/
if ((param_addr_ptr == NULL) ||
- (((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_ECB_MODE) &&
- ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_CBC_MODE) &&
- ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_CTR_MODE))) {
+ (((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_ECB_MODE) &&
+ ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_CBC_MODE) &&
+ ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_CTR_MODE)
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ &&
+ ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_GCM_MODE) &&
+ ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) != FCS_CRYPTO_GCM_GHASH_MODE)
+#endif
+ )){
return INTEL_SIP_SMC_STATUS_REJECTED;
}
@@ -2204,7 +2671,9 @@
* Check CBC/CTR here and limit to size 28 bytes
*/
if ((((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_CBC_MODE) ||
- ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_CTR_MODE)) &&
+ ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_CTR_MODE) ||
+ ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_GCM_MODE) ||
+ ((*param_addr_ptr & FCS_CRYPTO_BLOCK_MODE_MASK) == FCS_CRYPTO_GCM_GHASH_MODE)) &&
(param_size > FCS_CRYPTO_CBC_CTR_BUFFER_SIZE)) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
@@ -2235,17 +2704,21 @@
return INTEL_SIP_SMC_STATUS_OK;
}
-int intel_fcs_aes_crypt_update_finalize(uint32_t session_id,
- uint32_t context_id, uint64_t src_addr,
- uint32_t src_size, uint64_t dst_addr,
- uint32_t dst_size, uint8_t is_finalised,
- uint32_t *send_id)
+int intel_fcs_aes_crypt_update_finalize(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t context_id,
+ uint64_t src_addr, uint32_t src_size,
+ uint64_t dst_addr, uint32_t dst_size,
+ uint32_t aad_size, uint8_t is_finalised,
+ uint32_t *send_id, uint64_t smmu_src_addr,
+ uint64_t smmu_dst_addr)
{
int status;
int i;
uint32_t flag;
uint32_t crypto_header;
uint32_t fcs_aes_crypt_payload[FCS_AES_CMD_MAX_WORD_SIZE];
+ uint32_t src_addr_sdm = (uint32_t)src_addr;
+ uint32_t dst_addr_sdm = (uint32_t)dst_addr;
if (fcs_aes_init_payload.session_id != session_id ||
fcs_aes_init_payload.context_id != context_id) {
@@ -2297,7 +2770,7 @@
i++;
if ((crypto_header >> FCS_CS_FIELD_FLAG_OFFSET) &
- FCS_CS_FIELD_FLAG_INIT) {
+ (FCS_CS_FIELD_FLAG_INIT)) {
fcs_aes_crypt_payload[i] = fcs_aes_init_payload.key_id;
i++;
@@ -2314,18 +2787,41 @@
i += fcs_aes_init_payload.param_size / MBOX_WORD_BYTE;
}
- fcs_aes_crypt_payload[i] = (uint32_t) src_addr;
+ /* On the Agilex5 platform, we will use the SMMU payload address */
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+ src_addr_sdm = (uint32_t)smmu_src_addr;
+ dst_addr_sdm = (uint32_t)smmu_dst_addr;
+#endif
+
+ fcs_aes_crypt_payload[i] = src_addr_sdm;
i++;
fcs_aes_crypt_payload[i] = src_size;
i++;
- fcs_aes_crypt_payload[i] = (uint32_t) dst_addr;
+ fcs_aes_crypt_payload[i] = dst_addr_sdm;
i++;
fcs_aes_crypt_payload[i] = dst_size;
i++;
- status = mailbox_send_cmd_async(send_id, MBOX_FCS_AES_CRYPT_REQ,
- fcs_aes_crypt_payload, i,
- CMD_INDIRECT);
+ /* Additional Authenticated Data size */
+ if (aad_size > 0) {
+ fcs_aes_crypt_payload[i] = aad_size;
+ i++;
+ }
+
+ status = ((smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE) ||
+ (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE)) ?
+ mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+ GET_JOB_ID(trans_id),
+ MBOX_FCS_AES_CRYPT_REQ,
+ fcs_aes_crypt_payload,
+ i,
+ MBOX_CMD_FLAG_INDIRECT,
+ fcs_cs_aes_cb,
+ NULL,
+ 0U) :
+ mailbox_send_cmd_async(send_id, MBOX_FCS_AES_CRYPT_REQ,
+ fcs_aes_crypt_payload, i, CMD_INDIRECT);
+
if (is_finalised != 0U) {
memset((void *)&fcs_aes_init_payload, 0,
@@ -2338,3 +2834,77 @@
return INTEL_SIP_SMC_STATUS_OK;
}
+
+int intel_fcs_hkdf_request(uint32_t smc_fid, uint32_t trans_id,
+ uint32_t session_id, uint32_t step_type,
+ uint32_t mac_mode, uint32_t src_addr,
+ uint32_t key_uid, uint32_t op_key_size)
+{
+ int status;
+ uint32_t i = 0;
+ uintptr_t inputdata;
+ uint32_t payload[FCS_HKDF_REQUEST_DATA_SIZE] = {0U};
+
+ if (!is_address_in_ddr_range(src_addr, FCS_HKDF_REQUEST_DATA_SIZE)) {
+ ERROR("MBOX: %s: source addr not in the DDR range\n", __func__);
+ return INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+
+ /* Prepare command payload */
+
+ /* Session ID */
+ payload[i] = session_id;
+ i++;
+
+ /* Reserved, 8 bytes */
+ payload[i] = 0;
+ i++;
+
+ payload[i] = 0;
+ i++;
+
+ /* HKDF step type */
+ payload[i] = step_type;
+ i++;
+
+ /* MAC mode/PRF */
+ payload[i] = mac_mode;
+ i++;
+
+ /* Complete input data, 1st input data len + its data + 2nd input data len + its data. */
+ inputdata = src_addr;
+ memcpy_s((uint8_t *)&payload[i], FCS_HKDF_KEY_DATA_SIZE / sizeof(uint32_t),
+ (uint8_t *)inputdata, FCS_HKDF_KEY_DATA_SIZE / sizeof(uint32_t));
+
+ i += FCS_HKDF_KEY_DATA_SIZE / sizeof(uint32_t);
+
+ /* Key UID */
+ payload[i] = key_uid;
+ i++;
+
+ /* Pointer to size of output key object */
+ inputdata = inputdata + FCS_HKDF_KEY_DATA_SIZE;
+
+ /* Output Key object */
+ memcpy_s(&payload[i], op_key_size / sizeof(uint32_t), (void *)inputdata,
+ op_key_size / sizeof(uint32_t));
+
+ i += op_key_size / sizeof(uint32_t);
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(trans_id),
+ GET_JOB_ID(trans_id),
+ MBOX_FCS_HKDF_REQUEST,
+ payload,
+ i,
+ MBOX_CMD_FLAG_CASUAL,
+ fcs_hkdf_request_cb,
+ NULL,
+ 0U);
+
+ if (status < 0) {
+ ERROR("MBOX: %s: status %d\n", __func__, status);
+ return INTEL_SIP_SMC_STATUS_ERROR;
+ }
+
+ return INTEL_SIP_SMC_STATUS_OK;
+}
diff --git a/plat/intel/soc/common/soc/socfpga_mailbox.c b/plat/intel/soc/common/soc/socfpga_mailbox.c
index 69f0008..3b3b479 100644
--- a/plat/intel/soc/common/soc/socfpga_mailbox.c
+++ b/plat/intel/soc/common/soc/socfpga_mailbox.c
@@ -1,11 +1,12 @@
/*
* Copyright (c) 2020-2023, Intel Corporation. All rights reserved.
- * Copyright (c) 2024, Altera Corporation. All rights reserved.
+ * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <lib/mmio.h>
+#include <lib/spinlock.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <platform_def.h>
@@ -15,6 +16,34 @@
#include "socfpga_sip_svc.h"
#include "socfpga_system_manager.h"
+#if SIP_SVC_V3
+/* Function prototypes */
+void mailbox_init_v3(void);
+static int mailbox_response_handler_fsm(void);
+static inline void mailbox_free_cmd_desc(sdm_command_t *cmd_desc);
+static sdm_response_t *mailbox_get_resp_desc(uint8_t client_id, uint8_t job_id,
+ uint8_t *index);
+static sdm_command_t *mailbox_get_cmd_desc(uint8_t client_id, uint8_t job_id);
+static inline void mailbox_free_resp_desc(uint8_t index);
+static sdm_command_t *mailbox_get_free_cmd_desc(void);
+static sdm_response_t *mailbox_get_resp_desc_cid(uint8_t client_id,
+ uint8_t *index);
+static int mailbox_read_response_v3(uint8_t client_id, uint8_t *job_id,
+ uint32_t *header, uint32_t *resp,
+ uint32_t *resp_len,
+ uint8_t ignore_client_id);
+static int mailbox_poll_response_v3(uint8_t client_id, uint8_t job_id,
+ uint32_t *resp, unsigned int *resp_len,
+ uint32_t urgent);
+
+static spinlock_t mbox_db_lock; /* Mailbox service data base lock */
+static spinlock_t mbox_write_lock; /* Hardware mailbox FIFO write lock */
+static spinlock_t mbox_read_lock; /* Hardware mailbox FIFO read lock */
+
+static mailbox_service_t mbox_svc; /* Mailbox service data base */
+static uint8_t async_v1_job_id;
+#endif /* #if SIP_SVC_V3 */
+
static mailbox_payload_t mailbox_resp_payload;
static mailbox_container_t mailbox_resp_ctr = {0, 0, &mailbox_resp_payload};
@@ -34,13 +63,13 @@
static int wait_for_mailbox_cmdbuf_empty(uint32_t cin)
{
- unsigned int timeout = 200U;
+ unsigned int timeout = 20000U;
do {
if (is_mailbox_cmdbuf_empty(cin)) {
break;
}
- mdelay(10U);
+ udelay(50U);
} while (--timeout != 0U);
if (timeout == 0U) {
@@ -54,7 +83,9 @@
uint32_t data,
bool *is_doorbell_triggered)
{
- unsigned int timeout = 100U;
+ unsigned int timeout = 20000U;
+
+ VERBOSE("MBOX: 0x%x\n", data);
do {
if (is_mailbox_cmdbuf_full(*cin)) {
@@ -63,7 +94,7 @@
MBOX_DOORBELL_TO_SDM, 1U);
*is_doorbell_triggered = true;
}
- mdelay(10U);
+ udelay(50U);
} else {
mmio_write_32(MBOX_ENTRY_TO_ADDR(CMD, (*cin)++), data);
*cin %= MBOX_CMD_BUFFER_SIZE;
@@ -84,6 +115,11 @@
return MBOX_RET_OK;
}
+/*
+ * Function description: Write the command header, and its payload one by one
+ * into the mailbox command buffer. Along with this, check for mailbox buffer
+ * full condition and trigger doorbell to SDM if the command buffer is full.
+ */
static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args,
unsigned int len)
{
@@ -92,15 +128,21 @@
int ret;
bool is_doorbell_triggered = false;
+#if SIP_SVC_V3
+ spin_lock(&mbox_write_lock);
+#endif
+
cmd_free_offset = mmio_read_32(MBOX_OFFSET + MBOX_CIN);
sdm_read_offset = mmio_read_32(MBOX_OFFSET + MBOX_COUT);
+ /* Write the command header here */
ret = write_mailbox_cmd_buffer(&cmd_free_offset, sdm_read_offset,
header_cmd, &is_doorbell_triggered);
if (ret != 0) {
goto restart_mailbox;
}
+ /* Write the payload here w.r.to args and its len - one by one. */
for (i = 0U; i < len; i++) {
is_doorbell_triggered = false;
ret = write_mailbox_cmd_buffer(&cmd_free_offset,
@@ -113,6 +155,9 @@
mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1U);
+#if SIP_SVC_V3
+ spin_unlock(&mbox_write_lock);
+#endif
return MBOX_RET_OK;
restart_mailbox:
@@ -129,12 +174,21 @@
}
}
+#if SIP_SVC_V3
+ spin_unlock(&mbox_write_lock);
+#endif
return MBOX_TIMEOUT;
}
int mailbox_read_response(unsigned int *job_id, uint32_t *response,
unsigned int *resp_len)
{
+#if SIP_SVC_V3
+ return mailbox_read_response_v3(MBOX_ATF_CLIENT_ID,
+ (uint8_t *)job_id, NULL,
+ response, resp_len,
+ 0);
+#else
uint32_t rin;
uint32_t rout;
uint32_t resp_data;
@@ -174,13 +228,23 @@
return MBOX_RET_OK;
}
+
return MBOX_NO_RESPONSE;
+#endif
}
int mailbox_read_response_async(unsigned int *job_id, uint32_t *header,
uint32_t *response, unsigned int *resp_len,
uint8_t ignore_client_id)
{
+#if SIP_SVC_V3
+ /* Just to avoid the build warning */
+ (void)mailbox_resp_ctr;
+ return mailbox_read_response_v3(MBOX_ATF_CLIENT_ID,
+ (uint8_t *)job_id, header,
+ response, resp_len,
+ ignore_client_id);
+#else
uint32_t rin;
uint32_t rout;
uint32_t resp_data;
@@ -220,7 +284,6 @@
return MBOX_WRONG_ID;
}
}
-
*job_id = MBOX_RESP_JOB_ID(resp_data);
ret_resp_len = MBOX_RESP_LEN(resp_data);
mailbox_resp_ctr.payload->header = resp_data;
@@ -272,11 +335,16 @@
*resp_len = 0;
return (mailbox_resp_ctr.flag & MBOX_PAYLOAD_FLAG_BUSY) ? MBOX_BUSY : MBOX_NO_RESPONSE;
+#endif
}
int mailbox_poll_response(uint32_t job_id, uint32_t urgent, uint32_t *response,
- unsigned int *resp_len)
+ unsigned int *resp_len)
{
+#if SIP_SVC_V3
+ return mailbox_poll_response_v3(MBOX_ATF_CLIENT_ID, (uint8_t)job_id,
+ response, resp_len, urgent);
+#else
unsigned int timeout = 40U;
unsigned int sdm_loop = 255U;
unsigned int ret_resp_len;
@@ -285,7 +353,6 @@
uint32_t resp_data;
while (sdm_loop != 0U) {
-
do {
if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM)
== 1U) {
@@ -310,7 +377,7 @@
}
mmio_write_32(MBOX_OFFSET + MBOX_URG, 0U);
- INFO("Error: Mailbox did not get UA");
+ ERROR("MBOX: Mailbox did not get UA");
return MBOX_RET_ERROR;
}
@@ -324,13 +391,21 @@
rout %= MBOX_RESP_BUFFER_SIZE;
mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
- if (MBOX_RESP_CLIENT_ID(resp_data) != MBOX_ATF_CLIENT_ID
- || MBOX_RESP_JOB_ID(resp_data) != job_id) {
+ if ((MBOX_RESP_CLIENT_ID(resp_data) != MBOX_ATF_CLIENT_ID) ||
+ (MBOX_RESP_JOB_ID(resp_data) != job_id)) {
continue;
}
+ /* Get the return response len from the response header. */
ret_resp_len = MBOX_RESP_LEN(resp_data);
+ /* Print the response header. */
+ VERBOSE("MBOX: RespHdr: cid %d, jid %d, len %d, err_code 0x%x\n",
+ MBOX_RESP_CLIENT_ID(resp_data),
+ MBOX_RESP_JOB_ID(resp_data),
+ MBOX_RESP_LEN(resp_data),
+ MBOX_RESP_ERR(resp_data));
+
if (iterate_resp(ret_resp_len, response, resp_len)
!= MBOX_RET_OK) {
return MBOX_TIMEOUT;
@@ -349,6 +424,7 @@
INFO("Timed out waiting for SDM\n");
return MBOX_TIMEOUT;
+#endif
}
int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf,
@@ -366,8 +442,7 @@
if ((resp_buf != NULL) && (resp_len != NULL)
&& (*resp_len != 0U)) {
- *(resp_buf + total_resp_len)
- = resp_data;
+ *(resp_buf + total_resp_len) = resp_data;
*resp_len = *resp_len - 1;
total_resp_len++;
}
@@ -417,6 +492,9 @@
return status;
}
+#if SIP_SVC_V3
+ async_v1_job_id = (uint8_t)*job_id;
+#endif
*job_id = (*job_id + 1U) % MBOX_MAX_IND_JOB_ID;
return MBOX_RET_OK;
@@ -433,9 +511,7 @@
MBOX_STATUS_UA_MASK;
mmio_write_32(MBOX_OFFSET + MBOX_URG, cmd);
mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1U);
- }
-
- else {
+ } else {
status = fill_mailbox_circular_buffer(
MBOX_CLIENT_ID_CMD(MBOX_ATF_CLIENT_ID) |
MBOX_JOB_ID_CMD(job_id) |
@@ -460,12 +536,12 @@
void mailbox_set_int(uint32_t interrupt)
{
-
- mmio_write_32(MBOX_OFFSET+MBOX_INT, MBOX_COE_BIT(interrupt) |
+ mmio_write_32(MBOX_OFFSET+MBOX_INT,
+ MBOX_COE_BIT(interrupt) |
+ MBOX_RIE_BIT(interrupt) |
MBOX_UAE_BIT(interrupt));
}
-
void mailbox_set_qspi_open(void)
{
mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE);
@@ -606,6 +682,7 @@
mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE |
MBOX_INT_FLAG_UAE);
+
mmio_write_32(MBOX_OFFSET + MBOX_URG, 0U);
mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U);
@@ -616,8 +693,16 @@
return status;
}
+#if SIP_SVC_V3
+ /* Initialize the mailbox version3 implementation, and in V3 we
+ * are interested in only RIE interrupt
+ */
+ mailbox_init_v3();
+ mailbox_set_int(MBOX_INT_FLAG_RIE);
+#else
mailbox_set_int(MBOX_INT_FLAG_COE | MBOX_INT_FLAG_RIE |
MBOX_INT_FLAG_UAE);
+#endif
return MBOX_RET_OK;
}
@@ -730,3 +815,693 @@
return mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_SAFE_INJECT_SEU_ERR, arg, len,
CMD_CASUAL, NULL, NULL);
}
+
+#if SIP_SVC_V3
+static int mailbox_fill_cmd_desc(uint8_t client_id, uint8_t job_id,
+ uint32_t *resp_buff)
+{
+ sdm_command_t *cmd_desc = NULL;
+
+ /* Get a free command descriptor */
+ cmd_desc = mailbox_get_free_cmd_desc();
+ if (cmd_desc == NULL) {
+ return MBOX_BUFFER_FULL;
+ }
+
+ /* Record all the given values for the command. */
+ cmd_desc->client_id = client_id;
+ cmd_desc->job_id = job_id;
+ cmd_desc->cb = NULL;
+ cmd_desc->cb_args = resp_buff;
+ cmd_desc->cb_args_len = 0U;
+
+ return MBOX_RET_OK;
+}
+
+/* Returns the command descriptor based on the client and job ID. */
+static sdm_command_t *mailbox_get_cmd_desc(uint8_t client_id, uint8_t job_id)
+{
+ spin_lock(&mbox_db_lock);
+ for (uint32_t count = 0; count < MBOX_SVC_CMD_QUEUE_SIZE; count++) {
+ if ((mbox_svc.cmd_queue[count].client_id == client_id) &&
+ (mbox_svc.cmd_queue[count].job_id == job_id) &&
+ (mbox_svc.cmd_queue[count].flags & MBOX_SVC_CMD_IS_USED)) {
+ spin_unlock(&mbox_db_lock);
+ return &(mbox_svc.cmd_queue[count]);
+ }
+ }
+
+ spin_unlock(&mbox_db_lock);
+ VERBOSE("MBOX: Command descriptor not found for cid %d, jid %d\n",
+ client_id, job_id);
+
+ return NULL;
+}
+
+/* Returns the response descriptor based on only client ID. */
+static sdm_response_t *mailbox_get_resp_desc_cid(uint8_t client_id, uint8_t *index)
+{
+ spin_lock(&mbox_db_lock);
+
+ for (uint32_t count = 0; count < MBOX_SVC_RESP_QUEUE_SIZE; count++) {
+ if ((mbox_svc.resp_queue[count].client_id == client_id) &&
+ (mbox_svc.resp_queue[count].flags & FLAG_SDM_RESPONSE_IS_VALID)) {
+ *index = count;
+ /*
+ * Once we get the valid response descriptor, get the
+ * job ID and mark up the bitmaps.
+ */
+ uint8_t job_id = mbox_svc.resp_queue[count].job_id;
+ uint8_t transaction_id = MBOX_GET_TRANS_ID(client_id, job_id);
+
+ mbox_svc.received_bitmap[transaction_id / MBOX_TID_BITMAP_SIZE] &=
+ ~(1ULL << (transaction_id % MBOX_TID_BITMAP_SIZE));
+ mbox_svc.interrupt_bitmap[transaction_id / MBOX_TID_BITMAP_SIZE] &=
+ ~(1ULL << (transaction_id % MBOX_TID_BITMAP_SIZE));
+ spin_unlock(&mbox_db_lock);
+ return &(mbox_svc.resp_queue[count]);
+ }
+ }
+
+ spin_unlock(&mbox_db_lock);
+ VERBOSE("MBOX: Response descriptor not found for cid %d\n", client_id);
+
+ return NULL;
+}
+
+/* Returns the response descriptor based on the client and job ID. */
+static sdm_response_t *mailbox_get_resp_desc(uint8_t client_id, uint8_t job_id, uint8_t *index)
+{
+ spin_lock(&mbox_db_lock);
+ /*
+ * Let's first check whether we have a response bitmap set for the given
+ * client ID and job ID.
+ */
+ uint8_t transaction_id = MBOX_GET_TRANS_ID(client_id, job_id);
+
+ if ((mbox_svc.received_bitmap[transaction_id / MBOX_TID_BITMAP_SIZE] &
+ (1ULL << (transaction_id % MBOX_TID_BITMAP_SIZE))) == 0) {
+ spin_unlock(&mbox_db_lock);
+ VERBOSE("MBOX: Response bitmap not set for cid %d, jid %d, bitmap 0x%16lx\n",
+ client_id, job_id, mbox_svc.received_bitmap[transaction_id / 64]);
+ return NULL;
+ }
+
+ for (uint32_t count = 0; count < MBOX_SVC_RESP_QUEUE_SIZE; count++) {
+ if (mbox_svc.resp_queue[count].flags & FLAG_SDM_RESPONSE_IS_VALID) {
+ if ((mbox_svc.resp_queue[count].client_id == client_id) &&
+ (mbox_svc.resp_queue[count].job_id == job_id)) {
+ *index = count;
+ mbox_svc.received_bitmap[transaction_id / MBOX_TID_BITMAP_SIZE] &=
+ ~(1ULL << (transaction_id % MBOX_TID_BITMAP_SIZE));
+ mbox_svc.interrupt_bitmap[transaction_id / MBOX_TID_BITMAP_SIZE] &=
+ ~(1ULL << (transaction_id % MBOX_TID_BITMAP_SIZE));
+ spin_unlock(&mbox_db_lock);
+ return &(mbox_svc.resp_queue[count]);
+ }
+ }
+ }
+
+ spin_unlock(&mbox_db_lock);
+ VERBOSE("MBOX: Response descriptor not found for cid %d, jid %d\n",
+ client_id, job_id);
+
+ return NULL;
+}
+
+static int32_t mailbox_get_free_resp_desc(void)
+{
+ spin_lock(&mbox_db_lock);
+ static uint32_t free_index = MBOX_SVC_RESP_QUEUE_SIZE - 1;
+ uint32_t count = 0U, try = 0U;
+
+ for (try = 0; try < MBOX_SVC_RESP_QUEUE_SIZE; try++) {
+ free_index = (free_index + 1) % MBOX_SVC_RESP_QUEUE_SIZE;
+ if ((mbox_svc.resp_queue[free_index].flags &
+ FLAG_SDM_RESPONSE_IS_USED) != 0U) {
+ count = free_index;
+ spin_unlock(&mbox_db_lock);
+ return count;
+ }
+ }
+
+ /* No free descriptors are available */
+ spin_unlock(&mbox_db_lock);
+ VERBOSE("MBOX: No free response descriptors are available\n");
+
+ return MBOX_BUFFER_FULL;
+}
+
+static sdm_command_t *mailbox_get_free_cmd_desc(void)
+{
+ spin_lock(&mbox_db_lock);
+ static uint32_t free_index;
+
+ /* Rollover the command queue free index */
+ if (free_index == (MBOX_SVC_CMD_QUEUE_SIZE - 1)) {
+ free_index = 0U;
+ }
+
+ for (; free_index < MBOX_SVC_CMD_QUEUE_SIZE; free_index++) {
+ if ((mbox_svc.cmd_queue[free_index].flags &
+ MBOX_SVC_CMD_IS_USED) != 0U) {
+ mbox_svc.cmd_queue[free_index].flags |= MBOX_SVC_CMD_IS_USED;
+ spin_unlock(&mbox_db_lock);
+ return &(mbox_svc.cmd_queue[free_index]);
+ }
+ }
+
+ /* No free command descriptors are available */
+ spin_unlock(&mbox_db_lock);
+ VERBOSE("MBOX: No free command descriptors available\n");
+
+ return NULL;
+}
+
+static inline void mailbox_free_cmd_desc(sdm_command_t *cmd_desc)
+{
+ if (cmd_desc == NULL) {
+ return;
+ }
+
+ spin_lock(&mbox_db_lock);
+ memset((void *)cmd_desc, 0, sizeof(sdm_command_t));
+ spin_unlock(&mbox_db_lock);
+}
+
+static inline void mailbox_free_resp_desc(uint8_t index)
+{
+ if (index >= MBOX_SVC_RESP_QUEUE_SIZE) {
+ return;
+ }
+
+ spin_lock(&mbox_db_lock);
+ memset((void *)&mbox_svc.resp_queue[index], 0, sizeof(sdm_response_t));
+ spin_unlock(&mbox_db_lock);
+}
+
+/*
+ * This function serves the V1 _sync_read and _async_read functionality, and it
+ * is introduced as part of V3 framework to keep backward compatible with V1
+ * clients.
+ */
+static int mailbox_read_response_v3(uint8_t client_id, uint8_t *job_id,
+ uint32_t *header, uint32_t *resp,
+ uint32_t *resp_len,
+ uint8_t ignore_client_id)
+{
+ uint8_t di = 0U;
+ int status = MBOX_RET_OK;
+ sdm_response_t *resp_desc = NULL;
+ sdm_command_t *cmd_desc = NULL;
+
+ /*
+ * In the V1, the client ID is always MBOX_ATF_CLIENT_ID and in this
+ * routine we will collect the response which only belongs to this
+ * client ID. So safe to ignore this input.
+ */
+ (void)ignore_client_id;
+
+ /* Clear the SDM doorbell interrupt */
+ if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) == 1U)
+ mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U);
+
+ /* Fill the command descriptor index and get the same */
+ status = mailbox_fill_cmd_desc(client_id, async_v1_job_id, resp);
+ if (status != MBOX_RET_OK) {
+ return status;
+ }
+
+ cmd_desc = mailbox_get_cmd_desc(client_id, async_v1_job_id);
+
+ /* Get the response from SDM, just go through one cycle */
+ status = mailbox_response_handler_fsm();
+ if (status != MBOX_RET_OK) {
+ mailbox_free_cmd_desc(cmd_desc);
+ *resp_len = 0U;
+ return status;
+ }
+
+ /* Check the local response queue with the given client ID */
+ resp_desc = mailbox_get_resp_desc_cid(client_id, &di);
+ if (resp_desc == NULL) {
+ mailbox_free_cmd_desc(cmd_desc);
+ *resp_len = 0U;
+ return MBOX_NO_RESPONSE;
+ }
+
+ /* Update the received mailbox response length, job ID and header */
+ *job_id = resp_desc->job_id;
+ *resp_len = resp_desc->rcvd_resp_len;
+ if (header != NULL) {
+ *header = resp_desc->header;
+ }
+
+ /* Check the mailbox response error code */
+ if (MBOX_RESP_ERR(resp_desc->header) > 0U) {
+ INFO("MBOX: Error in async response: %x\n", resp_desc->header);
+ status = -MBOX_RESP_ERR(resp_desc->header);
+ }
+
+ /* Free up the response and command descriptors */
+ mailbox_free_resp_desc(di);
+ mailbox_free_cmd_desc(cmd_desc);
+
+ return status;
+}
+
+int mailbox_send_cmd_async_v3(uint8_t client_id, uint8_t job_id, uint32_t cmd,
+ uint32_t *args, uint32_t args_len, uint8_t cmd_flag,
+ sdm_command_callback cb, uint32_t *cb_args,
+ uint32_t cb_args_len)
+{
+ int status = 0;
+ sdm_command_t *cmd_desc = NULL;
+
+ VERBOSE("MBOX: cid: %d, jid: %d, cmd: %d, cmd_flag: %d\n",
+ client_id, job_id, cmd, cmd_flag);
+
+ if (IS_CMD_SET(cmd_flag, URGENT)) {
+ mmio_write_32(MBOX_OFFSET + MBOX_URG, cmd);
+ mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1U);
+ } else {
+ /* Get a free command descriptor */
+ cmd_desc = mailbox_get_free_cmd_desc();
+ if (cmd_desc == NULL) {
+ return MBOX_BUFFER_FULL;
+ }
+
+ /* Record all the given values for the command. */
+ cmd_desc->client_id = client_id;
+ cmd_desc->job_id = job_id;
+ cmd_desc->cb = cb;
+ cmd_desc->cb_args = cb_args;
+ cmd_desc->cb_args_len = cb_args_len;
+
+ /* Push the command to mailbox FIFO */
+ status = fill_mailbox_circular_buffer(
+ MBOX_FRAME_CMD_HEADER(client_id, job_id,
+ args_len, IS_CMD_SET(cmd_flag, INDIRECT), cmd),
+ args,
+ args_len);
+
+ if (status != MBOX_RET_OK) {
+ INFO("MBOX: Failed to push the command to mailbox FIFO\n");
+ /* Free the command descriptor. */
+ mailbox_free_cmd_desc(cmd_desc);
+ }
+ }
+
+ INFO("MBOX: %s: status: %d\n", __func__, status);
+
+ return status;
+}
+
+static int mailbox_poll_response_v3(uint8_t client_id, uint8_t job_id,
+ uint32_t *resp, unsigned int *resp_len,
+ uint32_t urgent)
+{
+ unsigned int timeout = 40U;
+ unsigned int sdm_loop = 255U;
+ bool is_cmd_desc_fill = false;
+ uint8_t di = 0U;
+ sdm_response_t *resp_desc = NULL;
+ sdm_command_t *cmd_desc = NULL;
+
+ while (sdm_loop != 0U) {
+ do {
+ if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM)
+ == 1U) {
+ break;
+ }
+ mdelay(10U);
+ } while (--timeout != 0U);
+
+ if (timeout == 0U) {
+ INFO("%s: Timed out waiting for SDM intr\n", __func__);
+ break;
+ }
+
+ mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U);
+
+ if ((urgent & 1U) != 0U) {
+ mdelay(5U);
+ if ((mmio_read_32(MBOX_OFFSET + MBOX_STATUS) &
+ MBOX_STATUS_UA_MASK) ^
+ (urgent & MBOX_STATUS_UA_MASK)) {
+ mmio_write_32(MBOX_OFFSET + MBOX_URG, 0U);
+ return MBOX_RET_OK;
+ }
+
+ mmio_write_32(MBOX_OFFSET + MBOX_URG, 0U);
+ ERROR("MBOX: Mailbox did not get UA");
+ return MBOX_RET_ERROR;
+ }
+
+ /* Fill the command descriptor index and get the same. */
+ if (!is_cmd_desc_fill) {
+ if (mailbox_fill_cmd_desc(client_id, job_id, resp) !=
+ MBOX_RET_OK) {
+ return MBOX_BUFFER_FULL;
+ }
+
+ cmd_desc = mailbox_get_cmd_desc(client_id, job_id);
+ is_cmd_desc_fill = true;
+ }
+
+ /* Since it is sync call, will try to read till it time out */
+ (void)mailbox_response_handler_fsm();
+
+ /* Check the response queue with the given client ID and job ID */
+ resp_desc = mailbox_get_resp_desc(client_id, job_id, &di);
+ if (resp_desc != NULL) {
+ VERBOSE("%s: Resp received for cid %d, jid %d\n",
+ __func__, resp_desc->client_id, resp_desc->job_id);
+
+ uint16_t header = resp_desc->header;
+
+ /* Update the return response length */
+ if (resp_len != NULL) {
+ *resp_len = resp_desc->rcvd_resp_len;
+ }
+
+ /* Free the response and command descriptor */
+ mailbox_free_resp_desc(di);
+ mailbox_free_cmd_desc(cmd_desc);
+
+ if (MBOX_RESP_ERR(header) > 0U) {
+ INFO("%s: SDM err code: 0x%x\n", __func__,
+ MBOX_RESP_ERR(header));
+ return -MBOX_RESP_ERR(header);
+ }
+
+ VERBOSE("%s: MBOX_RET_OK\n", __func__);
+ return MBOX_RET_OK;
+ }
+ sdm_loop--;
+ }
+
+ INFO("%s: Timed out waiting for SDM\n", __func__);
+ return MBOX_TIMEOUT;
+}
+
+/* SDM response parser handler state machine. */
+static void mailbox_response_parser(void)
+{
+ int di = -1; /* Descriptor index */
+ uint32_t rin;
+ uint32_t rout;
+
+ switch (mbox_svc.next_resp_state) {
+ case SRS_WAIT_FOR_RESP:
+ {
+ mbox_svc.resp_state = SRS_WAIT_FOR_RESP;
+
+ rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN);
+ rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
+ if (rin != rout) {
+ mbox_svc.next_resp_state = SRS_WAIT_FOR_HEADER;
+ }
+
+ break;
+ }
+
+ case SRS_WAIT_FOR_HEADER:
+ {
+ mbox_svc.resp_state = SRS_WAIT_FOR_HEADER;
+ uint32_t resp_hdr;
+ uint8_t trans_id = 0U;
+
+ rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN);
+ rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
+ if (rin != rout) {
+ /* Read the header and dequeue from the queue. */
+ resp_hdr = mmio_read_32(MBOX_ENTRY_TO_ADDR(RESP, (rout)++));
+ rout %= MBOX_RESP_BUFFER_SIZE;
+ mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
+
+ /* Allocate a new response descriptor */
+ di = mailbox_get_free_resp_desc();
+ if (di != -1) {
+ mbox_svc.curr_di = di;
+ mbox_svc.resp_queue[di].header = resp_hdr;
+ mbox_svc.resp_queue[di].client_id = MBOX_RESP_CLIENT_ID(resp_hdr);
+ mbox_svc.resp_queue[di].job_id = MBOX_RESP_JOB_ID(resp_hdr);
+ mbox_svc.resp_queue[di].resp_len = MBOX_RESP_LEN(resp_hdr);
+ mbox_svc.resp_queue[di].flags |= (FLAG_SDM_RESPONSE_IS_USED |
+ FLAG_SDM_RESPONSE_IS_IN_PROGRESS);
+ mbox_svc.resp_queue[di].err_code = MBOX_RESP_ERR(resp_hdr);
+ trans_id = MBOX_RESP_TRANSACTION_ID(resp_hdr);
+
+ VERBOSE("MBOX: Resp Hdr: cid %d, jid %d, len %d, err_code 0x%x\n",
+ mbox_svc.resp_queue[di].client_id,
+ mbox_svc.resp_queue[di].job_id,
+ mbox_svc.resp_queue[di].resp_len,
+ mbox_svc.resp_queue[di].err_code);
+
+ /* Check if the response is an argument response */
+ if (mbox_svc.resp_queue[di].resp_len > 0) {
+ mbox_svc.next_resp_state = SRS_WAIT_FOR_ARGUMENTS;
+ } else {
+ VERBOSE("MBOX: Received complete response with no args\n");
+ /* Non argument response, done */
+ mbox_svc.resp_queue[mbox_svc.curr_di].flags |=
+ FLAG_SDM_RESPONSE_IS_VALID;
+
+ /* Go back to waiting for new response */
+ mbox_svc.next_resp_state = SRS_WAIT_FOR_RESP;
+ mbox_svc.curr_di = -1;
+
+ /* Mark the transaction ID as received */
+ spin_lock(&mbox_db_lock);
+ mbox_svc.received_bitmap[trans_id / MBOX_TID_BITMAP_SIZE] |=
+ (1ULL << (trans_id % MBOX_TID_BITMAP_SIZE));
+ spin_unlock(&mbox_db_lock);
+ }
+ } else {
+ mbox_svc.next_resp_state = SRS_SYNC_ERROR;
+ }
+ }
+ break;
+ }
+
+ case SRS_WAIT_FOR_ARGUMENTS:
+ {
+ mbox_svc.resp_state = SRS_WAIT_FOR_ARGUMENTS;
+ uint16_t mbox_resp_len = mbox_svc.resp_queue[mbox_svc.curr_di].resp_len;
+ uint32_t *read_buff = NULL;
+ uint16_t read_len = 0U;
+ uint16_t read_max_len = 0U;
+ uint32_t timeout = 0U;
+
+ /* Determine where to copy the buffer. */
+ sdm_command_t *cmd_desc = mailbox_get_cmd_desc(
+ mbox_svc.resp_queue[mbox_svc.curr_di].client_id,
+ mbox_svc.resp_queue[mbox_svc.curr_di].job_id);
+ if (cmd_desc != NULL && cmd_desc->cb_args != NULL) {
+ read_buff = cmd_desc->cb_args;
+ read_max_len = mbox_resp_len;
+ } else {
+ read_buff = (uint32_t *)mbox_svc.resp_queue[mbox_svc.curr_di].resp_data;
+ read_max_len = MBOX_SVC_MAX_RESP_DATA_SIZE;
+ }
+
+ rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN);
+ rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
+
+ while ((read_len < mbox_resp_len) && (rin != rout) && (read_len < read_max_len)) {
+ timeout = 10000U;
+
+ /* Copy the response data to the buffer */
+ read_buff[read_len++] = mmio_read_32(MBOX_ENTRY_TO_ADDR(RESP, (rout)++));
+
+ VERBOSE("MBOX: 0x%x\n", read_buff[read_len - 1]);
+
+ /* Update the read out buffer index */
+ rout %= MBOX_RESP_BUFFER_SIZE;
+ mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
+
+ /*
+ * The response buffer is of 16 words size, this loop checks
+ * if the response buffer is empty and if empty trigger an
+ * interrupt to SDM and wait for the response buffer to fill
+ */
+ do {
+ if (read_len == mbox_resp_len)
+ break;
+
+ rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN);
+ if (rout == rin) {
+ mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1U);
+ udelay(100);
+ } else {
+ break;
+ }
+ timeout--;
+ } while ((read_len < mbox_resp_len) && (timeout != 0U));
+
+ if (timeout == 0U) {
+ INFO("MBOX: Timeout waiting for response data\n");
+ mbox_svc.next_resp_state = SRS_SYNC_ERROR;
+ break;
+ }
+ }
+
+ /* Check if we have received all the arguments */
+ mbox_svc.resp_queue[mbox_svc.curr_di].rcvd_resp_len = read_len;
+ if (mbox_resp_len == read_len) {
+ uint8_t transaction_id =
+ ((mbox_svc.resp_queue[mbox_svc.curr_di].client_id << 4) |
+ (mbox_svc.resp_queue[mbox_svc.curr_di].job_id));
+ VERBOSE("MBOX: Received all the response data len %d, transaction_id %d\n",
+ read_len, transaction_id);
+
+ spin_lock(&mbox_db_lock);
+ mbox_svc.received_bitmap[transaction_id / MBOX_TID_BITMAP_SIZE] |=
+ (1ULL << (transaction_id % MBOX_TID_BITMAP_SIZE));
+ spin_unlock(&mbox_db_lock);
+
+ mbox_svc.resp_queue[mbox_svc.curr_di].flags |= FLAG_SDM_RESPONSE_IS_VALID;
+ mbox_svc.next_resp_state = SRS_WAIT_FOR_RESP;
+ mbox_svc.curr_di = -1;
+ } else {
+ mbox_svc.next_resp_state = SRS_SYNC_ERROR;
+ VERBOSE("MBOX: Received partial response data len %d, max len %d\n",
+ read_len, read_max_len);
+ }
+ break;
+ }
+
+ case SRS_SYNC_ERROR:
+ {
+ mbox_svc.resp_state = SRS_SYNC_ERROR;
+ INFO("MBOX: Error in response handling\n");
+ break;
+ }
+
+ default:
+ break;
+ } /* switch */
+}
+
+static int mailbox_response_handler_fsm(void)
+{
+ int status = MBOX_RET_OK;
+
+ spin_lock(&mbox_read_lock);
+ /* Mailbox peripheral response parser */
+ do {
+ /* Iterate till the state machine transition ends */
+ mailbox_response_parser();
+
+ /* Note down if there is any error in the response parsing */
+ if (mbox_svc.next_resp_state == SRS_SYNC_ERROR) {
+ status = MBOX_RET_ERROR;
+ }
+
+ } while (mbox_svc.resp_state != mbox_svc.next_resp_state);
+ spin_unlock(&mbox_read_lock);
+
+ return status;
+}
+
+int mailbox_response_poll_on_intr_v3(uint8_t *client_id, uint8_t *job_id,
+ uint64_t *bitmap)
+{
+ uint32_t i = 0U;
+ int status = MBOX_RET_OK;
+
+ /* Clear the SDM doorbell interrupt immediately */
+ if (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) == 1U) {
+ mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0U);
+ }
+
+ /* Check mailbox FIFO for any pending responses available to read. */
+ status = mailbox_response_handler_fsm();
+ if (status != MBOX_RET_OK) {
+ return status;
+ }
+
+ /*
+ * Once we read the complete mailbox FIFO, let's mark up the bitmap for
+ * available responses with respect to each transcation IDs.
+ */
+ status = MBOX_NO_RESPONSE;
+ spin_lock(&mbox_db_lock);
+ for (i = 0; i < MBOX_MAX_TIDS_BITMAP; i++) {
+ bitmap[i] = mbox_svc.interrupt_bitmap[i] ^ mbox_svc.received_bitmap[i];
+ if (bitmap[i] != 0 && status == MBOX_NO_RESPONSE) {
+ status = MBOX_RET_OK;
+ }
+
+ mbox_svc.interrupt_bitmap[i] = mbox_svc.received_bitmap[i];
+ }
+ spin_unlock(&mbox_db_lock);
+
+ return status;
+}
+
+int mailbox_response_poll_v3(uint8_t client_id, uint8_t job_id,
+ uint32_t *ret_args, uint32_t *ret_args_len)
+{
+ sdm_command_t *cmd_desc = NULL;
+ sdm_response_t *resp_desc = NULL;
+ uint8_t di = 0U;
+ int status = MBOX_RET_OK;
+
+ /*
+ * Let's first check the local response queue with the given
+ * client ID and job ID
+ */
+ resp_desc = mailbox_get_resp_desc(client_id, job_id, &di);
+ if (resp_desc == NULL) {
+ /* Not available in the local queue, let's read mailbox FIFO */
+ status = mailbox_response_handler_fsm();
+ if (status != MBOX_RET_OK) {
+ return status;
+ }
+
+ resp_desc = mailbox_get_resp_desc(client_id, job_id, &di);
+ }
+ cmd_desc = mailbox_get_cmd_desc(client_id, job_id);
+
+ if (cmd_desc != NULL && resp_desc != NULL) {
+ VERBOSE("MBOX: Resp found for cid %d, jid %d\n", client_id, job_id);
+
+ /* Command callback function */
+ *ret_args_len = cmd_desc->cb(resp_desc, cmd_desc, ret_args);
+
+ /* Free the command and response descriptors. */
+ mailbox_free_cmd_desc(cmd_desc);
+ mailbox_free_resp_desc(di);
+
+ return MBOX_RET_OK;
+ }
+
+ INFO("MBOX: No resp found for cid: %d, jid: %d\n", client_id, job_id);
+
+ return MBOX_NO_RESPONSE;
+}
+
+void mailbox_init_v3(void)
+{
+ uint32_t count;
+
+ memset((void *)&mbox_svc, 0, sizeof(mbox_svc));
+
+ mbox_svc.next_resp_state = SRS_WAIT_FOR_RESP;
+ mbox_svc.resp_state = SRS_WAIT_FOR_RESP;
+
+ /* Free all entries from the response queue. */
+ for (count = 0; count < MBOX_SVC_RESP_QUEUE_SIZE; count++) {
+ mbox_svc.resp_queue[count].flags = 0;
+ }
+
+ /* Free all entries from the command queue. */
+ for (count = 0; count < MBOX_SVC_CMD_QUEUE_SIZE; count++) {
+ mbox_svc.cmd_queue[count].flags = 0;
+ }
+
+ mbox_svc.curr_di = -1;
+}
+#endif /* #if SIP_SVC_V3 */
diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c
index f7b41fa..f4a3ea0 100644
--- a/plat/intel/soc/common/socfpga_sip_svc.c
+++ b/plat/intel/soc/common/socfpga_sip_svc.c
@@ -801,6 +801,837 @@
}
#endif
+#if SIP_SVC_V3
+uint8_t sip_smc_cmd_cb_ret2(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ /* Returns 3 SMC arguments for SMC_RET3 */
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+
+ return ret_args_len;
+}
+
+uint8_t sip_smc_cmd_cb_ret3(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ /* Returns 3 SMC arguments for SMC_RET3 */
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ ret_args[ret_args_len++] = resp->resp_data[0];
+
+ return ret_args_len;
+}
+
+uint8_t sip_smc_ret_nbytes_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ INFO("MBOX: %s: mailbox_err 0%x, nbytes_ret %d\n",
+ __func__, resp->err_code, resp->rcvd_resp_len * MBOX_WORD_BYTE);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ ret_args[ret_args_len++] = resp->rcvd_resp_len * MBOX_WORD_BYTE;
+
+ return ret_args_len;
+}
+
+uint8_t sip_smc_get_chipid_cb(void *resp_desc, void *cmd_desc, uint32_t *ret_args)
+{
+ uint8_t ret_args_len = 0U;
+ sdm_response_t *resp = (sdm_response_t *)resp_desc;
+ sdm_command_t *cmd = (sdm_command_t *)cmd_desc;
+
+ (void)cmd;
+ INFO("MBOX: %s: mailbox_err 0%x, data[0] 0x%x, data[1] 0x%x\n",
+ __func__, resp->err_code, resp->resp_data[0], resp->resp_data[1]);
+
+ ret_args[ret_args_len++] = INTEL_SIP_SMC_STATUS_OK;
+ ret_args[ret_args_len++] = resp->err_code;
+ ret_args[ret_args_len++] = resp->resp_data[0];
+ ret_args[ret_args_len++] = resp->resp_data[1];
+
+ return ret_args_len;
+}
+
+static uintptr_t smc_ret(void *handle, uint32_t *ret_args, uint32_t ret_args_len)
+{
+ switch (ret_args_len) {
+ case SMC_RET_ARGS_ONE:
+ SMC_RET1(handle, ret_args[0]);
+ break;
+
+ case SMC_RET_ARGS_TWO:
+ SMC_RET2(handle, ret_args[0], ret_args[1]);
+ break;
+
+ case SMC_RET_ARGS_THREE:
+ SMC_RET3(handle, ret_args[0], ret_args[1], ret_args[2]);
+ break;
+
+ case SMC_RET_ARGS_FOUR:
+ SMC_RET4(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3]);
+ break;
+
+ case SMC_RET_ARGS_FIVE:
+ SMC_RET5(handle, ret_args[0], ret_args[1], ret_args[2], ret_args[3], ret_args[4]);
+ break;
+
+ default:
+ SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR);
+ break;
+ }
+}
+
+/*
+ * This function is responsible for handling all SiP SVC V3 calls from the
+ * non-secure world.
+ */
+static uintptr_t sip_smc_handler_v3(uint32_t smc_fid,
+ u_register_t x1,
+ u_register_t x2,
+ u_register_t x3,
+ u_register_t x4,
+ void *cookie,
+ void *handle,
+ u_register_t flags)
+{
+ int status = 0;
+ uint32_t mbox_error = 0U;
+ u_register_t x5, x6, x7, x8, x9, x10, x11;
+
+ /* Get all the SMC call arguments */
+ x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
+ x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
+ x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
+ x8 = SMC_GET_GP(handle, CTX_GPREG_X8);
+ x9 = SMC_GET_GP(handle, CTX_GPREG_X9);
+ x10 = SMC_GET_GP(handle, CTX_GPREG_X10);
+ x11 = SMC_GET_GP(handle, CTX_GPREG_X11);
+
+ INFO("MBOX: SVC_V3: x0 0x%x, x1 0x%lx, x2 0x%lx, x3 0x%lx, x4 0x%lx, x5 0x%lx\n",
+ smc_fid, x1, x2, x3, x4, x5);
+ INFO("MBOX: SVC_V3: x6 0x%lx, x7 0x%lx, x8 0x%lx, x9 0x%lx, x10 0x%lx x11 0x%lx\n",
+ x6, x7, x8, x9, x10, x11);
+
+ switch (smc_fid) {
+ case ALTERA_SIP_SMC_ASYNC_RESP_POLL:
+ {
+ uint32_t ret_args[8] = {0};
+ uint32_t ret_args_len;
+
+ status = mailbox_response_poll_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ ret_args,
+ &ret_args_len);
+ /* Always reserve [0] index for command status. */
+ ret_args[0] = status;
+
+ /* Return SMC call based on the number of return arguments */
+ return smc_ret(handle, ret_args, ret_args_len);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_RESP_POLL_ON_INTR:
+ {
+ /* TBD: Here now we don't need these CID and JID?? */
+ uint8_t client_id = 0U;
+ uint8_t job_id = 0U;
+ uint64_t trans_id_bitmap[4] = {0U};
+
+ status = mailbox_response_poll_on_intr_v3(&client_id,
+ &job_id,
+ trans_id_bitmap);
+
+ SMC_RET5(handle, status, trans_id_bitmap[0], trans_id_bitmap[1],
+ trans_id_bitmap[2], trans_id_bitmap[3]);
+ break;
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_GET_DEVICE_IDENTITY:
+ {
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_CMD_GET_DEVICEID,
+ NULL,
+ 0U,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_ret_nbytes_cb,
+ (uint32_t *)x2,
+ 2);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_GET_IDCODE:
+ {
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_CMD_GET_IDCODE,
+ NULL,
+ 0U,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_ret3,
+ NULL,
+ 0);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_QSPI_OPEN:
+ {
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_CMD_QSPI_OPEN,
+ NULL,
+ 0U,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_ret2,
+ NULL,
+ 0U);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_QSPI_CLOSE:
+ {
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_CMD_QSPI_CLOSE,
+ NULL,
+ 0U,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_ret2,
+ NULL,
+ 0U);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_QSPI_SET_CS:
+ {
+ uint32_t cmd_data = 0U;
+ uint32_t chip_sel = (uint32_t)x2;
+ uint32_t comb_addr_mode = (uint32_t)x3;
+ uint32_t ext_dec_mode = (uint32_t)x4;
+
+ cmd_data = (chip_sel << MBOX_QSPI_SET_CS_OFFSET) |
+ (comb_addr_mode << MBOX_QSPI_SET_CS_CA_OFFSET) |
+ (ext_dec_mode << MBOX_QSPI_SET_CS_MODE_OFFSET);
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_CMD_QSPI_SET_CS,
+ &cmd_data,
+ 1U,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_ret2,
+ NULL,
+ 0U);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_QSPI_ERASE:
+ {
+ uint32_t qspi_addr = (uint32_t)x2;
+ uint32_t qspi_nwords = (uint32_t)x3;
+
+ /* QSPI address offset to start erase, must be 4K aligned */
+ if (MBOX_IS_4K_ALIGNED(qspi_addr)) {
+ ERROR("MBOX: 0x%x: QSPI address not 4K aligned\n",
+ smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+
+ /* Number of words to erase, multiples of 0x400 or 4K */
+ if (qspi_nwords % MBOX_QSPI_ERASE_SIZE_GRAN) {
+ ERROR("MBOX: 0x%x: Given words not in multiples of 4K\n",
+ smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+
+ uint32_t cmd_data[2] = {qspi_addr, qspi_nwords};
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_CMD_QSPI_ERASE,
+ cmd_data,
+ sizeof(cmd_data) / MBOX_WORD_BYTE,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_ret2,
+ NULL,
+ 0U);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_QSPI_WRITE:
+ {
+ uint32_t *qspi_payload = (uint32_t *)x2;
+ uint32_t qspi_total_nwords = (((uint32_t)x3) / MBOX_WORD_BYTE);
+ uint32_t qspi_addr = qspi_payload[0];
+ uint32_t qspi_nwords = qspi_payload[1];
+
+ if (!MBOX_IS_WORD_ALIGNED(qspi_addr)) {
+ ERROR("MBOX: 0x%x: Given address is not WORD aligned\n",
+ smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+
+ if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) {
+ ERROR("MBOX: 0x%x: Number of words exceeds max limit\n",
+ smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_CMD_QSPI_WRITE,
+ qspi_payload,
+ qspi_total_nwords,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_ret2,
+ NULL,
+ 0U);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_QSPI_READ:
+ {
+ uint32_t qspi_addr = (uint32_t)x2;
+ uint32_t qspi_nwords = (((uint32_t)x4) / MBOX_WORD_BYTE);
+
+ if (qspi_nwords > MBOX_QSPI_RW_MAX_WORDS) {
+ ERROR("MBOX: 0x%x: Number of words exceeds max limit\n",
+ smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+
+ uint32_t cmd_data[2] = {qspi_addr, qspi_nwords};
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_CMD_QSPI_READ,
+ cmd_data,
+ sizeof(cmd_data) / MBOX_WORD_BYTE,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_ret_nbytes_cb,
+ (uint32_t *)x3,
+ 2);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_QSPI_GET_DEV_INFO:
+ {
+ uint32_t *dst_addr = (uint32_t *)x2;
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_CMD_QSPI_GET_DEV_INFO,
+ NULL,
+ 0U,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_ret_nbytes_cb,
+ (uint32_t *)dst_addr,
+ 2);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT:
+ case ALTERA_SIP_SMC_ASYNC_HWMON_READTEMP:
+ {
+ uint32_t channel = (uint32_t)x2;
+ uint32_t mbox_cmd = ((smc_fid == ALTERA_SIP_SMC_ASYNC_HWMON_READVOLT) ?
+ MBOX_HWMON_READVOLT : MBOX_HWMON_READTEMP);
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ mbox_cmd,
+ &channel,
+ 1U,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_ret3,
+ NULL,
+ 0);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_RANDOM_NUMBER_EXT:
+ {
+ uint32_t session_id = (uint32_t)x2;
+ uint32_t context_id = (uint32_t)x3;
+ uint64_t ret_random_addr = (uint64_t)x4;
+ uint32_t random_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5);
+ uint32_t crypto_header = 0U;
+
+ if ((random_len > (FCS_RANDOM_EXT_MAX_WORD_SIZE * MBOX_WORD_BYTE)) ||
+ (random_len == 0U) ||
+ (!is_size_4_bytes_aligned(random_len))) {
+ ERROR("MBOX: 0x%x is rejected\n", smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+
+ crypto_header = ((FCS_CS_FIELD_FLAG_INIT | FCS_CS_FIELD_FLAG_FINALIZE) <<
+ FCS_CS_FIELD_FLAG_OFFSET);
+ fcs_rng_payload payload = {session_id, context_id,
+ crypto_header, random_len};
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_FCS_RANDOM_GEN,
+ (uint32_t *)&payload,
+ sizeof(payload) / MBOX_WORD_BYTE,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_ret_nbytes_cb,
+ (uint32_t *)ret_random_addr,
+ 2);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_PROVISION_DATA:
+ {
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_FCS_GET_PROVISION,
+ NULL,
+ 0U,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_ret_nbytes_cb,
+ (uint32_t *)x2,
+ 2);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_CNTR_SET_PREAUTH:
+ {
+ status = intel_fcs_cntr_set_preauth(smc_fid, x1, x2, x3,
+ x4, &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_CHIP_ID:
+ {
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_CMD_GET_CHIPID,
+ NULL,
+ 0U,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_get_chipid_cb,
+ NULL,
+ 0);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_ATTESTATION_CERT:
+ {
+ status = intel_fcs_get_attestation_cert(smc_fid, x1, x2, x3,
+ (uint32_t *) &x4, &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CERT_ON_RELOAD:
+ {
+ status = intel_fcs_create_cert_on_reload(smc_fid, x1,
+ x2, &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_CRYPTION_EXT:
+ {
+ if (x4 == FCS_MODE_ENCRYPT) {
+ status = intel_fcs_encryption_ext(smc_fid, x1, x2, x3,
+ x5, x6, x7, (uint32_t *) &x8,
+ &mbox_error, x10, x11);
+ } else if (x4 == FCS_MODE_DECRYPT) {
+ status = intel_fcs_decryption_ext(smc_fid, x1, x2, x3,
+ x5, x6, x7, (uint32_t *) &x8,
+ &mbox_error, x9, x10, x11);
+ } else {
+ ERROR("MBOX: 0x%x: Wrong crypto mode\n", smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ }
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_SEND_CERTIFICATE:
+ {
+ status = intel_fcs_send_cert(smc_fid, x1, x2, x3, &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_OPEN_CS_SESSION:
+ {
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_FCS_OPEN_CS_SESSION,
+ NULL,
+ 0U,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_ret3,
+ NULL,
+ 0);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_CLOSE_CS_SESSION:
+ {
+ uint32_t session_id = (uint32_t)x2;
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_FCS_CLOSE_CS_SESSION,
+ &session_id,
+ 1U,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_ret2,
+ NULL,
+ 0);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_IMPORT_CS_KEY:
+ {
+ uint64_t key_addr = x2;
+ uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE;
+
+ if ((key_len_words > FCS_CS_KEY_OBJ_MAX_WORD_SIZE) ||
+ (!is_address_in_ddr_range(key_addr, key_len_words * 4))) {
+ ERROR("MBOX: 0x%x: Addr not in DDR range or key len exceeds\n",
+ smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_FCS_IMPORT_CS_KEY,
+ (uint32_t *)key_addr,
+ key_len_words,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_ret3,
+ NULL,
+ 0);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_CREATE_CS_KEY:
+ {
+ uint64_t key_addr = x2;
+ uint32_t key_len_words = (uint32_t)x3 / MBOX_WORD_BYTE;
+
+ if (!is_address_in_ddr_range(key_addr, key_len_words * 4)) {
+ ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_FCS_CREATE_CS_KEY,
+ (uint32_t *)key_addr,
+ key_len_words,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_ret3,
+ NULL,
+ 0);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_EXPORT_CS_KEY:
+ {
+ uint32_t session_id = (uint32_t)x2;
+ uint32_t key_uid = (uint32_t)x3;
+ uint64_t ret_key_addr = (uint64_t)x4;
+ uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5);
+
+ if (!is_address_in_ddr_range(ret_key_addr, key_len)) {
+ ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+
+ fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO,
+ RESERVED_AS_ZERO, key_uid};
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_FCS_EXPORT_CS_KEY,
+ (uint32_t *)&payload,
+ sizeof(payload) / MBOX_WORD_BYTE,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_ret_nbytes_cb,
+ (uint32_t *)ret_key_addr,
+ 2);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_REMOVE_CS_KEY:
+ {
+ uint32_t session_id = (uint32_t)x2;
+ uint32_t key_uid = (uint32_t)x3;
+
+ fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO,
+ RESERVED_AS_ZERO, key_uid};
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_FCS_REMOVE_CS_KEY,
+ (uint32_t *)&payload,
+ sizeof(payload) / MBOX_WORD_BYTE,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_cmd_cb_ret3,
+ NULL,
+ 0);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_CS_KEY_INFO:
+ {
+ uint32_t session_id = (uint32_t)x2;
+ uint32_t key_uid = (uint32_t)x3;
+ uint64_t ret_key_addr = (uint64_t)x4;
+ uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5);
+
+ if (!is_address_in_ddr_range(ret_key_addr, key_len)) {
+ ERROR("MBOX: 0x%x: Addr not in DDR range\n", smc_fid);
+ status = INTEL_SIP_SMC_STATUS_REJECTED;
+ SMC_RET1(handle, status);
+ }
+
+ fcs_cs_key_payload payload = {session_id, RESERVED_AS_ZERO,
+ RESERVED_AS_ZERO, key_uid};
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_FCS_GET_CS_KEY_INFO,
+ (uint32_t *)&payload,
+ sizeof(payload) / MBOX_WORD_BYTE,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_ret_nbytes_cb,
+ (uint32_t *)ret_key_addr,
+ 2);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_INIT:
+ {
+ status = intel_fcs_aes_crypt_init(x2, x3, x4, x5,
+ x6, &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE:
+ {
+ uint32_t job_id = 0U;
+ bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_AES_CRYPT_FINALIZE) ?
+ true : false;
+
+ status = intel_fcs_aes_crypt_update_finalize(smc_fid, x1, x2,
+ x3, x4, x5, x6, x7, x8, is_final,
+ &job_id, x9, x10);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_INIT:
+ {
+ status = intel_fcs_get_digest_init(x2, x3, x4, x5, x6,
+ &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE:
+ {
+ bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_GET_DIGEST_FINALIZE) ?
+ true : false;
+
+ status = intel_fcs_get_digest_update_finalize(smc_fid, x1, x2,
+ x3, x4, x5, x6, (uint32_t *) &x7,
+ is_final, &mbox_error, x8);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_INIT:
+ {
+ status = intel_fcs_mac_verify_init(x2, x3, x4, x5, x6,
+ &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE:
+ {
+ bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_MAC_VERIFY_FINALIZE) ?
+ true : false;
+
+ status = intel_fcs_mac_verify_update_finalize(smc_fid, x1, x2,
+ x3, x4, x5, x6, (uint32_t *) &x7, x8,
+ is_final, &mbox_error, x9);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_INIT:
+ {
+ status = intel_fcs_ecdsa_hash_sign_init(x2, x3, x4, x5, x6,
+ &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIGN_FINALIZE:
+ {
+ status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, x1, x2, x3,
+ x4, x5, x6, (uint32_t *) &x7,
+ &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_INIT:
+ {
+ status = intel_fcs_ecdsa_sha2_data_sign_init(x2, x3, x4, x5, x6,
+ &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
+ {
+ bool is_final = (smc_fid == ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE)
+ ? true : false;
+
+ status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid,
+ x1, x2, x3, x4, x5, x6, (uint32_t *) &x7,
+ is_final, &mbox_error, x8);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
+ {
+ status = intel_fcs_ecdsa_hash_sig_verify_init(x2, x3, x4, x5,
+ x6, &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
+ {
+ status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, x1,
+ x2, x3, x4, x5, x6, (uint32_t *) &x7,
+ &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
+ {
+ status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x2, x3, x4,
+ x5, x6, &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE:
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE:
+ {
+ bool is_final = (smc_fid ==
+ ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE) ?
+ true : false;
+
+ status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
+ smc_fid, x1, x2, x3, x4, x5, x6,
+ (uint32_t *) &x7, x8, is_final,
+ &mbox_error, x9);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_INIT:
+ {
+ status = intel_fcs_ecdsa_get_pubkey_init(x2, x3, x4, x5, x6,
+ &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
+ {
+ status = intel_fcs_ecdsa_get_pubkey_finalize(smc_fid, x1, x2, x3,
+ x4, (uint32_t *) &x5, &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_INIT:
+ {
+ status = intel_fcs_ecdh_request_init(x2, x3, x4, x5, x6,
+ &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_ECDH_REQUEST_FINALIZE:
+ {
+ uint32_t dest_size = (uint32_t)x7;
+
+ NOTICE("MBOX: %s, %d: x7 0x%x, dest_size 0x%x\n",
+ __func__, __LINE__, (uint32_t)x7, dest_size);
+
+ status = intel_fcs_ecdh_request_finalize(smc_fid, x1, x2, x3,
+ x4, x5, x6, (uint32_t *) &dest_size,
+ &mbox_error);
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_MCTP_MSG:
+ {
+ uint32_t *src_addr = (uint32_t *)x2;
+ uint32_t src_size = (uint32_t)x3;
+ uint32_t *dst_addr = (uint32_t *)x4;
+
+ status = mailbox_send_cmd_async_v3(GET_CLIENT_ID(x1),
+ GET_JOB_ID(x1),
+ MBOX_CMD_MCTP_MSG,
+ src_addr,
+ src_size / MBOX_WORD_BYTE,
+ MBOX_CMD_FLAG_CASUAL,
+ sip_smc_ret_nbytes_cb,
+ dst_addr,
+ 2);
+
+ SMC_RET1(handle, status);
+ }
+
+ case ALTERA_SIP_SMC_ASYNC_FCS_HKDF_REQUEST:
+ {
+ status = intel_fcs_hkdf_request(smc_fid, x1, x2, x3, x4, x5, x6,
+ x7);
+ SMC_RET1(handle, status);
+ }
+
+ default:
+ return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
+ cookie, handle, flags);
+ } /* switch (smc_fid) */
+}
+#endif
+
/*
* This function is responsible for handling all SiP calls from the NS world
*/
@@ -995,11 +1826,11 @@
x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
if (x3 == FCS_MODE_DECRYPT) {
- status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6,
- (uint32_t *) &x7, &mbox_error);
+ status = intel_fcs_decryption_ext(smc_fid, 0, x1, x2, x4, x5, x6,
+ (uint32_t *) &x7, &mbox_error, 0, 0, 0);
} else if (x3 == FCS_MODE_ENCRYPT) {
- status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6,
- (uint32_t *) &x7, &mbox_error);
+ status = intel_fcs_encryption_ext(smc_fid, 0, x1, x2, x4, x5, x6,
+ (uint32_t *) &x7, &mbox_error, 0, 0);
} else {
status = INTEL_SIP_SMC_STATUS_REJECTED;
}
@@ -1017,7 +1848,7 @@
SMC_RET1(handle, status);
case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE:
- status = intel_fcs_send_cert(x1, x2, &send_id);
+ status = intel_fcs_send_cert(smc_fid, 0, x1, x2, &send_id);
SMC_RET1(handle, status);
case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA:
@@ -1025,7 +1856,7 @@
SMC_RET1(handle, status);
case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH:
- status = intel_fcs_cntr_set_preauth(x1, x2, x3,
+ status = intel_fcs_cntr_set_preauth(smc_fid, 0, x1, x2, x3,
&mbox_error);
SMC_RET2(handle, status, mbox_error);
@@ -1060,12 +1891,12 @@
SMC_RET4(handle, status, mbox_error, x3, x4);
case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT:
- status = intel_fcs_get_attestation_cert(x1, x2,
+ status = intel_fcs_get_attestation_cert(smc_fid, 0, x1, x2,
(uint32_t *) &x3, &mbox_error);
SMC_RET4(handle, status, mbox_error, x2, x3);
case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD:
- status = intel_fcs_create_cert_on_reload(x1, &mbox_error);
+ status = intel_fcs_create_cert_on_reload(smc_fid, 0, x1, &mbox_error);
SMC_RET2(handle, status, mbox_error);
case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION:
@@ -1104,17 +1935,17 @@
case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
- status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
- x4, x5, (uint32_t *) &x6, false,
- &mbox_error);
+ status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2,
+ x3, x4, x5, (uint32_t *) &x6, false,
+ &mbox_error, 0);
SMC_RET4(handle, status, mbox_error, x5, x6);
case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
- status = intel_fcs_get_digest_update_finalize(x1, x2, x3,
- x4, x5, (uint32_t *) &x6, true,
- &mbox_error);
+ status = intel_fcs_get_digest_update_finalize(smc_fid, 0, x1, x2,
+ x3, x4, x5, (uint32_t *) &x6, true,
+ &mbox_error, 0);
SMC_RET4(handle, status, mbox_error, x5, x6);
case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE:
@@ -1143,18 +1974,18 @@
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
- status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
- x4, x5, (uint32_t *) &x6, x7,
- false, &mbox_error);
+ status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2,
+ x3, x4, x5, (uint32_t *) &x6, x7, false,
+ &mbox_error, 0);
SMC_RET4(handle, status, mbox_error, x5, x6);
case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
- status = intel_fcs_mac_verify_update_finalize(x1, x2, x3,
- x4, x5, (uint32_t *) &x6, x7,
- true, &mbox_error);
+ status = intel_fcs_mac_verify_update_finalize(smc_fid, 0, x1, x2,
+ x3, x4, x5, (uint32_t *) &x6, x7, true,
+ &mbox_error, 0);
SMC_RET4(handle, status, mbox_error, x5, x6);
case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE:
@@ -1184,17 +2015,17 @@
case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
- status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
- x3, x4, x5, (uint32_t *) &x6, false,
- &mbox_error);
+ status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid,
+ 0, x1, x2, x3, x4, x5, (uint32_t *) &x6,
+ false, &mbox_error, 0);
SMC_RET4(handle, status, mbox_error, x5, x6);
case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
- status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2,
- x3, x4, x5, (uint32_t *) &x6, true,
- &mbox_error);
+ status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(smc_fid,
+ 0, x1, x2, x3, x4, x5, (uint32_t *) &x6,
+ true, &mbox_error, 0);
SMC_RET4(handle, status, mbox_error, x5, x6);
case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE:
@@ -1222,8 +2053,9 @@
case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
- status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3,
- x4, x5, (uint32_t *) &x6, &mbox_error);
+ status = intel_fcs_ecdsa_hash_sign_finalize(smc_fid, 0, x1, x2,
+ x3, x4, x5, (uint32_t *) &x6,
+ &mbox_error);
SMC_RET4(handle, status, mbox_error, x5, x6);
case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT:
@@ -1235,8 +2067,9 @@
case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
- status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3,
- x4, x5, (uint32_t *) &x6, &mbox_error);
+ status = intel_fcs_ecdsa_hash_sig_verify_finalize(smc_fid, 0, x1,
+ x2, x3, x4, x5, (uint32_t *) &x6,
+ &mbox_error);
SMC_RET4(handle, status, mbox_error, x5, x6);
case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT:
@@ -1250,8 +2083,9 @@
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
- x1, x2, x3, x4, x5, (uint32_t *) &x6,
- x7, false, &mbox_error);
+ smc_fid, 0, x1, x2, x3, x4, x5,
+ (uint32_t *) &x6, x7, false,
+ &mbox_error, 0);
SMC_RET4(handle, status, mbox_error, x5, x6);
case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE:
@@ -1277,8 +2111,9 @@
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
x7 = SMC_GET_GP(handle, CTX_GPREG_X7);
status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize(
- x1, x2, x3, x4, x5, (uint32_t *) &x6,
- x7, true, &mbox_error);
+ smc_fid, 0, x1, x2, x3, x4, x5,
+ (uint32_t *) &x6, x7, true,
+ &mbox_error, 0);
SMC_RET4(handle, status, mbox_error, x5, x6);
case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT:
@@ -1288,8 +2123,9 @@
SMC_RET2(handle, status, mbox_error);
case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE:
- status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3,
- (uint32_t *) &x4, &mbox_error);
+ status = intel_fcs_ecdsa_get_pubkey_finalize(
+ INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE, 0,
+ x1, x2, x3, (uint32_t *) &x4, &mbox_error);
SMC_RET4(handle, status, mbox_error, x3, x4);
case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT:
@@ -1301,7 +2137,7 @@
case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
- status = intel_fcs_ecdh_request_finalize(x1, x2, x3,
+ status = intel_fcs_ecdh_request_finalize(smc_fid, 0, x1, x2, x3,
x4, x5, (uint32_t *) &x6, &mbox_error);
SMC_RET4(handle, status, mbox_error, x5, x6);
@@ -1314,15 +2150,15 @@
case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
- status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
- x5, x6, false, &send_id);
+ status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2,
+ x3, x4, x5, x6, 0, false, &send_id, 0, 0);
SMC_RET1(handle, status);
case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
- status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4,
- x5, x6, true, &send_id);
+ status = intel_fcs_aes_crypt_update_finalize(smc_fid, 0, x1, x2,
+ x3, x4, x5, x6, 0, true, &send_id, 0, 0);
SMC_RET1(handle, status);
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
@@ -1379,7 +2215,16 @@
cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) {
return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4,
cookie, handle, flags);
- } else {
+ }
+#if SIP_SVC_V3
+ else if ((cmd >= INTEL_SIP_SMC_CMD_V3_RANGE_BEGIN) &&
+ (cmd <= INTEL_SIP_SMC_CMD_V3_RANGE_END)) {
+ uintptr_t ret = sip_smc_handler_v3(smc_fid, x1, x2, x3, x4,
+ cookie, handle, flags);
+ return ret;
+ }
+#endif
+ else {
return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4,
cookie, handle, flags);
}
diff --git a/plat/intel/soc/n5x/bl31_plat_setup.c b/plat/intel/soc/n5x/bl31_plat_setup.c
index cb5ced6..65de036 100644
--- a/plat/intel/soc/n5x/bl31_plat_setup.c
+++ b/plat/intel/soc/n5x/bl31_plat_setup.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2020-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -115,6 +116,16 @@
mmio_write_64(PLAT_CPU_RELEASE_ADDR,
(uint64_t)plat_secondary_cpus_bl31_entry);
+#if SIP_SVC_V3
+ /*
+ * Re-initialize the mailbox to include V3 specific routines.
+ * In V3, this re-initialize is required because prior to BL31, U-Boot
+ * SPL has its own mailbox settings and this initialization will
+ * override to those settings as required by the V3 framework.
+ */
+ mailbox_init();
+#endif
+
mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
}
diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c
index d0aa972..5c25e43 100644
--- a/plat/intel/soc/stratix10/bl31_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl31_plat_setup.c
@@ -1,6 +1,7 @@
/*
* Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
+ * Copyright (c) 2025, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -122,6 +123,16 @@
mmio_write_64(PLAT_CPU_RELEASE_ADDR,
(uint64_t)plat_secondary_cpus_bl31_entry);
+#if SIP_SVC_V3
+ /*
+ * Re-initialize the mailbox to include V3 specific routines.
+ * In V3, this re-initialize is required because prior to BL31, U-Boot
+ * SPL has its own mailbox settings and this initialization will
+ * override to those settings as required by the V3 framework.
+ */
+ mailbox_init();
+#endif
+
mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
}
diff --git a/plat/mediatek/mt8188/plat_config.mk b/plat/mediatek/mt8188/plat_config.mk
index 82ef7e8..3f7d187 100644
--- a/plat/mediatek/mt8188/plat_config.mk
+++ b/plat/mediatek/mt8188/plat_config.mk
@@ -27,7 +27,6 @@
ERRATA_A78_1941498 := 1
ERRATA_A78_1951500 := 1
ERRATA_A78_1821534 := 1
-ERRATA_A78_2132060 := 1
ERRATA_A78_2242635 := 1
ERRATA_A78_2376745 := 1
ERRATA_A78_2395406 := 1
diff --git a/plat/mediatek/mt8195/platform.mk b/plat/mediatek/mt8195/platform.mk
index 48dafa3..e604d4f 100644
--- a/plat/mediatek/mt8195/platform.mk
+++ b/plat/mediatek/mt8195/platform.mk
@@ -99,7 +99,6 @@
ERRATA_A78_1941498 := 1
ERRATA_A78_1951500 := 1
ERRATA_A78_1821534 := 1
-ERRATA_A78_2132060 := 1
ERRATA_A78_2242635 := 1
# indicate the reset vector address can be programmed
diff --git a/plat/qti/sc7280/platform.mk b/plat/qti/sc7280/platform.mk
index 3d7d728..0b5ae52 100644
--- a/plat/qti/sc7280/platform.mk
+++ b/plat/qti/sc7280/platform.mk
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2017-2018, Arm Limited and Contributors. All rights reserved.
+# Copyright (c) 2017-2025, Arm Limited and Contributors. All rights reserved.
# Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
@@ -20,7 +20,6 @@
ERRATA_A55_1530923 := 1
ERRATA_A78_1941498 := 1
ERRATA_A78_1951500 := 1
-ERRATA_A78_2132060 := 1
# Disable the PSCI platform compatibility layer
ENABLE_PLAT_COMPAT := 0
diff --git a/services/std_svc/spm/el3_spmc/spmc_main.c b/services/std_svc/spm/el3_spmc/spmc_main.c
index bddfe96..c67a6fc 100644
--- a/services/std_svc/spm/el3_spmc/spmc_main.c
+++ b/services/std_svc/spm/el3_spmc/spmc_main.c
@@ -1359,6 +1359,16 @@
/* Execution stops here. */
/* Supported ABIs only from the secure world. */
+ case FFA_MEM_PERM_GET_SMC32:
+ case FFA_MEM_PERM_GET_SMC64:
+ case FFA_MEM_PERM_SET_SMC32:
+ case FFA_MEM_PERM_SET_SMC64:
+ /* these ABIs are only supported from S-EL0 SPs */
+ #if !(SPMC_AT_EL3_SEL0_SP)
+ return spmc_ffa_error_return(handle, FFA_ERROR_NOT_SUPPORTED);
+ #endif
+ /* fall through */
+
case FFA_SECONDARY_EP_REGISTER_SMC64:
case FFA_MSG_SEND_DIRECT_RESP_SMC32:
case FFA_MSG_SEND_DIRECT_RESP_SMC64:
@@ -1367,7 +1377,6 @@
case FFA_MSG_WAIT:
case FFA_CONSOLE_LOG_SMC32:
case FFA_CONSOLE_LOG_SMC64:
-
if (!secure_origin) {
return spmc_ffa_error_return(handle,
FFA_ERROR_NOT_SUPPORTED);
diff --git a/tools/nxp/create_pbl/Makefile b/tools/nxp/create_pbl/Makefile
index cd2ccc1..9285b72 100644
--- a/tools/nxp/create_pbl/Makefile
+++ b/tools/nxp/create_pbl/Makefile
@@ -44,7 +44,7 @@
$(s)echo "Built $@ successfully"
$(s)echo
-+${OBJECTS_1} ${OBJECTS_2}: %.o: %.c Makefile
+${OBJECTS_1} ${OBJECTS_2}: %.o: %.c Makefile
$(s)echo " CC $<"
$(q)$(host-cc) -c ${CPPFLAGS} ${CFLAGS} ${INCLUDE_PATHS} $< -o $@