tree 6d5845092453e24370cc9a776d20ecd6ad65e325
parent 17b8a8a33680cbbfa1b84c871304eb1296f1883d
author Govindraj Raja <govindraj.raja@arm.com> 1737504171 -0600
committer Yann Gautier <yann.gautier@st.com> 1738687785 +0100

fix(cpus): workaround for Cortex-X2 erratum 3701772

Cortex-X2 erratum 3701772 that applies to r0p0, r1p0, r2p0, r2p1
is still Open.

The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775100/latest/

Change-Id: I2ffc5e7d7467f1bcff8b895fea52a1daa7d14495
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
(cherry picked from commit ae6c7c97d4e0f491854b34628e0fa1038668f8e4)