PSCI: Remove references to affinity based power management
As per Section 4.2.2. in the PSCI specification, the term "affinity"
is used in the context of describing the hierarchical arrangement
of cores. This often, but not always, maps directly to the processor
power domain topology of the system. The current PSCI implementation
assumes that this is always the case i.e. MPIDR based levels of
affinity always map to levels in a power domain topology tree.
This patch is the first in a series of patches which remove this
assumption. It removes all occurences of the terms "affinity
instances and levels" when used to describe the power domain
topology. Only the terminology is changed in this patch. Subsequent
patches will implement functional changes to remove the above
mentioned assumption.
Change-Id: Iee162f051b228828310610c5a320ff9d31009b4e
diff --git a/services/std_svc/psci1.0/psci_setup.c b/services/std_svc/psci1.0/psci_setup.c
index a04f8e7..002e220 100644
--- a/services/std_svc/psci1.0/psci_setup.c
+++ b/services/std_svc/psci1.0/psci_setup.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -42,20 +42,20 @@
* Per cpu non-secure contexts used to program the architectural state prior
* return to the normal world.
* TODO: Use the memory allocator to set aside memory for the contexts instead
- * of relying on platform defined constants. Using PSCI_NUM_AFFS will be an
- * overkill.
+ * of relying on platform defined constants. Using PSCI_NUM_PWR_DOMAINS will be
+ * an overkill.
******************************************************************************/
static cpu_context_t psci_ns_context[PLATFORM_CORE_COUNT];
/*******************************************************************************
- * In a system, a certain number of affinity instances are present at an
- * affinity level. The cumulative number of instances across all levels are
- * stored in 'psci_aff_map'. The topology tree has been flattenned into this
- * array. To retrieve nodes, information about the extents of each affinity
- * level i.e. start index and end index needs to be present. 'psci_aff_limits'
- * stores this information.
+ * In a system, a certain number of power domain instances are present at a
+ * power level. The cumulative number of instances across all levels are
+ * stored in 'psci_pwr_domain_map'. The topology tree has been flattenned into
+ * this array. To retrieve nodes, information about the extents of each power
+ * level i.e. start index and end index needs to be present.
+ * 'psci_pwr_lvl_limits' stores this information.
******************************************************************************/
-aff_limits_node_t psci_aff_limits[MPIDR_MAX_AFFLVL + 1];
+pwr_lvl_limits_node_t psci_pwr_lvl_limits[MPIDR_MAX_AFFLVL + 1];
/******************************************************************************
* Define the psci capability variable.
@@ -64,12 +64,12 @@
/*******************************************************************************
- * Routines for retrieving the node corresponding to an affinity level instance
+ * Routines for retrieving the node corresponding to a power domain instance
* in the mpidr. The first one uses binary search to find the node corresponding
- * to the mpidr (key) at a particular affinity level. The second routine decides
- * extents of the binary search at each affinity level.
+ * to the mpidr (key) at a particular power level. The second routine decides
+ * extents of the binary search at each power level.
******************************************************************************/
-static int psci_aff_map_get_idx(unsigned long key,
+static int psci_pwr_domain_map_get_idx(unsigned long key,
int min_idx,
int max_idx)
{
@@ -85,80 +85,80 @@
/*
* Make sure we are within array limits.
*/
- assert(min_idx >= 0 && max_idx < PSCI_NUM_AFFS);
+ assert(min_idx >= 0 && max_idx < PSCI_NUM_PWR_DOMAINS);
/*
* Bisect the array around 'mid' and then recurse into the array chunk
* where the key is likely to be found. The mpidrs in each node in the
- * 'psci_aff_map' for a given affinity level are stored in an ascending
- * order which makes the binary search possible.
+ * 'psci_pwr_domain_map' for a given power level are stored in an
+ * ascending order which makes the binary search possible.
*/
mid = min_idx + ((max_idx - min_idx) >> 1); /* Divide by 2 */
- if (psci_aff_map[mid].mpidr > key)
- return psci_aff_map_get_idx(key, min_idx, mid - 1);
- else if (psci_aff_map[mid].mpidr < key)
- return psci_aff_map_get_idx(key, mid + 1, max_idx);
+ if (psci_pwr_domain_map[mid].mpidr > key)
+ return psci_pwr_domain_map_get_idx(key, min_idx, mid - 1);
+ else if (psci_pwr_domain_map[mid].mpidr < key)
+ return psci_pwr_domain_map_get_idx(key, mid + 1, max_idx);
else
return mid;
}
-aff_map_node_t *psci_get_aff_map_node(unsigned long mpidr, int aff_lvl)
+pwr_map_node_t *psci_get_pwr_map_node(unsigned long mpidr, int pwr_lvl)
{
int rc;
- if (aff_lvl > PLATFORM_MAX_AFFLVL)
+ if (pwr_lvl > PLAT_MAX_PWR_LVL)
return NULL;
- /* Right shift the mpidr to the required affinity level */
- mpidr = mpidr_mask_lower_afflvls(mpidr, aff_lvl);
+ /* Right shift the mpidr to the required power level */
+ mpidr = mpidr_mask_lower_afflvls(mpidr, pwr_lvl);
- rc = psci_aff_map_get_idx(mpidr,
- psci_aff_limits[aff_lvl].min,
- psci_aff_limits[aff_lvl].max);
+ rc = psci_pwr_domain_map_get_idx(mpidr,
+ psci_pwr_lvl_limits[pwr_lvl].min,
+ psci_pwr_lvl_limits[pwr_lvl].max);
if (rc >= 0)
- return &psci_aff_map[rc];
+ return &psci_pwr_domain_map[rc];
else
return NULL;
}
/*******************************************************************************
* This function populates an array with nodes corresponding to a given range of
- * affinity levels in an mpidr. It returns successfully only when the affinity
- * levels are correct, the mpidr is valid i.e. no affinity level is absent from
- * the topology tree & the affinity instance at level 0 is not absent.
+ * power levels in an mpidr. It returns successfully only when the power
+ * levels are correct, the mpidr is valid i.e. no power level is absent from
+ * the topology tree & the power domain instance at level 0 is not absent.
******************************************************************************/
-int psci_get_aff_map_nodes(unsigned long mpidr,
- int start_afflvl,
- int end_afflvl,
- aff_map_node_t *mpidr_nodes[])
+int psci_get_pwr_map_nodes(unsigned long mpidr,
+ int start_pwrlvl,
+ int end_pwrlvl,
+ pwr_map_node_t *mpidr_nodes[])
{
int rc = PSCI_E_INVALID_PARAMS, level;
- aff_map_node_t *node;
+ pwr_map_node_t *node;
- rc = psci_check_afflvl_range(start_afflvl, end_afflvl);
+ rc = psci_check_pwrlvl_range(start_pwrlvl, end_pwrlvl);
if (rc != PSCI_E_SUCCESS)
return rc;
- for (level = start_afflvl; level <= end_afflvl; level++) {
+ for (level = start_pwrlvl; level <= end_pwrlvl; level++) {
/*
- * Grab the node for each affinity level. No affinity level
+ * Grab the node for each power level. No power level
* can be missing as that would mean that the topology tree
* is corrupted.
*/
- node = psci_get_aff_map_node(mpidr, level);
+ node = psci_get_pwr_map_node(mpidr, level);
if (node == NULL) {
rc = PSCI_E_INVALID_PARAMS;
break;
}
/*
- * Skip absent affinity levels unless it's afffinity level 0.
+ * Skip absent power levels unless it's power level 0.
* An absent cpu means that the mpidr is invalid. Save the
- * pointer to the node for the present affinity level
+ * pointer to the node for the present power level
*/
- if (!(node->state & PSCI_AFF_PRESENT)) {
+ if (!(node->state & PSCI_PWR_DOMAIN_PRESENT)) {
if (level == MPIDR_AFFLVL0) {
rc = PSCI_E_INVALID_PARAMS;
break;
@@ -173,39 +173,38 @@
}
/*******************************************************************************
- * Function which initializes the 'aff_map_node' corresponding to an affinity
- * level instance. Each node has a unique mpidr, level and bakery lock. The data
- * field is opaque and holds affinity level specific data e.g. for affinity
- * level 0 it contains the index into arrays that hold the secure/non-secure
- * state for a cpu that's been turned on/off
+ * Function which initializes the 'pwr_map_node' corresponding to a power
+ * domain instance. Each node has a unique mpidr, level and bakery lock.
******************************************************************************/
-static void psci_init_aff_map_node(unsigned long mpidr,
+static void psci_init_pwr_map_node(unsigned long mpidr,
int level,
unsigned int idx)
{
unsigned char state;
uint32_t linear_id;
- psci_aff_map[idx].mpidr = mpidr;
- psci_aff_map[idx].level = level;
- psci_lock_init(psci_aff_map, idx);
+ psci_pwr_domain_map[idx].mpidr = mpidr;
+ psci_pwr_domain_map[idx].level = level;
+ psci_lock_init(psci_pwr_domain_map, idx);
/*
- * If an affinity instance is present then mark it as OFF to begin with.
+ * If an power domain instance is present then mark it as OFF
+ * to begin with.
*/
- state = plat_get_aff_state(level, mpidr);
- psci_aff_map[idx].state = state;
+ state = plat_get_pwr_domain_state(level, mpidr);
+ psci_pwr_domain_map[idx].state = state;
if (level == MPIDR_AFFLVL0) {
/*
- * Mark the cpu as OFF. Higher affinity level reference counts
+ * Mark the cpu as OFF. Higher power level reference counts
* have already been memset to 0
*/
- if (state & PSCI_AFF_PRESENT)
- psci_set_state(&psci_aff_map[idx], PSCI_STATE_OFF);
+ if (state & PSCI_PWR_DOMAIN_PRESENT)
+ psci_set_state(&psci_pwr_domain_map[idx],
+ PSCI_STATE_OFF);
/*
- * Associate a non-secure context with this affinity
+ * Associate a non-secure context with this power
* instance through the context management library.
*/
linear_id = platform_get_core_pos(mpidr);
@@ -228,65 +227,68 @@
/*******************************************************************************
* Core routine used by the Breadth-First-Search algorithm to populate the
- * affinity tree. Each level in the tree corresponds to an affinity level. This
- * routine's aim is to traverse to the target affinity level and populate nodes
- * in the 'psci_aff_map' for all the siblings at that level. It uses the current
- * affinity level to keep track of how many levels from the root of the tree
- * have been traversed. If the current affinity level != target affinity level,
+ * power domain tree. Each level in the tree corresponds to a power level. This
+ * routine's aim is to traverse to the target power level and populate nodes
+ * in the 'psci_pwr_domain_map' for all the siblings at that level. It uses the
+ * current power level to keep track of how many levels from the root of the
+ * tree have been traversed. If the current power level != target power level,
* then the platform is asked to return the number of children that each
- * affinity instance has at the current affinity level. Traversal is then done
- * for each child at the next lower level i.e. current affinity level - 1.
+ * power domain instance has at the current power level. Traversal is then done
+ * for each child at the next lower level i.e. current power level - 1.
*
- * CAUTION: This routine assumes that affinity instance ids are allocated in a
- * monotonically increasing manner at each affinity level in a mpidr starting
+ * CAUTION: This routine assumes that power domain instance ids are allocated
+ * in a monotonically increasing manner at each power level in a mpidr starting
* from 0. If the platform breaks this assumption then this code will have to
* be reworked accordingly.
******************************************************************************/
-static unsigned int psci_init_aff_map(unsigned long mpidr,
- unsigned int affmap_idx,
- int cur_afflvl,
- int tgt_afflvl)
+static unsigned int psci_init_pwr_map(unsigned long mpidr,
+ unsigned int pwrmap_idx,
+ int cur_pwrlvl,
+ int tgt_pwrlvl)
{
- unsigned int ctr, aff_count;
+ unsigned int ctr, pwr_inst_count;
- assert(cur_afflvl >= tgt_afflvl);
+ assert(cur_pwrlvl >= tgt_pwrlvl);
/*
- * Find the number of siblings at the current affinity level &
+ * Find the number of siblings at the current power level &
* assert if there are none 'cause then we have been invoked with
* an invalid mpidr.
*/
- aff_count = plat_get_aff_count(cur_afflvl, mpidr);
- assert(aff_count);
+ pwr_inst_count = plat_get_pwr_domain_count(cur_pwrlvl, mpidr);
+ assert(pwr_inst_count);
- if (tgt_afflvl < cur_afflvl) {
- for (ctr = 0; ctr < aff_count; ctr++) {
- mpidr = mpidr_set_aff_inst(mpidr, ctr, cur_afflvl);
- affmap_idx = psci_init_aff_map(mpidr,
- affmap_idx,
- cur_afflvl - 1,
- tgt_afflvl);
+ if (tgt_pwrlvl < cur_pwrlvl) {
+ for (ctr = 0; ctr < pwr_inst_count; ctr++) {
+ mpidr = mpidr_set_pwr_domain_inst(mpidr, ctr,
+ cur_pwrlvl);
+ pwrmap_idx = psci_init_pwr_map(mpidr,
+ pwrmap_idx,
+ cur_pwrlvl - 1,
+ tgt_pwrlvl);
}
} else {
- for (ctr = 0; ctr < aff_count; ctr++, affmap_idx++) {
- mpidr = mpidr_set_aff_inst(mpidr, ctr, cur_afflvl);
- psci_init_aff_map_node(mpidr, cur_afflvl, affmap_idx);
+ for (ctr = 0; ctr < pwr_inst_count; ctr++, pwrmap_idx++) {
+ mpidr = mpidr_set_pwr_domain_inst(mpidr, ctr,
+ cur_pwrlvl);
+ psci_init_pwr_map_node(mpidr, cur_pwrlvl, pwrmap_idx);
}
- /* affmap_idx is 1 greater than the max index of cur_afflvl */
- psci_aff_limits[cur_afflvl].max = affmap_idx - 1;
+ /* pwrmap_idx is 1 greater than the max index of cur_pwrlvl */
+ psci_pwr_lvl_limits[cur_pwrlvl].max = pwrmap_idx - 1;
}
- return affmap_idx;
+ return pwrmap_idx;
}
/*******************************************************************************
* This function initializes the topology tree by querying the platform. To do
- * so, it's helper routines implement a Breadth-First-Search. At each affinity
- * level the platform conveys the number of affinity instances that exist i.e.
- * the affinity count. The algorithm populates the psci_aff_map recursively
- * using this information. On a platform that implements two clusters of 4 cpus
- * each, the populated aff_map_array would look like this:
+ * so, it's helper routines implement a Breadth-First-Search. At each power
+ * level the platform conveys the number of power domain instances that exist
+ * i.e. the power instance count. The algorithm populates the
+ * psci_pwr_domain_map* recursively using this information. On a platform that
+ * implements two clusters of 4 cpus each, the populated pwr_map_array would
+ * look like this:
*
* <- cpus cluster0 -><- cpus cluster1 ->
* ---------------------------------------------------
@@ -298,71 +300,72 @@
*
* The first 2 entries are of the cluster nodes. The next 4 entries are of cpus
* within cluster 0. The last 4 entries are of cpus within cluster 1.
- * The 'psci_aff_limits' array contains the max & min index of each affinity
- * level within the 'psci_aff_map' array. This allows restricting search of a
- * node at an affinity level between the indices in the limits array.
+ * The 'psci_pwr_lvl_limits' array contains the max & min index of each power
+ * level within the 'psci_pwr_domain_map' array. This allows restricting search
+ * of a node at a power level between the indices in the limits array.
******************************************************************************/
int32_t psci_setup(void)
{
unsigned long mpidr = read_mpidr();
- int afflvl, affmap_idx, max_afflvl;
- aff_map_node_t *node;
+ int pwrlvl, pwrmap_idx, max_pwrlvl;
+ pwr_map_node_t *node;
psci_plat_pm_ops = NULL;
- /* Find out the maximum affinity level that the platform implements */
- max_afflvl = PLATFORM_MAX_AFFLVL;
- assert(max_afflvl <= MPIDR_MAX_AFFLVL);
+ /* Find out the maximum power level that the platform implements */
+ max_pwrlvl = PLAT_MAX_PWR_LVL;
+ assert(max_pwrlvl <= MPIDR_MAX_AFFLVL);
/*
* This call traverses the topology tree with help from the platform and
- * populates the affinity map using a breadth-first-search recursively.
- * We assume that the platform allocates affinity instance ids from 0
- * onwards at each affinity level in the mpidr. FIRST_MPIDR = 0.0.0.0
+ * populates the power map using a breadth-first-search recursively.
+ * We assume that the platform allocates power domain instance ids from
+ * 0 onwards at each power level in the mpidr. FIRST_MPIDR = 0.0.0.0
*/
- affmap_idx = 0;
- for (afflvl = max_afflvl; afflvl >= MPIDR_AFFLVL0; afflvl--) {
- affmap_idx = psci_init_aff_map(FIRST_MPIDR,
- affmap_idx,
- max_afflvl,
- afflvl);
+ pwrmap_idx = 0;
+ for (pwrlvl = max_pwrlvl; pwrlvl >= MPIDR_AFFLVL0; pwrlvl--) {
+ pwrmap_idx = psci_init_pwr_map(FIRST_MPIDR,
+ pwrmap_idx,
+ max_pwrlvl,
+ pwrlvl);
}
#if !USE_COHERENT_MEM
/*
- * The psci_aff_map only needs flushing when it's not allocated in
- * coherent memory.
+ * The psci_pwr_domain_map only needs flushing when it's not allocated
+ * in coherent memory.
*/
- flush_dcache_range((uint64_t) &psci_aff_map, sizeof(psci_aff_map));
+ flush_dcache_range((uint64_t) &psci_pwr_domain_map,
+ sizeof(psci_pwr_domain_map));
#endif
/*
- * Set the bounds for the affinity counts of each level in the map. Also
+ * Set the bounds for number of instances of each level in the map. Also
* flush out the entire array so that it's visible to subsequent power
- * management operations. The 'psci_aff_limits' array is allocated in
- * normal memory. It will be accessed when the mmu is off e.g. after
+ * management operations. The 'psci_pwr_lvl_limits' array is allocated
+ * in normal memory. It will be accessed when the mmu is off e.g. after
* reset. Hence it needs to be flushed.
*/
- for (afflvl = MPIDR_AFFLVL0; afflvl < max_afflvl; afflvl++) {
- psci_aff_limits[afflvl].min =
- psci_aff_limits[afflvl + 1].max + 1;
+ for (pwrlvl = MPIDR_AFFLVL0; pwrlvl < max_pwrlvl; pwrlvl++) {
+ psci_pwr_lvl_limits[pwrlvl].min =
+ psci_pwr_lvl_limits[pwrlvl + 1].max + 1;
}
- flush_dcache_range((unsigned long) psci_aff_limits,
- sizeof(psci_aff_limits));
+ flush_dcache_range((unsigned long) psci_pwr_lvl_limits,
+ sizeof(psci_pwr_lvl_limits));
/*
- * Mark the affinity instances in our mpidr as ON. No need to lock as
- * this is the primary cpu.
+ * Mark the power domain instances in our mpidr as ON. No need to lock
+ * as this is the primary cpu.
*/
mpidr &= MPIDR_AFFINITY_MASK;
- for (afflvl = MPIDR_AFFLVL0; afflvl <= max_afflvl; afflvl++) {
+ for (pwrlvl = MPIDR_AFFLVL0; pwrlvl <= max_pwrlvl; pwrlvl++) {
- node = psci_get_aff_map_node(mpidr, afflvl);
+ node = psci_get_pwr_map_node(mpidr, pwrlvl);
assert(node);
/* Mark each present node as ON. */
- if (node->state & PSCI_AFF_PRESENT)
+ if (node->state & PSCI_PWR_DOMAIN_PRESENT)
psci_set_state(node, PSCI_STATE_ON);
}
@@ -372,12 +375,13 @@
/* Initialize the psci capability */
psci_caps = PSCI_GENERIC_CAP;
- if (psci_plat_pm_ops->affinst_off)
+ if (psci_plat_pm_ops->pwr_domain_off)
psci_caps |= define_psci_cap(PSCI_CPU_OFF);
- if (psci_plat_pm_ops->affinst_on && psci_plat_pm_ops->affinst_on_finish)
+ if (psci_plat_pm_ops->pwr_domain_on &&
+ psci_plat_pm_ops->pwr_domain_on_finish)
psci_caps |= define_psci_cap(PSCI_CPU_ON_AARCH64);
- if (psci_plat_pm_ops->affinst_suspend &&
- psci_plat_pm_ops->affinst_suspend_finish) {
+ if (psci_plat_pm_ops->pwr_domain_suspend &&
+ psci_plat_pm_ops->pwr_domain_suspend_finish) {
psci_caps |= define_psci_cap(PSCI_CPU_SUSPEND_AARCH64);
if (psci_plat_pm_ops->get_sys_suspend_power_state)
psci_caps |= define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64);