diff --git a/drivers/rpi3/sdhost/rpi3_sdhost.c b/drivers/rpi3/sdhost/rpi3_sdhost.c
index efcd6db..c4b6fca 100644
--- a/drivers/rpi3/sdhost/rpi3_sdhost.c
+++ b/drivers/rpi3/sdhost/rpi3_sdhost.c
@@ -272,8 +272,6 @@
 	}
 
 	cmd_idx = cmd->cmd_idx & HC_CMD_COMMAND_MASK;
-	if (cmd_idx == MMC_CMD(17))
-		cmd_idx = MMC_CMD(18);
 
 	cmd_arg = cmd->cmd_arg;
 	if (cmd_idx == MMC_ACMD(51)) {
@@ -364,8 +362,12 @@
 		mmio_write_32(reg_base + HC_HOSTSTATUS,
 			      HC_HSTST_MASK_ERROR_ALL);
 
+		/*
+		 * If the command SEND_OP_COND returns with CRC7 error,
+		 * it can be considered as having completed successfully.
+		 */
 		if (!(sdhsts & HC_HSTST_ERROR_CRC7)
-		    || (cmd_idx != MMC_ACMD(51))) {
+		    || (cmd_idx != MMC_CMD(1))) {
 			if (sdhsts & HC_HSTST_TIMEOUT_CMD) {
 				ERROR("rpi3_sdhost: timeout status 0x%x\n",
 				      sdhsts);
@@ -533,21 +535,6 @@
 	if (rpi3_sdhost_params.current_cmd == MMC_CMD(18))
 		send_command_decorated(MMC_CMD(12), 0);
 
-	if (err == -(EILSEQ)) {
-		const int max_retries = 20;
-		int r;
-
-		rpi3_sdhost_params.crc_err_retries++;
-		if (rpi3_sdhost_params.crc_err_retries < max_retries) {
-			/* retries if there's an CRC error */
-			r = rpi3_sdhost_prepare(lba, buf, size);
-			send_command_decorated(MMC_CMD(18), lba);
-			r = rpi3_sdhost_read(lba, buf, size);
-			if (r == 0)
-				err = 0;
-		}
-	}
-
 	return err;
 }
 
@@ -617,16 +604,20 @@
 	}
 
 	/* setting pull resistors for 48 to 53.
-	 * GPIO 48 (SD_CLK) to GPIO_PULL_UP
-	 * GPIO 49 (SD_CMD) to GPIO_PULL_NONE
-	 * GPIO 50 (SD_D0)  to GPIO_PULL_NONE
-	 * GPIO 51 (SD_D1)  to GPIO_PULL_NONE
-	 * GPIO 52 (SD_D2)  to GPIO_PULL_NONE
-	 * GPIO 53 (SD_D3)  to GPIO_PULL_NONE
+	 * It is debatable to set SD_CLK to UP or NONE. We massively
+	 * tested different brands of SD Cards and found NONE works
+	 * most stable.
+	 *
+	 * GPIO 48 (SD_CLK) to GPIO_PULL_NONE
+	 * GPIO 49 (SD_CMD) to GPIO_PULL_UP
+	 * GPIO 50 (SD_D0)  to GPIO_PULL_UP
+	 * GPIO 51 (SD_D1)  to GPIO_PULL_UP
+	 * GPIO 52 (SD_D2)  to GPIO_PULL_UP
+	 * GPIO 53 (SD_D3)  to GPIO_PULL_UP
 	 */
-	gpio_set_pull(48, GPIO_PULL_UP);
+	gpio_set_pull(48, GPIO_PULL_NONE);
 	for (int i = 49; i <= 53; i++)
-		gpio_set_pull(i, GPIO_PULL_NONE);
+		gpio_set_pull(i, GPIO_PULL_UP);
 
 	/* Set pin 48-53 to alt-0. It means route SDHOST to card slot */
 	for (int i = 48; i <= 53; i++)
@@ -675,15 +666,14 @@
 				     rpi3_sdhost_params.gpio48_pinselect[i-48]);
 	}
 
-	/* Must reset the pull resistors for u-boot to work.
-	 * GPIO 48 (SD_CLK) to GPIO_PULL_NONE
+	/* Reset the pull resistors before entering BL33.
+	 * GPIO 48 (SD_CLK) to GPIO_PULL_UP
 	 * GPIO 49 (SD_CMD) to GPIO_PULL_UP
 	 * GPIO 50 (SD_D0)  to GPIO_PULL_UP
 	 * GPIO 51 (SD_D1)  to GPIO_PULL_UP
 	 * GPIO 52 (SD_D2)  to GPIO_PULL_UP
 	 * GPIO 53 (SD_D3)  to GPIO_PULL_UP
 	 */
-	gpio_set_pull(48, GPIO_PULL_NONE);
-	for (int i = 49; i <= 53; i++)
+	for (int i = 48; i <= 53; i++)
 		gpio_set_pull(i, GPIO_PULL_UP);
 }
diff --git a/include/drivers/rpi3/sdhost/rpi3_sdhost.h b/include/drivers/rpi3/sdhost/rpi3_sdhost.h
index bc906e3..1653240 100644
--- a/include/drivers/rpi3/sdhost/rpi3_sdhost.h
+++ b/include/drivers/rpi3/sdhost/rpi3_sdhost.h
@@ -21,7 +21,6 @@
 	uint8_t		cmdbusy;
 	uint8_t		mmc_app_cmd;
 	uint32_t	ns_per_fifo_word;
-	uint32_t	crc_err_retries;
 
 	uint32_t	sdcard_rca;
 	uint32_t	gpio48_pinselect[6];
diff --git a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_nt_fw_config.dts b/plat/arm/board/rde1edge/fdts/rde1edge_nt_fw_config.dts
similarity index 77%
rename from plat/arm/board/sgiclarkh/fdts/sgiclarkh_nt_fw_config.dts
rename to plat/arm/board/rde1edge/fdts/rde1edge_nt_fw_config.dts
index 3dedf1d..4176921 100644
--- a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_nt_fw_config.dts
+++ b/plat/arm/board/rde1edge/fdts/rde1edge_nt_fw_config.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,7 +7,7 @@
 /dts-v1/;
 / {
 	/* compatible string */
-	compatible = "arm,sgi-clark";
+	compatible = "arm,rd-e1edge";
 
 	/*
 	 * Place holder for system-id node with default values. The
diff --git a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_tb_fw_config.dts b/plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts
similarity index 100%
rename from plat/arm/board/sgiclarkh/fdts/sgiclarkh_tb_fw_config.dts
rename to plat/arm/board/rde1edge/fdts/rde1edge_tb_fw_config.dts
diff --git a/plat/arm/board/sgiclarkh/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h
similarity index 75%
rename from plat/arm/board/sgiclarkh/include/platform_def.h
rename to plat/arm/board/rde1edge/include/platform_def.h
index fe8907b..954a1cd 100644
--- a/plat/arm/board/sgiclarkh/include/platform_def.h
+++ b/plat/arm/board/rde1edge/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -18,8 +18,8 @@
 #define PLAT_CSS_MHU_BASE		UL(0x45400000)
 
 /* Base address of DMC-620 instances */
-#define SGICLARKH_DMC620_BASE0		UL(0x4e000000)
-#define SGICLARKH_DMC620_BASE1		UL(0x4e100000)
+#define RDE1EDGE_DMC620_BASE0		UL(0x4e000000)
+#define RDE1EDGE_DMC620_BASE1		UL(0x4e100000)
 
 #define PLAT_MAX_PWR_LVL		ARM_PWR_LVL2
 
diff --git a/plat/arm/board/sgiclarkh/platform.mk b/plat/arm/board/rde1edge/platform.mk
similarity index 73%
rename from plat/arm/board/sgiclarkh/platform.mk
rename to plat/arm/board/rde1edge/platform.mk
index 1e93d93..833bb82 100644
--- a/plat/arm/board/sgiclarkh/platform.mk
+++ b/plat/arm/board/rde1edge/platform.mk
@@ -6,34 +6,34 @@
 
 include plat/arm/css/sgi/sgi-common.mk
 
-SGICLARKH_BASE		=	plat/arm/board/sgiclarkh
+RDE1EDGE_BASE		=	plat/arm/board/rde1edge
 
-PLAT_INCLUDES		+=	-I${SGICLARKH_BASE}/include/
+PLAT_INCLUDES		+=	-I${RDE1EDGE_BASE}/include/
 
 SGI_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_e1.S
 
 BL1_SOURCES		+=	${SGI_CPU_SOURCES}
 
-BL2_SOURCES		+=	${SGICLARKH_BASE}/sgiclarkh_plat.c	\
-				${SGICLARKH_BASE}/sgiclarkh_security.c	\
+BL2_SOURCES		+=	${RDE1EDGE_BASE}/rde1edge_plat.c	\
+				${RDE1EDGE_BASE}/rde1edge_security.c	\
 				drivers/arm/tzc/tzc_dmc620.c		\
 				lib/utils/mem_region.c			\
 				plat/arm/common/arm_nor_psci_mem_protect.c
 
 BL31_SOURCES		+=	${SGI_CPU_SOURCES}			\
-				${SGICLARKH_BASE}/sgiclarkh_plat.c	\
+				${RDE1EDGE_BASE}/rde1edge_plat.c	\
 				drivers/cfi/v2m/v2m_flash.c		\
 				lib/utils/mem_region.c			\
 				plat/arm/common/arm_nor_psci_mem_protect.c
 
 # Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES		+=	${SGICLARKH_BASE}/fdts/${PLAT}_tb_fw_config.dts
+FDT_SOURCES		+=	${RDE1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts
 TB_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
 
 # Add the TB_FW_CONFIG to FIP and specify the same to certtool
 $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
 
-FDT_SOURCES		+=	${SGICLARKH_BASE}/fdts/${PLAT}_nt_fw_config.dts
+FDT_SOURCES		+=	${RDE1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts
 NT_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
 
 # Add the NT_FW_CONFIG to FIP and specify the same to certtool
diff --git a/plat/arm/board/sgiclarkh/sgiclarkh_plat.c b/plat/arm/board/rde1edge/rde1edge_plat.c
similarity index 100%
rename from plat/arm/board/sgiclarkh/sgiclarkh_plat.c
rename to plat/arm/board/rde1edge/rde1edge_plat.c
diff --git a/plat/arm/board/rde1edge/rde1edge_security.c b/plat/arm/board/rde1edge/rde1edge_security.c
new file mode 100644
index 0000000..2123e09
--- /dev/null
+++ b/plat/arm/board/rde1edge/rde1edge_security.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/arm/tzc_dmc620.h>
+
+uintptr_t rde1edge_dmc_base[] = {
+	RDE1EDGE_DMC620_BASE0,
+	RDE1EDGE_DMC620_BASE1
+};
+
+static const tzc_dmc620_driver_data_t rde1edge_plat_driver_data = {
+	.dmc_base = rde1edge_dmc_base,
+	.dmc_count = ARRAY_SIZE(rde1edge_dmc_base)
+};
+
+static const tzc_dmc620_acc_addr_data_t rde1edge_acc_addr_data[] = {
+	{
+		.region_base = ARM_AP_TZC_DRAM1_BASE,
+		.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
+		.sec_attr = TZC_DMC620_REGION_S_RDWR
+	}
+};
+
+static const tzc_dmc620_config_data_t rde1edge_plat_config_data = {
+	.plat_drv_data = &rde1edge_plat_driver_data,
+	.plat_acc_addr_data = rde1edge_acc_addr_data,
+	.acc_addr_count = ARRAY_SIZE(rde1edge_acc_addr_data)
+};
+
+/* Initialize the secure environment */
+void plat_arm_security_setup(void)
+{
+	arm_tzc_dmc620_setup(&rde1edge_plat_config_data);
+}
diff --git a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_nt_fw_config.dts b/plat/arm/board/rdn1edge/fdts/rdn1edge_nt_fw_config.dts
similarity index 74%
copy from plat/arm/board/sgiclarkh/fdts/sgiclarkh_nt_fw_config.dts
copy to plat/arm/board/rdn1edge/fdts/rdn1edge_nt_fw_config.dts
index 3dedf1d..fff5874 100644
--- a/plat/arm/board/sgiclarkh/fdts/sgiclarkh_nt_fw_config.dts
+++ b/plat/arm/board/rdn1edge/fdts/rdn1edge_nt_fw_config.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,7 +7,7 @@
 /dts-v1/;
 / {
 	/* compatible string */
-	compatible = "arm,sgi-clark";
+	compatible = "arm,rd-n1edge";
 
 	/*
 	 * Place holder for system-id node with default values. The
@@ -18,5 +18,4 @@
 		platform-id = <0x0>;
 		config-id = <0x0>;
 	};
-
 };
diff --git a/plat/arm/board/sgiclarka/fdts/sgiclarka_tb_fw_config.dts b/plat/arm/board/rdn1edge/fdts/rdn1edge_tb_fw_config.dts
similarity index 100%
rename from plat/arm/board/sgiclarka/fdts/sgiclarka_tb_fw_config.dts
rename to plat/arm/board/rdn1edge/fdts/rdn1edge_tb_fw_config.dts
diff --git a/plat/arm/board/sgiclarka/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h
similarity index 74%
rename from plat/arm/board/sgiclarka/include/platform_def.h
rename to plat/arm/board/rdn1edge/include/platform_def.h
index d2cdb49..2ca0dd4 100644
--- a/plat/arm/board/sgiclarka/include/platform_def.h
+++ b/plat/arm/board/rdn1edge/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -18,8 +18,8 @@
 #define PLAT_CSS_MHU_BASE		UL(0x45400000)
 
 /* Base address of DMC-620 instances */
-#define SGICLARKA_DMC620_BASE0		UL(0x4e000000)
-#define SGICLARKA_DMC620_BASE1		UL(0x4e100000)
+#define RDN1EDGE_DMC620_BASE0		UL(0x4e000000)
+#define RDN1EDGE_DMC620_BASE1		UL(0x4e100000)
 
 /* System power domain level */
 #define CSS_SYSTEM_PWR_DMN_LVL		ARM_PWR_LVL2
diff --git a/plat/arm/board/sgiclarka/platform.mk b/plat/arm/board/rdn1edge/platform.mk
similarity index 73%
rename from plat/arm/board/sgiclarka/platform.mk
rename to plat/arm/board/rdn1edge/platform.mk
index 81e416e..cacdaa1 100644
--- a/plat/arm/board/sgiclarka/platform.mk
+++ b/plat/arm/board/rdn1edge/platform.mk
@@ -6,34 +6,34 @@
 
 include plat/arm/css/sgi/sgi-common.mk
 
-SGICLARKA_BASE		=	plat/arm/board/sgiclarka
+RDN1EDGE_BASE		=	plat/arm/board/rdn1edge
 
-PLAT_INCLUDES		+=	-I${SGICLARKA_BASE}/include/
+PLAT_INCLUDES		+=	-I${RDN1EDGE_BASE}/include/
 
 SGI_CPU_SOURCES		:=	lib/cpus/aarch64/neoverse_n1.S
 
 BL1_SOURCES		+=	${SGI_CPU_SOURCES}
 
-BL2_SOURCES		+=	${SGICLARKA_BASE}/sgiclarka_plat.c	\
-				${SGICLARKA_BASE}/sgiclarka_security.c	\
+BL2_SOURCES		+=	${RDN1EDGE_BASE}/rdn1edge_plat.c	\
+				${RDN1EDGE_BASE}/rdn1edge_security.c	\
 				drivers/arm/tzc/tzc_dmc620.c		\
 				lib/utils/mem_region.c			\
 				plat/arm/common/arm_nor_psci_mem_protect.c
 
 BL31_SOURCES		+=	${SGI_CPU_SOURCES}			\
-				${SGICLARKA_BASE}/sgiclarka_plat.c	\
+				${RDN1EDGE_BASE}/rdn1edge_plat.c	\
 				drivers/cfi/v2m/v2m_flash.c		\
 				lib/utils/mem_region.c			\
 				plat/arm/common/arm_nor_psci_mem_protect.c
 
 # Add the FDT_SOURCES and options for Dynamic Config
-FDT_SOURCES		+=	${SGICLARKA_BASE}/fdts/${PLAT}_tb_fw_config.dts
+FDT_SOURCES		+=	${RDN1EDGE_BASE}/fdts/${PLAT}_tb_fw_config.dts
 TB_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
 
 # Add the TB_FW_CONFIG to FIP and specify the same to certtool
 $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
 
-FDT_SOURCES		+=	${SGICLARKA_BASE}/fdts/${PLAT}_nt_fw_config.dts
+FDT_SOURCES		+=	${RDN1EDGE_BASE}/fdts/${PLAT}_nt_fw_config.dts
 NT_FW_CONFIG		:=	${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb
 
 # Add the NT_FW_CONFIG to FIP and specify the same to certtool
diff --git a/plat/arm/board/sgiclarka/sgiclarka_plat.c b/plat/arm/board/rdn1edge/rdn1edge_plat.c
similarity index 100%
rename from plat/arm/board/sgiclarka/sgiclarka_plat.c
rename to plat/arm/board/rdn1edge/rdn1edge_plat.c
diff --git a/plat/arm/board/rdn1edge/rdn1edge_security.c b/plat/arm/board/rdn1edge/rdn1edge_security.c
new file mode 100644
index 0000000..ffa8935
--- /dev/null
+++ b/plat/arm/board/rdn1edge/rdn1edge_security.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019, ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <platform_def.h>
+
+#include <common/debug.h>
+#include <drivers/arm/tzc_dmc620.h>
+
+uintptr_t rdn1edge_dmc_base[] = {
+	RDN1EDGE_DMC620_BASE0,
+	RDN1EDGE_DMC620_BASE1
+};
+
+static const tzc_dmc620_driver_data_t rdn1edge_plat_driver_data = {
+	.dmc_base = rdn1edge_dmc_base,
+	.dmc_count = ARRAY_SIZE(rdn1edge_dmc_base)
+};
+
+static const tzc_dmc620_acc_addr_data_t rdn1edge_acc_addr_data[] = {
+	{
+		.region_base = ARM_AP_TZC_DRAM1_BASE,
+		.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
+		.sec_attr = TZC_DMC620_REGION_S_RDWR
+	}
+};
+
+static const tzc_dmc620_config_data_t rdn1edge_plat_config_data = {
+	.plat_drv_data = &rdn1edge_plat_driver_data,
+	.plat_acc_addr_data = rdn1edge_acc_addr_data,
+	.acc_addr_count = ARRAY_SIZE(rdn1edge_acc_addr_data)
+};
+
+/* Initialize the secure environment */
+void plat_arm_security_setup(void)
+{
+	arm_tzc_dmc620_setup(&rdn1edge_plat_config_data);
+}
diff --git a/plat/arm/board/sgiclarka/fdts/sgiclarka_nt_fw_config.dts b/plat/arm/board/sgiclarka/fdts/sgiclarka_nt_fw_config.dts
deleted file mode 100644
index 43bd856..0000000
--- a/plat/arm/board/sgiclarka/fdts/sgiclarka_nt_fw_config.dts
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-/dts-v1/;
-/ {
-	/* compatible string */
-	compatible = "arm,sgi-clark";
-
-	/*
-	 * Place holder for system-id node with default values. The
-	 * value of platform-id and config-id will be set to the
-	 * correct values during the BL2 stage of boot.
-	 */
-	system-id {
-		platform-id = <0x0>;
-		config-id = <0x0>;
-	};
-};
diff --git a/plat/arm/board/sgiclarka/sgiclarka_security.c b/plat/arm/board/sgiclarka/sgiclarka_security.c
deleted file mode 100644
index c455111..0000000
--- a/plat/arm/board/sgiclarka/sgiclarka_security.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <drivers/arm/tzc_dmc620.h>
-
-uintptr_t sgiclarka_dmc_base[] = {
-	SGICLARKA_DMC620_BASE0,
-	SGICLARKA_DMC620_BASE1
-};
-
-static const tzc_dmc620_driver_data_t sgiclarka_plat_driver_data = {
-	.dmc_base = sgiclarka_dmc_base,
-	.dmc_count = ARRAY_SIZE(sgiclarka_dmc_base)
-};
-
-static const tzc_dmc620_acc_addr_data_t sgiclarka_acc_addr_data[] = {
-	{
-		.region_base = ARM_AP_TZC_DRAM1_BASE,
-		.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
-		.sec_attr = TZC_DMC620_REGION_S_RDWR
-	}
-};
-
-static const tzc_dmc620_config_data_t sgiclarka_plat_config_data = {
-	.plat_drv_data = &sgiclarka_plat_driver_data,
-	.plat_acc_addr_data = sgiclarka_acc_addr_data,
-	.acc_addr_count = ARRAY_SIZE(sgiclarka_acc_addr_data)
-};
-
-/* Initialize the secure environment */
-void plat_arm_security_setup(void)
-{
-	arm_tzc_dmc620_setup(&sgiclarka_plat_config_data);
-}
diff --git a/plat/arm/board/sgiclarkh/sgiclarkh_security.c b/plat/arm/board/sgiclarkh/sgiclarkh_security.c
deleted file mode 100644
index aaf9691..0000000
--- a/plat/arm/board/sgiclarkh/sgiclarkh_security.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2018, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <platform_def.h>
-
-#include <common/debug.h>
-#include <drivers/arm/tzc_dmc620.h>
-
-uintptr_t sgiclarkh_dmc_base[] = {
-	SGICLARKH_DMC620_BASE0,
-	SGICLARKH_DMC620_BASE1
-};
-
-static const tzc_dmc620_driver_data_t sgiclarkh_plat_driver_data = {
-	.dmc_base = sgiclarkh_dmc_base,
-	.dmc_count = ARRAY_SIZE(sgiclarkh_dmc_base)
-};
-
-static const tzc_dmc620_acc_addr_data_t sgiclarkh_acc_addr_data[] = {
-	{
-		.region_base = ARM_AP_TZC_DRAM1_BASE,
-		.region_top = ARM_AP_TZC_DRAM1_BASE + ARM_TZC_DRAM1_SIZE - 1,
-		.sec_attr = TZC_DMC620_REGION_S_RDWR
-	}
-};
-
-static const tzc_dmc620_config_data_t sgiclarkh_plat_config_data = {
-	.plat_drv_data = &sgiclarkh_plat_driver_data,
-	.plat_acc_addr_data = sgiclarkh_acc_addr_data,
-	.acc_addr_count = ARRAY_SIZE(sgiclarkh_acc_addr_data)
-};
-
-/* Initialize the secure environment */
-void plat_arm_security_setup(void)
-{
-	arm_tzc_dmc620_setup(&sgiclarkh_plat_config_data);
-}
diff --git a/plat/rpi3/rpi3_bl2_setup.c b/plat/rpi3/rpi3_bl2_setup.c
index 3d1f8f9..b5e5835 100644
--- a/plat/rpi3/rpi3_bl2_setup.c
+++ b/plat/rpi3/rpi3_bl2_setup.c
@@ -44,8 +44,8 @@
 
 	memset(&params, 0, sizeof(struct rpi3_sdhost_params));
 	params.reg_base = RPI3_SDHOST_BASE;
-	params.bus_width = MMC_BUS_WIDTH_4;
-	params.clk_rate = 392464;
+	params.bus_width = MMC_BUS_WIDTH_1;
+	params.clk_rate = 50000000;
 	mmc_info.mmc_dev_type = MMC_IS_SD_HC;
 	rpi3_sdhost_init(&params, &mmc_info);
 }
diff --git a/readme.rst b/readme.rst
index deca2d2..ae9ca80 100644
--- a/readme.rst
+++ b/readme.rst
@@ -194,7 +194,7 @@
 
 -  Allwinner sun50i_64 and sun50i_h6
 -  Amlogic Meson S905 (GXBB)
--  Arm SGI-575, SGI Clark.A, SGI Clark.H and SGM-775
+-  Arm SGI-575, RDN1Edge, RDE1Edge and SGM-775
 -  Arm Neoverse N1 System Development Platform
 -  HiKey, HiKey960 and Poplar boards
 -  Marvell Armada 3700 and 8K