Clarify platform porting interface to TSP
* Move TSP platform porting functions to new file:
include/bl32/tsp/platform_tsp.h.
* Create new TSP_IRQ_SEC_PHY_TIMER definition for use by the generic
TSP interrupt handling code, instead of depending on the FVP
specific definition IRQ_SEC_PHY_TIMER.
* Rename TSP platform porting functions from bl32_* to tsp_*, and
definitions from BL32_* to TSP_*.
* Update generic TSP code to use new platform porting function names
and definitions.
* Update FVP port accordingly and move all TSP source files to:
plat/fvp/tsp/.
* Update porting guide with above changes.
Note: THIS CHANGE REQUIRES ALL PLATFORM PORTS OF THE TSP TO
BE UPDATED
Fixes ARM-software/tf-issues#167
Change-Id: Ic0ff8caf72aebb378d378193d2f017599fc6b78f
diff --git a/plat/fvp/include/platform_def.h b/plat/fvp/include/platform_def.h
index c87ba54..32f070f 100644
--- a/plat/fvp/include/platform_def.h
+++ b/plat/fvp/include/platform_def.h
@@ -32,7 +32,7 @@
#define __PLATFORM_DEF_H__
#include <arch.h>
-#include <../fvp_def.h>
+#include "../fvp_def.h"
/*******************************************************************************
@@ -131,8 +131,8 @@
#if FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_SRAM
# define TSP_SEC_MEM_BASE FVP_TRUSTED_SRAM_BASE
# define TSP_SEC_MEM_SIZE FVP_TRUSTED_SRAM_SIZE
+# define TSP_PROGBITS_LIMIT BL2_BASE
# define BL32_BASE FVP_TRUSTED_SRAM_BASE
-# define BL32_PROGBITS_LIMIT BL2_BASE
# define BL32_LIMIT BL31_BASE
#elif FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM
# define TSP_SEC_MEM_BASE FVP_TRUSTED_DRAM_BASE
@@ -144,6 +144,11 @@
# error "Unsupported FVP_TSP_RAM_LOCATION_ID value"
#endif
+/*
+ * ID of the secure physical generic timer interrupt used by the TSP.
+ */
+#define TSP_IRQ_SEC_PHY_TIMER IRQ_SEC_PHY_TIMER
+
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
@@ -152,11 +157,6 @@
#define MAX_MMAP_REGIONS 16
/*******************************************************************************
- * ID of the secure physical generic timer interrupt.
- ******************************************************************************/
-#define IRQ_SEC_PHY_TIMER 29
-
-/*******************************************************************************
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
* to the platform as it might have a combination of integrated and external