diff --git a/include/plat/arm/board/common/v2m_def.h b/include/plat/arm/board/common/v2m_def.h
index 6a6979c..cb11dac 100644
--- a/include/plat/arm/board/common/v2m_def.h
+++ b/include/plat/arm/board/common/v2m_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -8,6 +8,13 @@
 
 #include <lib/utils_def.h>
 
+/* Base address of all V2M */
+#ifdef PLAT_V2M_OFFSET
+#define V2M_OFFSET			PLAT_V2M_OFFSET
+#else
+#define V2M_OFFSET			UL(0)
+#endif
+
 /* V2M motherboard system registers & offsets */
 #define V2M_SYSREGS_BASE		UL(0x1c010000)
 #define V2M_SYS_ID			UL(0x0)
@@ -69,18 +76,18 @@
 
 
 /* NOR Flash */
-#define V2M_FLASH0_BASE			UL(0x08000000)
+#define V2M_FLASH0_BASE			(V2M_OFFSET + UL(0x08000000))
 #define V2M_FLASH0_SIZE			UL(0x04000000)
-#define V2M_FLASH_BLOCK_SIZE		UL(0x00040000)	/* 256 KB */
+#define V2M_FLASH_BLOCK_SIZE		UL(0x00040000) /* 256 KB */
 
-#define V2M_IOFPGA_BASE			UL(0x1c000000)
+#define V2M_IOFPGA_BASE			(V2M_OFFSET + UL(0x1c000000))
 #define V2M_IOFPGA_SIZE			UL(0x03000000)
 
 /* PL011 UART related constants */
-#define V2M_IOFPGA_UART0_BASE		UL(0x1c090000)
-#define V2M_IOFPGA_UART1_BASE		UL(0x1c0a0000)
-#define V2M_IOFPGA_UART2_BASE		UL(0x1c0b0000)
-#define V2M_IOFPGA_UART3_BASE		UL(0x1c0c0000)
+#define V2M_IOFPGA_UART0_BASE		(V2M_OFFSET + UL(0x1c090000))
+#define V2M_IOFPGA_UART1_BASE		(V2M_OFFSET + UL(0x1c0a0000))
+#define V2M_IOFPGA_UART2_BASE		(V2M_OFFSET + UL(0x1c0b0000))
+#define V2M_IOFPGA_UART3_BASE		(V2M_OFFSET + UL(0x1c0c0000))
 
 #define V2M_IOFPGA_UART0_CLK_IN_HZ	24000000
 #define V2M_IOFPGA_UART1_CLK_IN_HZ	24000000
@@ -88,11 +95,11 @@
 #define V2M_IOFPGA_UART3_CLK_IN_HZ	24000000
 
 /* SP804 timer related constants */
-#define V2M_SP804_TIMER0_BASE		UL(0x1C110000)
-#define V2M_SP804_TIMER1_BASE		UL(0x1C120000)
+#define V2M_SP804_TIMER0_BASE		(V2M_OFFSET + UL(0x1C110000))
+#define V2M_SP804_TIMER1_BASE		(V2M_OFFSET + UL(0x1C120000))
 
 /* SP810 controller */
-#define V2M_SP810_BASE			UL(0x1c020000)
+#define V2M_SP810_BASE			(V2M_OFFSET + UL(0x1c020000))
 #define V2M_SP810_CTRL_TIM0_SEL		BIT_32(15)
 #define V2M_SP810_CTRL_TIM1_SEL		BIT_32(17)
 #define V2M_SP810_CTRL_TIM2_SEL		BIT_32(19)
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 9d47b90..08f7ff9 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -58,12 +58,11 @@
 #define ARM_TRUSTED_DRAM_ID		1
 #define ARM_DRAM_ID			2
 
-/* The first 4KB of Trusted SRAM are used as shared memory */
-#ifdef __PLAT_ARM_TRUSTED_SRAM_BASE__
+#ifdef PLAT_ARM_TRUSTED_SRAM_BASE
 #define ARM_TRUSTED_SRAM_BASE		PLAT_ARM_TRUSTED_SRAM_BASE
 #else
 #define ARM_TRUSTED_SRAM_BASE		UL(0x04000000)
-#endif /* __PLAT_ARM_TRUSTED_SRAM_BASE__ */
+#endif /* PLAT_ARM_TRUSTED_SRAM_BASE */
 
 #define ARM_SHARED_RAM_BASE		ARM_TRUSTED_SRAM_BASE
 #define ARM_SHARED_RAM_SIZE		UL(0x00001000)	/* 4 KB */
@@ -154,11 +153,11 @@
 					 ARM_TZC_DRAM1_SIZE)
 #define ARM_NS_DRAM1_END		(ARM_NS_DRAM1_BASE +		\
 					 ARM_NS_DRAM1_SIZE - 1U)
-#ifdef __PLAT_ARM_DRAM1_BASE__
+#ifdef PLAT_ARM_DRAM1_BASE
 #define ARM_DRAM1_BASE			PLAT_ARM_DRAM1_BASE
 #else
 #define ARM_DRAM1_BASE			ULL(0x80000000)
-#endif /* __PLAT_ARM_DRAM1_BASE__ */
+#endif /* PLAT_ARM_DRAM1_BASE */
 
 #define ARM_DRAM1_SIZE			ULL(0x80000000)
 #define ARM_DRAM1_END			(ARM_DRAM1_BASE +		\
@@ -321,16 +320,44 @@
 					 ARM_BL_REGIONS)
 
 /* Memory mapped Generic timer interfaces  */
+#ifdef PLAT_ARM_SYS_CNTCTL_BASE
+#define ARM_SYS_CNTCTL_BASE             PLAT_ARM_SYS_CNTCTL_BASE
+#else
 #define ARM_SYS_CNTCTL_BASE		UL(0x2a430000)
+#endif
+
+#ifdef PLAT_ARM_SYS_CNTREAD_BASE
+#define ARM_SYS_CNTREAD_BASE             PLAT_ARM_SYS_CNTREAD_BASE
+#else
 #define ARM_SYS_CNTREAD_BASE		UL(0x2a800000)
+#endif
+
+#ifdef PLAT_ARM_SYS_TIMCTL_BASE
+#define ARM_SYS_TIMCTL_BASE             PLAT_ARM_SYS_TIMCTL_BASE
+#else
 #define ARM_SYS_TIMCTL_BASE		UL(0x2a810000)
+#endif
+
+#ifdef PLAT_ARM_SYS_CNT_BASE_S
+#define ARM_SYS_CNT_BASE_S             PLAT_ARM_SYS_CNT_BASE_S
+#else
 #define ARM_SYS_CNT_BASE_S		UL(0x2a820000)
+#endif
+
+#ifdef PLAT_ARM_SYS_CNT_BASE_NS
+#define ARM_SYS_CNT_BASE_NS             PLAT_ARM_SYS_CNT_BASE_NS
+#else
 #define ARM_SYS_CNT_BASE_NS		UL(0x2a830000)
+#endif
 
 #define ARM_CONSOLE_BAUDRATE		115200
 
 /* Trusted Watchdog constants */
+#ifdef PLAT_ARM_SP805_TWDG_BASE
+#define ARM_SP805_TWDG_BASE             PLAT_ARM_SP805_TWDG_BASE
+#else
 #define ARM_SP805_TWDG_BASE		UL(0x2a490000)
+#endif
 #define ARM_SP805_TWDG_CLK_HZ		32768
 /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
  * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */