refactor(cpufeat): separate the EL2 and EL3 enablement code
Combining the EL2 and EL3 enablement code necessitates that it must be
called at el3_exit, which is the only place with enough context to make
the decision of what needs to be set.
Decouple them to allow them to be called from elsewhere.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I147764c42771e7d4100699ec8fae98dac0a505c0
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index 4a6598a..b7d014a 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -505,43 +505,10 @@
static void manage_extensions_nonsecure_mixed(bool el2_unused, cpu_context_t *ctx)
{
#if IMAGE_BL31
- if (is_feat_spe_supported()) {
- spe_enable(el2_unused);
- }
-
if (is_feat_amu_supported()) {
amu_enable(el2_unused, ctx);
}
-
- /* Enable SVE and FPU/SIMD */
- if (is_feat_sve_supported()) {
- sve_enable(ctx);
- }
-
- if (is_feat_sme_supported()) {
- sme_enable(ctx);
- }
-
- if (is_feat_mpam_supported()) {
- mpam_enable(el2_unused);
- }
-
- if (is_feat_trbe_supported()) {
- trbe_enable();
- }
-
- if (is_feat_brbe_supported()) {
- brbe_enable();
- }
-
- if (is_feat_sys_reg_trace_supported()) {
- sys_reg_trace_enable(ctx);
- }
-
- if (is_feat_trf_supported()) {
- trf_enable();
- }
-#endif
+#endif /* IMAGE_BL31 */
}
/*******************************************************************************
@@ -552,7 +519,31 @@
#if IMAGE_BL31
void cm_manage_extensions_el3(void)
{
- pmuv3_disable_el3();
+ if (is_feat_spe_supported()) {
+ spe_init_el3();
+ }
+
+ if (is_feat_sme_supported()) {
+ sme_init_el3();
+ }
+
+ if (is_feat_mpam_supported()) {
+ mpam_init_el3();
+ }
+
+ if (is_feat_trbe_supported()) {
+ trbe_init_el3();
+ }
+
+ if (is_feat_brbe_supported()) {
+ brbe_init_el3();
+ }
+
+ if (is_feat_trf_supported()) {
+ trf_init_el3();
+ }
+
+ pmuv3_init_el3();
}
#endif /* IMAGE_BL31 */
@@ -562,6 +553,19 @@
static void manage_extensions_nonsecure(cpu_context_t *ctx)
{
#if IMAGE_BL31
+ /* Enable SVE and FPU/SIMD */
+ if (is_feat_sve_supported()) {
+ sve_enable(ctx);
+ }
+
+ if (is_feat_sme_supported()) {
+ sme_enable(ctx);
+ }
+
+ if (is_feat_sys_reg_trace_supported()) {
+ sys_reg_trace_enable(ctx);
+ }
+
pmuv3_enable(ctx);
#endif /* IMAGE_BL31 */
}
@@ -573,7 +577,35 @@
static void manage_extensions_nonsecure_el2_unused(void)
{
#if IMAGE_BL31
+ if (is_feat_spe_supported()) {
+ spe_init_el2_unused();
+ }
+
+ if (is_feat_mpam_supported()) {
+ mpam_init_el2_unused();
+ }
+
+ if (is_feat_trbe_supported()) {
+ trbe_init_el2_unused();
+ }
+
+ if (is_feat_sys_reg_trace_supported()) {
+ sys_reg_trace_init_el2_unused();
+ }
+
+ if (is_feat_trf_supported()) {
+ trf_init_el2_unused();
+ }
+
pmuv3_init_el2_unused();
+
+ if (is_feat_sve_supported()) {
+ sve_init_el2_unused();
+ }
+
+ if (is_feat_sme_supported()) {
+ sme_init_el2_unused();
+ }
#endif /* IMAGE_BL31 */
}
@@ -606,6 +638,7 @@
* Enable SME, SVE, FPU/SIMD in secure context, secure manager
* must ensure SME, SVE, and FPU/SIMD context properly managed.
*/
+ sme_init_el3();
sme_enable(ctx);
} else {
/*
@@ -719,24 +752,8 @@
* Initialise CPTR_EL2 setting all fields rather than
* relying on the hw. All fields have architecturally
* UNKNOWN reset values.
- *
- * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1
- * accesses to the CPACR_EL1 or CPACR from both
- * Execution states do not trap to EL2.
- *
- * CPTR_EL2.TTA: Set to zero so that Non-secure System
- * register accesses to the trace registers from both
- * Execution states do not trap to EL2.
- * If PE trace unit System registers are not implemented
- * then this bit is reserved, and must be set to zero.
- *
- * CPTR_EL2.TFP: Set to zero so that Non-secure accesses
- * to SIMD and floating-point functionality from both
- * Execution states do not trap to EL2.
*/
- write_cptr_el2(CPTR_EL2_RESET_VAL &
- ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT
- | CPTR_EL2_TFP_BIT));
+ write_cptr_el2(CPTR_EL2_RESET_VAL);
/*
* Initialise CNTHCTL_EL2. All fields are
@@ -787,16 +804,6 @@
* relying on hw. Some fields are architecturally
* UNKNOWN on reset.
*
- * MDCR_EL2.TTRF: Set to zero so that access to Trace
- * Filter Control register TRFCR_EL1 at EL1 is not
- * trapped to EL2. This bit is RES0 in versions of
- * the architecture earlier than ARMv8.4.
- *
- * MDCR_EL2.TPMS: Set to zero so that accesses to
- * Statistical Profiling control registers from EL1
- * do not trap to EL2. This bit is RES0 when SPE is
- * not implemented.
- *
* MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and
* EL1 System register accesses to the Debug ROM
* registers are not trapped to EL2.
@@ -810,16 +817,10 @@
*
* MDCR_EL2.TDE: Set to zero so that debug exceptions
* are not routed to EL2.
- *
- * MDCR_EL2.E2TB: Set to zero so that the trace Buffer
- * owning exception level is NS-EL1 and, tracing is
- * prohibited at NS-EL2. These bits are RES0 when
- * FEAT_TRBE is not implemented.
*/
- mdcr_el2 = ((MDCR_EL2_RESET_VAL) & ~(MDCR_EL2_TTRF |
- MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT |
- MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT |
- MDCR_EL2_E2TB(MDCR_EL2_E2TB_EL1)));
+ mdcr_el2 = ((MDCR_EL2_RESET_VAL) &
+ ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT |
+ MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT));
write_mdcr_el2(mdcr_el2);