Revert "Move architecture timer setup to platform-specific code"
This reverts commit 1c297bf015226c182b66498d5a64b8b51c7624f5
because it introduced a bug: the CNTFRQ_EL0 register was no
longer programmed by all CPUs. bl31_platform_setup() function
is invoked only in the cold boot path and consequently only
on the primary cpu.
A subsequent commit will correctly implement the necessary changes
to the counter frequency setup code.
Fixes ARM-software/tf-issues#125
Conflicts:
docs/firmware-design.md
plat/fvp/bl31_plat_setup.c
Change-Id: Ib584ad7ed069707ac04cf86717f836136ad3ab54
diff --git a/plat/fvp/bl31_plat_setup.c b/plat/fvp/bl31_plat_setup.c
index eb137e0..07987e4 100644
--- a/plat/fvp/bl31_plat_setup.c
+++ b/plat/fvp/bl31_plat_setup.c
@@ -30,9 +30,8 @@
#include <platform.h>
#include <fvp_pwrc.h>
-#include <assert.h>
-#include <arch_helpers.h>
#include <console.h>
+#include <bl_common.h>
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
@@ -129,7 +128,6 @@
void bl31_platform_setup()
{
unsigned int reg_val;
- unsigned int counter_base_frequency;
/* Initialize the gic cpu and distributor interfaces */
gic_setup();
@@ -143,15 +141,6 @@
mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL,
(1ull << 31) | (1 << 30) | (7 << 20) | (0 << 16));
- /* Read the frequency from Frequency modes table */
- counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
-
- /* The first entry of the frequency modes table must not be 0 */
- assert(counter_base_frequency != 0);
-
- /* Program the counter frequency */
- write_cntfrq_el0(counter_base_frequency);
-
/* Allow access to the System counter timer module */
reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT);
reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT);