diff --git a/plat/fvp/aarch64/plat_common.c b/plat/fvp/aarch64/plat_common.c
index 099751d..b17093f 100644
--- a/plat/fvp/aarch64/plat_common.c
+++ b/plat/fvp/aarch64/plat_common.c
@@ -130,14 +130,15 @@
  * the platform memory map & initialize the mmu, for the given exception level
  ******************************************************************************/
 #define DEFINE_CONFIGURE_MMU_EL(_el)					\
-	void configure_mmu_el##_el(meminfo_t *mem_layout,		\
+	void configure_mmu_el##_el(unsigned long total_base,		\
+				   unsigned long total_size,		\
 				   unsigned long ro_start,		\
 				   unsigned long ro_limit,		\
 				   unsigned long coh_start,		\
 				   unsigned long coh_limit)		\
 	{								\
-		mmap_add_region(mem_layout->total_base,			\
-				mem_layout->total_size,			\
+		mmap_add_region(total_base,				\
+				total_size,				\
 				MT_MEMORY | MT_RW | MT_SECURE);		\
 		mmap_add_region(ro_start, ro_limit - ro_start,		\
 				MT_MEMORY | MT_RO | MT_SECURE);		\
diff --git a/plat/fvp/bl1_plat_setup.c b/plat/fvp/bl1_plat_setup.c
index ac3b69a..76d6963 100644
--- a/plat/fvp/bl1_plat_setup.c
+++ b/plat/fvp/bl1_plat_setup.c
@@ -138,7 +138,8 @@
 		cci_enable_coherency(read_mpidr());
 	}
 
-	configure_mmu_el3(&bl1_tzram_layout,
+	configure_mmu_el3(bl1_tzram_layout.total_base,
+			  bl1_tzram_layout.total_size,
 			  TZROM_BASE,
 			  TZROM_BASE + TZROM_SIZE,
 			  BL1_COHERENT_RAM_BASE,
diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_plat_setup.c
index 1eb8001..3d02c5c 100644
--- a/plat/fvp/bl2_plat_setup.c
+++ b/plat/fvp/bl2_plat_setup.c
@@ -78,7 +78,6 @@
  * to BL31
  ******************************************************************************/
 static bl31_params_t *bl2_to_bl31_params;
-static bl31_plat_params_t *bl2_to_bl31_plat_params;
 static entry_point_info_t *bl31_ep_info;
 
 meminfo_t *bl2_plat_sec_mem_layout(void)
@@ -116,9 +115,6 @@
 	bl2_to_bl31_params = &bl31_params_mem->bl31_params;
 	SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
 
-	/* Assign memory for platform specific information */
-	bl2_to_bl31_plat_params = &bl31_params_mem->bl31_plat_params;
-
 	/* Fill BL31 related information */
 	bl31_ep_info = &bl31_params_mem->bl31_ep_info;
 	bl2_to_bl31_params->bl31_image_info = &bl31_params_mem->bl31_image_info;
@@ -136,18 +132,6 @@
 		SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info,
 					PARAM_IMAGE_BINARY,
 					VERSION_1, 0);
-		/*
-		 * Populate the extents of memory available for loading BL32.
-		 * TODO: We are temporarily executing BL2 from TZDRAM;
-		 * will eventually move to Trusted SRAM
-		 */
-		bl2_to_bl31_plat_params->bl32_meminfo.total_base = BL32_BASE;
-		bl2_to_bl31_plat_params->bl32_meminfo.free_base = BL32_BASE;
-		bl2_to_bl31_plat_params->bl32_meminfo.total_size =
-			(TZDRAM_BASE + TZDRAM_SIZE) - BL32_BASE;
-		bl2_to_bl31_plat_params->bl32_meminfo.free_size =
-			(TZDRAM_BASE + TZDRAM_SIZE) - BL32_BASE;
-		bl2_to_bl31_plat_params->bl32_meminfo.attr = BOT_LOAD;
 	}
 
 	/* Fill BL33 related information */
@@ -157,23 +141,10 @@
 	bl2_to_bl31_params->bl33_image_info = &bl31_params_mem->bl33_image_info;
 	SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
 					VERSION_1, 0);
-	/* Populate the extents of memory available for loading BL33 */
-	bl2_to_bl31_plat_params->bl33_meminfo.total_base = DRAM_BASE;
-	bl2_to_bl31_plat_params->bl33_meminfo.total_size = DRAM_SIZE;
-	bl2_to_bl31_plat_params->bl33_meminfo.free_base = DRAM_BASE;
-	bl2_to_bl31_plat_params->bl33_meminfo.free_size = DRAM_SIZE;
 
 	return bl2_to_bl31_params;
 }
 
-/*******************************************************************************
- * This function returns a pointer to the memory that the platform has kept
- * aside to pass platform related information that BL31 could need
- ******************************************************************************/
-bl31_plat_params_t *bl2_plat_get_bl31_plat_params(void)
-{
-	return bl2_to_bl31_plat_params;
-}
 
 /*******************************************************************************
  * This function returns a pointer to the shared memory that the platform
@@ -239,7 +210,8 @@
  ******************************************************************************/
 void bl2_plat_arch_setup()
 {
-	configure_mmu_el1(&bl2_tzram_layout,
+	configure_mmu_el1(bl2_tzram_layout.total_base,
+			  bl2_tzram_layout.total_size,
 			  BL2_RO_BASE,
 			  BL2_RO_LIMIT,
 			  BL2_COHERENT_RAM_BASE,
@@ -308,3 +280,38 @@
 					DISABLE_ALL_EXCEPTIONS);
 	SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
 }
+
+
+/*******************************************************************************
+ * Populate the extents of memory available for loading BL32
+ ******************************************************************************/
+void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
+{
+	/*
+	 * Populate the extents of memory available for loading BL32.
+	 * TODO: We are temporarily executing BL2 from TZDRAM;
+	 * will eventually move to Trusted SRAM
+	 */
+	bl32_meminfo->total_base = BL32_BASE;
+	bl32_meminfo->free_base = BL32_BASE;
+	bl32_meminfo->total_size =
+			(TZDRAM_BASE + TZDRAM_SIZE) - BL32_BASE;
+	bl32_meminfo->free_size =
+			(TZDRAM_BASE + TZDRAM_SIZE) - BL32_BASE;
+	bl32_meminfo->attr = BOT_LOAD;
+	bl32_meminfo->next = 0;
+}
+
+
+/*******************************************************************************
+ * Populate the extents of memory available for loading BL33
+ ******************************************************************************/
+void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
+{
+	bl33_meminfo->total_base = DRAM_BASE;
+	bl33_meminfo->total_size = DRAM_SIZE;
+	bl33_meminfo->free_base = DRAM_BASE;
+	bl33_meminfo->free_size = DRAM_SIZE;
+	bl33_meminfo->attr = 0;
+	bl33_meminfo->attr = 0;
+}
diff --git a/plat/fvp/bl31_plat_setup.c b/plat/fvp/bl31_plat_setup.c
index 83072e4..949b156 100644
--- a/plat/fvp/bl31_plat_setup.c
+++ b/plat/fvp/bl31_plat_setup.c
@@ -72,17 +72,6 @@
  * BL31 from BL2.
  ******************************************************************************/
 static bl31_params_t *bl2_to_bl31_params;
-static bl31_plat_params_t *bl2_to_bl31_plat_params;
-
-meminfo_t *bl31_plat_sec_mem_layout(void)
-{
-	return &bl2_to_bl31_plat_params->bl31_meminfo;
-}
-
-meminfo_t *bl31_plat_get_bl32_mem_layout(void)
-{
-	return &bl2_to_bl31_plat_params->bl32_meminfo;
-}
 
 /*******************************************************************************
  * Return a pointer to the 'entry_point_info' structure of the next image for the
@@ -117,14 +106,12 @@
  * data
  ******************************************************************************/
 void bl31_early_platform_setup(bl31_params_t *from_bl2,
-			       bl31_plat_params_t *plat_info_from_bl2)
+				void *plat_params_from_bl2)
 {
 	assert(from_bl2->h.type == PARAM_BL31);
 	assert(from_bl2->h.version >= VERSION_1);
 
 	bl2_to_bl31_params = from_bl2;
-	bl2_to_bl31_plat_params = plat_info_from_bl2;
-
 
 	/* Initialize the console to provide early debug support */
 	console_init(PL011_UART0_BASE);
@@ -179,7 +166,8 @@
  ******************************************************************************/
 void bl31_plat_arch_setup()
 {
-	configure_mmu_el3(&bl2_to_bl31_plat_params->bl31_meminfo,
+	configure_mmu_el3(TZRAM_BASE,
+			  TZRAM_SIZE,
 			  BL31_RO_BASE,
 			  BL31_RO_LIMIT,
 			  BL31_COHERENT_RAM_BASE,
diff --git a/plat/fvp/bl32_plat_setup.c b/plat/fvp/bl32_plat_setup.c
index bb2b602..8406d31 100644
--- a/plat/fvp/bl32_plat_setup.c
+++ b/plat/fvp/bl32_plat_setup.c
@@ -63,38 +63,16 @@
 #define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
 #define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
 
-/* Data structure which holds the extents of the trusted SRAM for BL32 */
-static meminfo_t bl32_tzdram_layout
-__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
-		section("tzfw_coherent_mem")));
-
-meminfo_t *bl32_plat_sec_mem_layout(void)
-{
-	return &bl32_tzdram_layout;
-}
-
 /*******************************************************************************
- * BL1 has passed the extents of the trusted SRAM that's at BL32's disposal.
- * Initialize the BL32 data structure with the memory extends and initialize
- * the UART
+ * Initialize the UART
  ******************************************************************************/
-void bl32_early_platform_setup(meminfo_t *mem_layout,
-			      void *data)
+void bl32_early_platform_setup(void)
 {
 	/*
 	 * Initialize a different console than already in use to display
 	 * messages from TSP
 	 */
 	console_init(PL011_UART1_BASE);
-
-	/* Setup the BL32 memory layout */
-	bl32_tzdram_layout.total_base = mem_layout->total_base;
-	bl32_tzdram_layout.total_size = mem_layout->total_size;
-	bl32_tzdram_layout.free_base = mem_layout->free_base;
-	bl32_tzdram_layout.free_size = mem_layout->free_size;
-	bl32_tzdram_layout.attr = mem_layout->attr;
-	bl32_tzdram_layout.next = 0;
-
 }
 
 /*******************************************************************************
@@ -111,7 +89,8 @@
  ******************************************************************************/
 void bl32_plat_arch_setup()
 {
-	configure_mmu_el1(&bl32_tzdram_layout,
+	configure_mmu_el1(BL32_RO_BASE,
+			  (BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE),
 			  BL32_RO_BASE,
 			  BL32_RO_LIMIT,
 			  BL32_COHERENT_RAM_BASE,
diff --git a/plat/fvp/platform.h b/plat/fvp/platform.h
index 85a74bc..50f1124 100644
--- a/plat/fvp/platform.h
+++ b/plat/fvp/platform.h
@@ -356,7 +356,6 @@
 struct plat_pm_ops;
 struct meminfo;
 struct bl31_params;
-struct bl31_plat_params;
 struct image_info;
 struct entry_point_info;
 
@@ -364,11 +363,10 @@
 /*******************************************************************************
  * This structure represents the superset of information that is passed to
  * BL31 e.g. while passing control to it from BL2 which is bl31_params
- * and bl31_plat_params and its elements
+ * and another platform specific params
  ******************************************************************************/
 typedef struct bl2_to_bl31_params_mem {
 	struct bl31_params bl31_params;
-	struct bl31_plat_params bl31_plat_params;
 	struct image_info bl31_image_info;
 	struct image_info bl32_image_info;
 	struct image_info bl33_image_info;
@@ -401,12 +399,14 @@
 extern unsigned int platform_get_core_pos(unsigned long mpidr);
 extern void enable_mmu_el1(void);
 extern void enable_mmu_el3(void);
-extern void configure_mmu_el1(struct meminfo *mem_layout,
+extern void configure_mmu_el1(unsigned long total_base,
+			      unsigned long total_size,
 			      unsigned long ro_start,
 			      unsigned long ro_limit,
 			      unsigned long coh_start,
 			      unsigned long coh_limit);
-extern void configure_mmu_el3(struct meminfo *mem_layout,
+extern void configure_mmu_el3(unsigned long total_base,
+			      unsigned long total_size,
 			      unsigned long ro_start,
 			      unsigned long ro_limit,
 			      unsigned long coh_start,
@@ -474,6 +474,12 @@
 extern void bl2_plat_set_bl33_ep_info(struct image_info *image,
 					struct entry_point_info *ep);
 
+/* Gets the memory layout for BL32 */
+extern void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info);
+
+/* Gets the memory layout for BL33 */
+extern void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info);
+
 
 #endif /*__ASSEMBLY__*/