feat(the): add support for FEAT_THE
Arm v8.9 introduces FEAT_THE, adding Translation Hardening Extension
Read-Check-Write mask registers, RCWMASK_EL1 and RCWSMASK_EL1.
Support this, context switching the registers and disabling
traps so lower ELs can access the new registers.
Change the FVP platform to default to handling this as a dynamic option
so the right decision can be made by the code at runtime.
Change-Id: I8775787f523639b39faf61d046ef482f73b2a562
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/include/lib/el3_runtime/context_el1.h b/include/lib/el3_runtime/context_el1.h
index 038de25..ab3be63 100644
--- a/include/lib/el3_runtime/context_el1.h
+++ b/include/lib/el3_runtime/context_el1.h
@@ -107,6 +107,11 @@
uint64_t gcspr_el0;
} el1_gcs_regs_t;
+typedef struct el1_the_regs {
+ uint64_t rcwmask_el1;
+ uint64_t rcwsmask_el1;
+} el1_the_regs_t;
+
typedef struct el1_sysregs {
el1_common_regs_t common;
@@ -155,6 +160,10 @@
el1_gcs_regs_t gcs;
#endif
+#if ENABLE_FEAT_THE
+ el1_the_regs_t the;
+#endif
+
} el1_sysregs_t;
@@ -266,6 +275,16 @@
#define read_el1_ctx_gcs(ctx, reg) ULL(0)
#define write_el1_ctx_gcs(ctx, reg, val)
#endif /* ENABLE_FEAT_GCS */
+
+#if ENABLE_FEAT_THE
+#define read_el1_ctx_the(ctx, reg) (((ctx)->the).reg)
+#define write_el1_ctx_the(ctx, reg, val) ((((ctx)->the).reg) \
+ = (uint64_t) (val))
+#else
+#define read_el1_ctx_the(ctx, reg) ULL(0)
+#define write_el1_ctx_the(ctx, reg, val)
+#endif /* ENABLE_FEAT_THE */
+
/******************************************************************************/
#endif /* __ASSEMBLER__ */