fix(cpus): workaround for Cortex-X3 erratum 3701769
Cortex-X3 erratum 3701769 that applies to r0p0, r1p0, r1p1 and r1p2
is still Open.
The workaround is for EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest/
Change-Id: Ifd722e1bb8616ada2ad158297a7ca80b19a3370b
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c
index 5dbc50d..f61d6e8 100644
--- a/lib/cpus/errata_common.c
+++ b/lib/cpus/errata_common.c
@@ -16,6 +16,7 @@
#include <cortex_a720_ae.h>
#include <cortex_a725.h>
#include <cortex_x2.h>
+#include <cortex_x3.h>
#include <cortex_x4.h>
#include <lib/cpus/cpu_ops.h>
#include <lib/cpus/errata.h>
@@ -92,6 +93,13 @@
break;
#endif /* ERRATA_X2_3701772 */
+#if ERRATA_X3_3701769
+ case EXTRACT_PARTNUM(CORTEX_X3_MIDR):
+ if (check_erratum_cortex_x3_3701769(cpu_get_rev_var()) == ERRATA_APPLIES)
+ return true;
+ break;
+#endif /* ERRATA_X3_3701769 */
+
default:
break;
}