diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index 073c157..e94b32a 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -62,11 +62,22 @@
 #define ARM_SHARED_RAM_BASE		ARM_TRUSTED_SRAM_BASE
 #define ARM_SHARED_RAM_SIZE		UL(0x00001000)	/* 4 KB */
 
+#if ENABLE_RME
+/* Store level 0 GPT at the top of the Trusted SRAM */
+#define ARM_L0_GPT_BASE			(ARM_TRUSTED_SRAM_BASE + \
+					 PLAT_ARM_TRUSTED_SRAM_SIZE - \
+					 ARM_L0_GPT_SIZE)
+#define ARM_L0_GPT_SIZE			UL(0x00001000)	/* 4 KB */
+#else
+#define ARM_L0_GPT_SIZE			UL(0)
+#endif
+
 /* The remaining Trusted SRAM is used to load the BL images */
-#define ARM_BL_RAM_BASE			(ARM_SHARED_RAM_BASE +	\
+#define ARM_BL_RAM_BASE			(ARM_SHARED_RAM_BASE + \
 					 ARM_SHARED_RAM_SIZE)
-#define ARM_BL_RAM_SIZE			(PLAT_ARM_TRUSTED_SRAM_SIZE -	\
-					 ARM_SHARED_RAM_SIZE)
+#define ARM_BL_RAM_SIZE			(PLAT_ARM_TRUSTED_SRAM_SIZE - \
+					 ARM_SHARED_RAM_SIZE - \
+					 ARM_L0_GPT_SIZE)
 
 /*
  * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as
@@ -355,7 +366,6 @@
 					ARM_EL3_RMM_SHARED_BASE,	\
 					ARM_EL3_RMM_SHARED_SIZE,	\
 					MT_MEMORY | MT_RW | MT_REALM)
-
 #endif /* ENABLE_RME */
 
 /*
@@ -543,18 +553,6 @@
 #define ARM_FW_CONFIGS_LIMIT		(ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE)
 #endif
 
-#if ENABLE_RME
-/*
- * Store the L0 GPT on Trusted SRAM next to firmware
- * configuration memory, 4KB aligned.
- */
-#define ARM_L0_GPT_SIZE			(PAGE_SIZE)
-#define ARM_L0_GPT_BASE			(ARM_FW_CONFIGS_LIMIT)
-#define ARM_L0_GPT_LIMIT		(ARM_L0_GPT_BASE + ARM_L0_GPT_SIZE)
-#else
-#define ARM_L0_GPT_SIZE			U(0)
-#endif
-
 /*******************************************************************************
  * BL1 specific defines.
  * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
@@ -570,7 +568,8 @@
 #endif
 
 /*
- * Put BL1 RW at the top of the Trusted SRAM.
+ * With ENABLE_RME=1 put BL1 RW below L0 GPT,
+ * or at the top of Trusted SRAM otherwise.
  */
 #define BL1_RW_BASE			(ARM_BL_RAM_BASE +		\
 						ARM_BL_RAM_SIZE -	\
diff --git a/plat/arm/board/fvp/fdts/fvp_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
index 5d58731..a11c1de 100644
--- a/plat/arm/board/fvp/fdts/fvp_fw_config.dts
+++ b/plat/arm/board/fvp/fdts/fvp_fw_config.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2025, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,6 +7,10 @@
 #include <common/tbbr/tbbr_img_def.h>
 #include <platform_def.h>
 
+/* DTB load addresses */
+#define TB_SOC_FW_ADDR	(ARM_BL_RAM_BASE + 0x300)
+#define TOS_FW_ADDR	(ARM_BL_RAM_BASE + 0x500)
+
 /dts-v1/;
 
 / {
@@ -14,7 +18,7 @@
 		compatible = "fconf,dyn_cfg-dtb_registry";
 
 		tb_fw-config {
-			load-address = <0x0 0x4001300>;
+			load-address = <0x0 TB_SOC_FW_ADDR>;
 			max-size = <0x1800>;
 			id = <TB_FW_CONFIG_ID>;
 		};
@@ -33,7 +37,7 @@
 		 * is loaded at base of DRAM.
 		 */
 		soc_fw-config {
-			load-address = <0x0 0x04001300>;
+			load-address = <0x0 TB_SOC_FW_ADDR>;
 			max-size = <0x200>;
 			id = <SOC_FW_CONFIG_ID>;
 		};
@@ -41,8 +45,7 @@
 /* If required, SPD should enable loading of trusted OS fw config */
 #if defined(SPD_tspd) || defined(SPD_spmd)
 		tos_fw-config {
-
-			load-address = <0x0 0x04001500>;
+			load-address = <0x0 TOS_FW_ADDR>;
 #if ENABLE_RME
 			secondary-load-address = <0x0 0x7e00000>;
 #endif /* ENABLE_RME */
@@ -50,7 +53,6 @@
 			id = <TOS_FW_CONFIG_ID>;
 		};
 #endif
-
 		nt_fw-config {
 			load-address = <0x0 0x80000000>;
 			max-size = <0x200>;
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
index 7fa2b77..4936344 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
@@ -507,8 +507,6 @@
 #define ARM_L0_GPT_BASE			NRD_CSS_SHARED_SRAM_SIZE -	\
 					ARM_L0_GPT_SIZE
 
-#define ARM_L0_GPT_LIMIT		(ARM_L0_GPT_BASE + ARM_L0_GPT_SIZE)
-
 /*******************************************************************************
  * Arm shared RAM specifics
  ******************************************************************************/