diff --git a/plat/fvp/aarch64/bl1_plat_helpers.S b/plat/fvp/aarch64/bl1_plat_helpers.S
index 8cdb10e..0adb541 100644
--- a/plat/fvp/aarch64/bl1_plat_helpers.S
+++ b/plat/fvp/aarch64/bl1_plat_helpers.S
@@ -38,7 +38,7 @@
 	.globl	plat_secondary_cold_boot_setup
 
 
-	.section	platform_code, "ax"; .align 3
+	.section	.text, "ax"; .align 3
 
 
 	.macro	platform_choose_gicmmap  param1, param2, x_tmp, w_tmp, res
diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c
index 0b5f4eb..fd0e073 100644
--- a/plat/fvp/aarch64/fvp_common.c
+++ b/plat/fvp/aarch64/fvp_common.c
@@ -367,8 +367,6 @@
 
 	/*****************************************************************
 	 * LEVEL3 PAGETABLE SETUP
-	 * The following setup assumes knowledge of the scatter file. This
-	 * should be reasonable as this is platform specific code.
 	 *****************************************************************/
 
 	/* Fill up the level3 pagetable for the trusted SRAM. */
@@ -378,21 +376,13 @@
 	if (tzram_end_index == tzram_start_index)
 		tzram_end_index++;
 
-	/*
-	 * Reusing trom* to mark RO memory. BLX_STACKS follows BLX_RO in the
-	 * scatter file. Using BLX_RO$$Limit does not work as it might not
-	 * cross the page boundary thus leading to truncation of valid RO
-	 * memory
-	 */
+	/* Reusing trom* to mark RO memory. */
 	trom_start_index = FOUR_KB_INDEX(ro_start);
 	trom_end_index = FOUR_KB_INDEX(ro_limit);
 	if (trom_end_index == trom_start_index)
 		trom_end_index++;
 
-	/*
-	 * Reusing dev* to mark coherent device memory. $$Limit works here
-	 * 'cause the coherent memory section is known to be 4k in size
-	 */
+	/* Reusing dev* to mark coherent device memory. */
 	dev0_start_index = FOUR_KB_INDEX(coh_start);
 	dev0_end_index = FOUR_KB_INDEX(coh_limit);
 	if (dev0_end_index == dev0_start_index)
@@ -506,6 +496,11 @@
 		   unsigned long coh_start,
 		   unsigned long coh_limit)
 {
+	assert(IS_PAGE_ALIGNED(ro_start));
+	assert(IS_PAGE_ALIGNED(ro_limit));
+	assert(IS_PAGE_ALIGNED(coh_start));
+	assert(IS_PAGE_ALIGNED(coh_limit));
+
 	fill_xlation_tables(mem_layout,
 			    ro_start,
 			    ro_limit,
diff --git a/plat/fvp/aarch64/fvp_helpers.S b/plat/fvp/aarch64/fvp_helpers.S
index 250149b..7a893d0 100644
--- a/plat/fvp/aarch64/fvp_helpers.S
+++ b/plat/fvp/aarch64/fvp_helpers.S
@@ -33,7 +33,7 @@
 
 	.globl	plat_report_exception
 
-	.section platform_code, "ax"
+	.section	.text, "ax"
 
 	/* ---------------------------------------------
 	 * void plat_report_exception(unsigned int type)
diff --git a/plat/fvp/bl1_plat_setup.c b/plat/fvp/bl1_plat_setup.c
index 434dfb7..74b79d1 100644
--- a/plat/fvp/bl1_plat_setup.c
+++ b/plat/fvp/bl1_plat_setup.c
@@ -40,46 +40,27 @@
  * Declarations of linker defined symbols which will help us find the layout
  * of trusted SRAM
  ******************************************************************************/
-#if defined (__GNUC__)
-extern unsigned long __FIRMWARE_ROM_START__;
-extern unsigned long __FIRMWARE_ROM_SIZE__;
-extern unsigned long __FIRMWARE_DATA_START__;
-extern unsigned long __FIRMWARE_DATA_SIZE__;
-extern unsigned long __FIRMWARE_BSS_START__;
-extern unsigned long __FIRMWARE_BSS_SIZE__;
-extern unsigned long __DATA_RAM_START__;
-extern unsigned long __DATA_RAM_SIZE__;
-extern unsigned long __BSS_RAM_START__;
-extern unsigned long __BSS_RAM_SIZE__;
-extern unsigned long __FIRMWARE_RAM_STACKS_START__;
-extern unsigned long __FIRMWARE_RAM_STACKS_SIZE__;
-extern unsigned long __FIRMWARE_RAM_PAGETABLES_START__;
-extern unsigned long __FIRMWARE_RAM_PAGETABLES_SIZE__;
-extern unsigned long __FIRMWARE_RAM_COHERENT_START__;
-extern unsigned long __FIRMWARE_RAM_COHERENT_SIZE__;
+extern unsigned long __COHERENT_RAM_START__;
+extern unsigned long __COHERENT_RAM_END__;
+extern unsigned long __COHERENT_RAM_UNALIGNED_SIZE__;
 
-#define BL1_COHERENT_MEM_BASE	(&__FIRMWARE_RAM_COHERENT_START__)
-#define BL1_COHERENT_MEM_LIMIT \
-	((unsigned long long)&__FIRMWARE_RAM_COHERENT_START__ + \
-	 (unsigned long long)&__FIRMWARE_RAM_COHERENT_SIZE__)
+extern unsigned long __BL1_RAM_START__;
+extern unsigned long __BL1_RAM_END__;
 
-#define BL1_FIRMWARE_RAM_GLOBALS_ZI_BASE \
-	(unsigned long)(&__BSS_RAM_START__)
-#define BL1_FIRMWARE_RAM_GLOBALS_ZI_LENGTH \
-	(unsigned long)(&__FIRMWARE_BSS_SIZE__)
+/*
+ * The next 2 constants identify the extents of the coherent memory region.
+ * These addresses are used by the MMU setup code and therefore they must be
+ * page-aligned.  It is the responsibility of the linker script to ensure that
+ * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
+ * page-aligned addresses.
+ */
+#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
+#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
+#define BL1_COHERENT_RAM_LENGTH \
+	(unsigned long)(&__COHERENT_RAM_UNALIGNED_SIZE__)
 
-#define BL1_FIRMWARE_RAM_COHERENT_ZI_BASE \
-	(unsigned long)(&__FIRMWARE_RAM_COHERENT_START__)
-#define BL1_FIRMWARE_RAM_COHERENT_ZI_LENGTH\
-	(unsigned long)(&__FIRMWARE_RAM_COHERENT_SIZE__)
-
-#define BL1_NORMAL_RAM_BASE (unsigned long)(&__BSS_RAM_START__)
-#define BL1_NORMAL_RAM_LIMIT \
-	((unsigned long)&__FIRMWARE_RAM_COHERENT_START__ +	\
-	 (unsigned long)&__FIRMWARE_RAM_COHERENT_SIZE__)
-#else
- #error "Unknown compiler."
-#endif
+#define BL1_RAM_BASE (unsigned long)(&__BL1_RAM_START__)
+#define BL1_RAM_LIMIT (unsigned long)(&__BL1_RAM_END__)
 
 
 /* Data structure which holds the extents of the trusted SRAM for BL1*/
@@ -95,16 +76,9 @@
  ******************************************************************************/
 void bl1_early_platform_setup(void)
 {
-	unsigned long bl1_normal_ram_base;
-	unsigned long bl1_coherent_ram_limit;
-	unsigned long tzram_limit = TZRAM_BASE + TZRAM_SIZE;
-
-	/*
-	 * Initialize extents of the bl1 sections as per the platform
-	 * defined values.
-	 */
-	bl1_normal_ram_base  = BL1_NORMAL_RAM_BASE;
-	bl1_coherent_ram_limit = BL1_NORMAL_RAM_LIMIT;
+	const unsigned long bl1_ram_base = BL1_RAM_BASE;
+	const unsigned long bl1_ram_limit = BL1_RAM_LIMIT;
+	const unsigned long tzram_limit = TZRAM_BASE + TZRAM_SIZE;
 
 	/*
 	 * Calculate how much ram is BL1 using & how much remains free.
@@ -113,19 +87,19 @@
 	 * TODO: add support for discontigous chunks of free ram if
 	 *       needed. Might need dynamic memory allocation support
 	 *       et al.
-	 *       Also assuming that the section for coherent memory is
-	 *       the last and for globals the first in the scatter file.
 	 */
 	bl1_tzram_layout.total_base = TZRAM_BASE;
 	bl1_tzram_layout.total_size = TZRAM_SIZE;
 
-	if (bl1_coherent_ram_limit == tzram_limit) {
+	if (bl1_ram_limit == tzram_limit) {
+		/* BL1 has been loaded at the top of memory. */
 		bl1_tzram_layout.free_base = TZRAM_BASE;
-		bl1_tzram_layout.free_size = bl1_normal_ram_base - TZRAM_BASE;
+		bl1_tzram_layout.free_size = bl1_ram_base - TZRAM_BASE;
 	} else {
-		bl1_tzram_layout.free_base = bl1_coherent_ram_limit;
+		/* BL1 has been loaded at the bottom of memory. */
+		bl1_tzram_layout.free_base = bl1_ram_limit;
 		bl1_tzram_layout.free_size =
-			tzram_limit - bl1_coherent_ram_limit;
+			tzram_limit - bl1_ram_limit;
 	}
 
 	/* Initialize the platform config for future decision making */
@@ -143,8 +117,8 @@
 	 * This should zero out our coherent stacks as well but we don't care
 	 * as they are not being used right now.
 	 */
-	memset((void *) BL1_FIRMWARE_RAM_COHERENT_ZI_BASE, 0,
-	       (size_t) BL1_FIRMWARE_RAM_COHERENT_ZI_LENGTH);
+	memset((void *) BL1_COHERENT_RAM_BASE, 0,
+	       (size_t) BL1_COHERENT_RAM_LENGTH);
 
 	/* Enable and initialize the System level generic timer */
 	mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_EN);
@@ -175,11 +149,8 @@
 	}
 
 	configure_mmu(&bl1_tzram_layout,
-		TZROM_BASE,			/* Read_only region start */
-		TZROM_BASE + TZROM_SIZE,	/* Read_only region size */
-		/* Coherent region start */
-		BL1_FIRMWARE_RAM_COHERENT_ZI_BASE,
-		/* Coherent region size */
-		BL1_FIRMWARE_RAM_COHERENT_ZI_BASE +
-			BL1_FIRMWARE_RAM_COHERENT_ZI_LENGTH);
+	              TZROM_BASE,
+	              TZROM_BASE + TZROM_SIZE,
+	              BL1_COHERENT_RAM_BASE,
+	              BL1_COHERENT_RAM_LIMIT);
 }
diff --git a/plat/fvp/bl2_plat_setup.c b/plat/fvp/bl2_plat_setup.c
index 4fdef8b..bb3b45a 100644
--- a/plat/fvp/bl2_plat_setup.c
+++ b/plat/fvp/bl2_plat_setup.c
@@ -39,20 +39,30 @@
  * Declarations of linker defined symbols which will help us find the layout
  * of trusted SRAM
  ******************************************************************************/
-#if defined (__GNUC__)
-extern unsigned long __BL2_RO_BASE__;
-extern unsigned long __BL2_STACKS_BASE__;
-extern unsigned long __BL2_COHERENT_RAM_BASE__;
-extern unsigned long __BL2_RW_BASE__;
+extern unsigned long __RO_START__;
+extern unsigned long __RO_END__;
 
-#define BL2_RO_BASE		__BL2_RO_BASE__
-#define BL2_STACKS_BASE		__BL2_STACKS_BASE__
-#define BL2_COHERENT_RAM_BASE	__BL2_COHERENT_RAM_BASE__
-#define BL2_RW_BASE		__BL2_RW_BASE__
+extern unsigned long __COHERENT_RAM_START__;
+extern unsigned long __COHERENT_RAM_END__;
 
-#else
- #error "Unknown compiler."
-#endif
+/*
+ * The next 2 constants identify the extents of the code & RO data region.
+ * These addresses are used by the MMU setup code and therefore they must be
+ * page-aligned.  It is the responsibility of the linker script to ensure that
+ * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
+ */
+#define BL2_RO_BASE (unsigned long)(&__RO_START__)
+#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
+
+/*
+ * The next 2 constants identify the extents of the coherent memory region.
+ * These addresses are used by the MMU setup code and therefore they must be
+ * page-aligned.  It is the responsibility of the linker script to ensure that
+ * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
+ * page-aligned addresses.
+ */
+#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
+#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
 
 /* Pointer to memory visible to both BL2 and BL31 for passing data */
 extern unsigned char **bl2_el_change_mem_ptr;
@@ -106,8 +116,8 @@
 void bl2_plat_arch_setup()
 {
 	configure_mmu(&bl2_tzram_layout,
-		      (unsigned long) &BL2_RO_BASE,
-		      (unsigned long) &BL2_STACKS_BASE,
-		      (unsigned long) &BL2_COHERENT_RAM_BASE,
-		      (unsigned long) &BL2_RW_BASE);
+		      BL2_RO_BASE,
+		      BL2_RO_LIMIT,
+		      BL2_COHERENT_RAM_BASE,
+		      BL2_COHERENT_RAM_LIMIT);
 }
diff --git a/plat/fvp/bl31_plat_setup.c b/plat/fvp/bl31_plat_setup.c
index 0dd5c69..47b6d5b 100644
--- a/plat/fvp/bl31_plat_setup.c
+++ b/plat/fvp/bl31_plat_setup.c
@@ -44,20 +44,30 @@
  * Declarations of linker defined symbols which will help us find the layout
  * of trusted SRAM
  ******************************************************************************/
-#if defined (__GNUC__)
-extern unsigned long __BL31_RO_BASE__;
-extern unsigned long __BL31_STACKS_BASE__;
-extern unsigned long __BL31_COHERENT_RAM_BASE__;
-extern unsigned long __BL31_RW_BASE__;
+extern unsigned long __RO_START__;
+extern unsigned long __RO_END__;
 
-#define BL31_RO_BASE		__BL31_RO_BASE__
-#define BL31_STACKS_BASE	__BL31_STACKS_BASE__
-#define BL31_COHERENT_RAM_BASE	__BL31_COHERENT_RAM_BASE__
-#define BL31_RW_BASE		__BL31_RW_BASE__
+extern unsigned long __COHERENT_RAM_START__;
+extern unsigned long __COHERENT_RAM_END__;
 
-#else
- #error "Unknown compiler."
-#endif
+/*
+ * The next 2 constants identify the extents of the code & RO data region.
+ * These addresses are used by the MMU setup code and therefore they must be
+ * page-aligned.  It is the responsibility of the linker script to ensure that
+ * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
+ */
+#define BL31_RO_BASE (unsigned long)(&__RO_START__)
+#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
+
+/*
+ * The next 2 constants identify the extents of the coherent memory region.
+ * These addresses are used by the MMU setup code and therefore they must be
+ * page-aligned.  It is the responsibility of the linker script to ensure that
+ * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
+ * refer to page-aligned addresses.
+ */
+#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
+#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
 
 /*******************************************************************************
  * This data structures holds information copied by BL31 from BL2 to pass
@@ -167,10 +177,10 @@
 void bl31_plat_arch_setup()
 {
 	configure_mmu(&bl31_tzram_layout,
-		      (unsigned long) &BL31_RO_BASE,
-		      (unsigned long) &BL31_STACKS_BASE,
-		      (unsigned long) &BL31_COHERENT_RAM_BASE,
-		      (unsigned long) &BL31_RW_BASE);
+		      BL31_RO_BASE,
+		      BL31_RO_LIMIT,
+		      BL31_COHERENT_RAM_BASE,
+		      BL31_COHERENT_RAM_LIMIT);
 }
 
 /*******************************************************************************