marvell: comphy: update rx_training procedure
1) Relay only on rx training, remove parts responsible for tx training
(trx training).
2) Add extra steps e.g. preconfigure FFE before starting training.
3) Remove some unnecessary steps like RRBS31 loopback setting which
shouldn't be relevant for tx_training.
Change-Id: Ib1e8567714f9ce33578186a262c339aa4b1c51f2
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c
index b682086..3313a42 100644
--- a/drivers/marvell/comphy/phy-comphy-cp110.c
+++ b/drivers/marvell/comphy/phy-comphy-cp110.c
@@ -2012,12 +2012,58 @@
return ret;
}
+static void rx_pre_train(uint64_t comphy_base, uint8_t comphy_index)
+{
+ uintptr_t hpipe_addr;
+ uint32_t mask, data;
+
+ hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
+ comphy_index);
+
+ debug("rx_training preparation\n\n");
+
+ mask = HPIPE_TRX0_GAIN_TRAIN_WITH_C_MASK;
+ data = (0x1 << HPIPE_TRX0_GAIN_TRAIN_WITH_C_OFF);
+ mask |= HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_MASK;
+ data |= (0x0 << HPIPE_TRX0_GAIN_TRAIN_WITH_SAMPLER_OFF);
+ reg_set(hpipe_addr + HPIPE_TRX0_REG, data, mask);
+
+
+ mask = HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK;
+ data = (0x1e << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF);
+ mask |= HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_MASK;
+ data |= (0x0 << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_K_OFF);
+ reg_set(hpipe_addr + HPIPE_TRX_REG2, data, mask);
+
+ mask = HPIPE_TRX_REG1_MIN_BOOST_MODE_MASK;
+ data = (0x1 << HPIPE_TRX_REG1_MIN_BOOST_MODE_OFF);
+ reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask);
+
+ mask = HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_MASK;
+ data = (0x8 << HPIPE_CRD2_CRD_MIDPOINT_SMALL_THRES_K_OFF);
+ reg_set(hpipe_addr + HPIPE_CDR_CONTROL1_REG, data, mask);
+
+ mask = HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_MASK;
+ data = (0x8 << HPIPE_CRD2_CRD_MIDPOINT_LARGE_THRES_K_OFF);
+ reg_set(hpipe_addr + HPIPE_CDR_CONTROL2_REG, data, mask);
+
+ mask = HPIPE_CRD_MIDPOINT_PHASE_OS_MASK;
+ data = (0x0 << HPIPE_CRD_MIDPOINT_PHASE_OS_OFFSET);
+ reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask);
+
+ mask = HPIPE_TRX_REG1_SUMFTAP_EN_MASK;
+ data = (0x38 << HPIPE_TRX_REG1_SUMFTAP_EN_OFF);
+ mask |= HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_MASK;
+ data |= (0x1e << HPIPE_TRX_REG2_SUMF_BOOST_TARGET_C_OFF);
+ reg_set(hpipe_addr + HPIPE_TRX_REG1, data, mask);
+}
+
int mvebu_cp110_comphy_xfi_rx_training(uint64_t comphy_base,
uint8_t comphy_index)
{
uint32_t mask, data, timeout;
uint32_t g1_ffe_cap_sel, g1_ffe_res_sel, align90, g1_dfe_res;
- uintptr_t hpipe_addr, sd_ip_addr;
+ uintptr_t hpipe_addr;
uint8_t ap_nr, cp_nr;
@@ -2025,30 +2071,10 @@
hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
comphy_index);
- sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base),
- comphy_index);
debug_enter();
- debug("stage: RF Reset\n");
-
- /* Release from hard reset */
- mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
- data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
-
- mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
- data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
-
- /* Wait 50ms - until band gap and ref clock ready */
- mdelay(50);
+ rx_pre_train(comphy_base, comphy_index);
debug("Preparation for rx_training\n\n");
@@ -2068,34 +2094,10 @@
data = 0 << HPIPE_DFE_RES_FORCE_OFFSET;
reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
- debug("PRBS31 loppback\n\n");
-
- /* Configure PRBS counters */
- mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
- data = 0xe << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
-
- mask = HPIPE_PHY_TEST_DATA_MASK;
- data = 0xc4 << HPIPE_PHY_TEST_DATA_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_DATA_REG, data, mask);
-
- mask = HPIPE_PHY_TEST_EN_MASK;
- data = 0x1 << HPIPE_PHY_TEST_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
-
- mdelay(10);
- debug("Enable TX/RX training\n\n");
+ debug("Enable RX training\n\n");
mask = HPIPE_TRX_RX_TRAIN_EN_MASK;
data = 0x1 << HPIPE_TRX_RX_TRAIN_EN_OFFSET;
- mask |= HPIPE_TRX_RX_ANA_IF_CLK_ENE_MASK;
- data |= 0x1 << HPIPE_TRX_RX_ANA_IF_CLK_ENE_OFFSET;
- mask |= HPIPE_TRX_TX_CTRL_CLK_EN_MASK;
- data |= 0x1 << HPIPE_TRX_TX_CTRL_CLK_EN_OFFSET;
- mask |= HPIPE_TRX_UPDATE_THEN_HOLD_MASK;
- data |= 0x1 << HPIPE_TRX_UPDATE_THEN_HOLD_OFFSET;
- mask |= HPIPE_TRX_TX_F0T_EO_BASED_MASK;
- data |= 0x1 << HPIPE_TRX_TX_F0T_EO_BASED_OFFSET;
reg_set(hpipe_addr + HPIPE_TRX_TRAIN_CTRL_0_REG, data, mask);
/* Check the result of RX training */
@@ -2180,21 +2182,9 @@
data = 1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
- /* Use the value from CAL_OS_PH_EXT */
- mask = HPIPE_CAL_RXCLKALIGN_90_EXT_EN_MASK;
- data = 1 << HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG,
- data, mask);
-
- /* Update align90 */
- mask = HPIPE_CAL_OS_PH_EXT_MASK;
- data = align90 << HPIPE_CAL_OS_PH_EXT_OFFSET;
- reg_set(hpipe_addr + HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG,
- data, mask);
-
/* Force DFE resolution (use gen table value) */
mask = HPIPE_DFE_RES_FORCE_MASK;
- data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
+ data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET;
reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
/* 0x111-G1 DFE_Setting_4 */
@@ -2202,38 +2192,6 @@
data = g1_dfe_res << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
- debug("PRBS31 loppback\n\n");
-
- mask = HPIPE_PHY_TEST_PT_TESTMODE_MASK;
- data = 0x1 << HPIPE_PHY_TEST_PT_TESTMODE_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_OOB_0_REGISTER, data, mask);
-
- /* Configure PRBS counters */
- mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
- data = 0xe << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
-
- mask = HPIPE_PHY_TEST_DATA_MASK;
- data = 0xc4 << HPIPE_PHY_TEST_DATA_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_DATA_REG, data, mask);
-
- mask = HPIPE_PHY_TEST_EN_MASK;
- data = 0x1 << HPIPE_PHY_TEST_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
-
- /* Reset PRBS error counter */
- mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
- data = 0x1 << HPIPE_PHY_TEST_RESET_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
-
- mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
- data = 0x0 << HPIPE_PHY_TEST_RESET_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
-
- mask = HPIPE_PHY_TEST_PT_TESTMODE_MASK;
- data = 0x1 << HPIPE_PHY_TEST_PT_TESTMODE_OFFSET;
- reg_set(hpipe_addr + HPIPE_PHY_TEST_OOB_0_REGISTER, data, mask);
-
printf("########################################################\n");
printf("# To use trained values update the ATF sources:\n");
printf("# plat/marvell/armada/a8k/<board_type>/board/phy-porting-layer.h ");
@@ -2252,12 +2210,6 @@
printf("};\n\n");
printf("########################################################\n");
- /* check */
- debug("PRBS error counter[0x%lx] 0x%x\n\n",
- hpipe_addr + HPIPE_PHY_TEST_PRBS_ERROR_COUNTER_1_REG,
- mmio_read_32(hpipe_addr +
- HPIPE_PHY_TEST_PRBS_ERROR_COUNTER_1_REG));
-
rx_trainng_done[ap_nr][cp_nr][comphy_index] = 1;
return 0;