tree 8d894f2bf5d5e3ec7d29ca270169c2c37457e814
parent 5f5d1ed7d5a7626b2da48f3ac423d366bbee1fd8
author Louis Mayencourt <louis.mayencourt@arm.com> 1551106677 +0000
committer Louis Mayencourt <louis.mayencourt@arm.com> 1551198059 +0000

Add workaround for errata 790748 for Cortex-A75

Internal timing conditions might cause the CPU to stop processing
interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this.

Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>